1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Fifo-attached Serial Interface (FSI) support for SH7724 4 // 5 // Copyright (C) 2009 Renesas Solutions Corp. 6 // Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 // 8 // Based on ssi.c 9 // Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 10 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/scatterlist.h> 18 #include <linux/sh_dma.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/workqueue.h> 22 #include <sound/soc.h> 23 #include <sound/pcm_params.h> 24 #include <sound/sh_fsi.h> 25 26 /* PortA/PortB register */ 27 #define REG_DO_FMT 0x0000 28 #define REG_DOFF_CTL 0x0004 29 #define REG_DOFF_ST 0x0008 30 #define REG_DI_FMT 0x000C 31 #define REG_DIFF_CTL 0x0010 32 #define REG_DIFF_ST 0x0014 33 #define REG_CKG1 0x0018 34 #define REG_CKG2 0x001C 35 #define REG_DIDT 0x0020 36 #define REG_DODT 0x0024 37 #define REG_MUTE_ST 0x0028 38 #define REG_OUT_DMAC 0x002C 39 #define REG_OUT_SEL 0x0030 40 #define REG_IN_DMAC 0x0038 41 42 /* master register */ 43 #define MST_CLK_RST 0x0210 44 #define MST_SOFT_RST 0x0214 45 #define MST_FIFO_SZ 0x0218 46 47 /* core register (depend on FSI version) */ 48 #define A_MST_CTLR 0x0180 49 #define B_MST_CTLR 0x01A0 50 #define CPU_INT_ST 0x01F4 51 #define CPU_IEMSK 0x01F8 52 #define CPU_IMSK 0x01FC 53 #define INT_ST 0x0200 54 #define IEMSK 0x0204 55 #define IMSK 0x0208 56 57 /* DO_FMT */ 58 /* DI_FMT */ 59 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */ 60 #define CR_BWS_24 (0x0 << 20) /* FSI2 */ 61 #define CR_BWS_16 (0x1 << 20) /* FSI2 */ 62 #define CR_BWS_20 (0x2 << 20) /* FSI2 */ 63 64 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ 65 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ 66 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ 67 68 #define CR_MONO (0x0 << 4) 69 #define CR_MONO_D (0x1 << 4) 70 #define CR_PCM (0x2 << 4) 71 #define CR_I2S (0x3 << 4) 72 #define CR_TDM (0x4 << 4) 73 #define CR_TDM_D (0x5 << 4) 74 75 /* OUT_DMAC */ 76 /* IN_DMAC */ 77 #define VDMD_MASK (0x3 << 4) 78 #define VDMD_FRONT (0x0 << 4) /* Package in front */ 79 #define VDMD_BACK (0x1 << 4) /* Package in back */ 80 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ 81 82 #define DMA_ON (0x1 << 0) 83 84 /* DOFF_CTL */ 85 /* DIFF_CTL */ 86 #define IRQ_HALF 0x00100000 87 #define FIFO_CLR 0x00000001 88 89 /* DOFF_ST */ 90 #define ERR_OVER 0x00000010 91 #define ERR_UNDER 0x00000001 92 #define ST_ERR (ERR_OVER | ERR_UNDER) 93 94 /* CKG1 */ 95 #define ACKMD_MASK 0x00007000 96 #define BPFMD_MASK 0x00000700 97 #define DIMD (1 << 4) 98 #define DOMD (1 << 0) 99 100 /* A/B MST_CTLR */ 101 #define BP (1 << 4) /* Fix the signal of Biphase output */ 102 #define SE (1 << 0) /* Fix the master clock */ 103 104 /* CLK_RST */ 105 #define CRB (1 << 4) 106 #define CRA (1 << 0) 107 108 /* IO SHIFT / MACRO */ 109 #define BI_SHIFT 12 110 #define BO_SHIFT 8 111 #define AI_SHIFT 4 112 #define AO_SHIFT 0 113 #define AB_IO(param, shift) (param << shift) 114 115 /* SOFT_RST */ 116 #define PBSR (1 << 12) /* Port B Software Reset */ 117 #define PASR (1 << 8) /* Port A Software Reset */ 118 #define IR (1 << 4) /* Interrupt Reset */ 119 #define FSISR (1 << 0) /* Software Reset */ 120 121 /* OUT_SEL (FSI2) */ 122 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ 123 /* 1: Biphase and serial */ 124 125 /* FIFO_SZ */ 126 #define FIFO_SZ_MASK 0x7 127 128 #define FSI_RATES SNDRV_PCM_RATE_8000_96000 129 130 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 131 132 /* 133 * bus options 134 * 135 * 0x000000BA 136 * 137 * A : sample widtht 16bit setting 138 * B : sample widtht 24bit setting 139 */ 140 141 #define SHIFT_16DATA 0 142 #define SHIFT_24DATA 4 143 144 #define PACKAGE_24BITBUS_BACK 0 145 #define PACKAGE_24BITBUS_FRONT 1 146 #define PACKAGE_16BITBUS_STREAM 2 147 148 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) 149 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) 150 151 /* 152 * FSI driver use below type name for variable 153 * 154 * xxx_num : number of data 155 * xxx_pos : position of data 156 * xxx_capa : capacity of data 157 */ 158 159 /* 160 * period/frame/sample image 161 * 162 * ex) PCM (2ch) 163 * 164 * period pos period pos 165 * [n] [n + 1] 166 * |<-------------------- period--------------------->| 167 * ==|============================================ ... =|== 168 * | | 169 * ||<----- frame ----->|<------ frame ----->| ... | 170 * |+--------------------+--------------------+- ... | 171 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | 172 * |+--------------------+--------------------+- ... | 173 * ==|============================================ ... =|== 174 */ 175 176 /* 177 * FSI FIFO image 178 * 179 * | | 180 * | | 181 * | [ sample ] | 182 * | [ sample ] | 183 * | [ sample ] | 184 * | [ sample ] | 185 * --> go to codecs 186 */ 187 188 /* 189 * FSI clock 190 * 191 * FSIxCLK [CPG] (ick) -------> | 192 * |-> FSI_DIV (div)-> FSI2 193 * FSIxCK [external] (xck) ---> | 194 */ 195 196 /* 197 * struct 198 */ 199 200 struct fsi_stream_handler; 201 struct fsi_stream { 202 203 /* 204 * these are initialized by fsi_stream_init() 205 */ 206 struct snd_pcm_substream *substream; 207 int fifo_sample_capa; /* sample capacity of FSI FIFO */ 208 int buff_sample_capa; /* sample capacity of ALSA buffer */ 209 int buff_sample_pos; /* sample position of ALSA buffer */ 210 int period_samples; /* sample number / 1 period */ 211 int period_pos; /* current period position */ 212 int sample_width; /* sample width */ 213 int uerr_num; 214 int oerr_num; 215 216 /* 217 * bus options 218 */ 219 u32 bus_option; 220 221 /* 222 * thse are initialized by fsi_handler_init() 223 */ 224 struct fsi_stream_handler *handler; 225 struct fsi_priv *priv; 226 227 /* 228 * these are for DMAEngine 229 */ 230 struct dma_chan *chan; 231 int dma_id; 232 }; 233 234 struct fsi_clk { 235 /* see [FSI clock] */ 236 struct clk *own; 237 struct clk *xck; 238 struct clk *ick; 239 struct clk *div; 240 int (*set_rate)(struct device *dev, 241 struct fsi_priv *fsi); 242 243 unsigned long rate; 244 unsigned int count; 245 }; 246 247 struct fsi_priv { 248 void __iomem *base; 249 phys_addr_t phys; 250 struct fsi_master *master; 251 252 struct fsi_stream playback; 253 struct fsi_stream capture; 254 255 struct fsi_clk clock; 256 257 u32 fmt; 258 259 int chan_num:16; 260 unsigned int clk_master:1; 261 unsigned int clk_cpg:1; 262 unsigned int spdif:1; 263 unsigned int enable_stream:1; 264 unsigned int bit_clk_inv:1; 265 unsigned int lr_clk_inv:1; 266 }; 267 268 struct fsi_stream_handler { 269 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); 270 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); 271 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); 272 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); 273 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); 274 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, 275 int enable); 276 }; 277 #define fsi_stream_handler_call(io, func, args...) \ 278 (!(io) ? -ENODEV : \ 279 !((io)->handler->func) ? 0 : \ 280 (io)->handler->func(args)) 281 282 struct fsi_core { 283 int ver; 284 285 u32 int_st; 286 u32 iemsk; 287 u32 imsk; 288 u32 a_mclk; 289 u32 b_mclk; 290 }; 291 292 struct fsi_master { 293 void __iomem *base; 294 struct fsi_priv fsia; 295 struct fsi_priv fsib; 296 const struct fsi_core *core; 297 spinlock_t lock; 298 }; 299 300 static inline int fsi_stream_is_play(struct fsi_priv *fsi, 301 struct fsi_stream *io) 302 { 303 return &fsi->playback == io; 304 } 305 306 307 /* 308 * basic read write function 309 */ 310 311 static void __fsi_reg_write(u32 __iomem *reg, u32 data) 312 { 313 /* valid data area is 24bit */ 314 data &= 0x00ffffff; 315 316 __raw_writel(data, reg); 317 } 318 319 static u32 __fsi_reg_read(u32 __iomem *reg) 320 { 321 return __raw_readl(reg); 322 } 323 324 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) 325 { 326 u32 val = __fsi_reg_read(reg); 327 328 val &= ~mask; 329 val |= data & mask; 330 331 __fsi_reg_write(reg, val); 332 } 333 334 #define fsi_reg_write(p, r, d)\ 335 __fsi_reg_write((p->base + REG_##r), d) 336 337 #define fsi_reg_read(p, r)\ 338 __fsi_reg_read((p->base + REG_##r)) 339 340 #define fsi_reg_mask_set(p, r, m, d)\ 341 __fsi_reg_mask_set((p->base + REG_##r), m, d) 342 343 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) 344 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) 345 static u32 _fsi_master_read(struct fsi_master *master, u32 reg) 346 { 347 u32 ret; 348 unsigned long flags; 349 350 spin_lock_irqsave(&master->lock, flags); 351 ret = __fsi_reg_read(master->base + reg); 352 spin_unlock_irqrestore(&master->lock, flags); 353 354 return ret; 355 } 356 357 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) 358 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) 359 static void _fsi_master_mask_set(struct fsi_master *master, 360 u32 reg, u32 mask, u32 data) 361 { 362 unsigned long flags; 363 364 spin_lock_irqsave(&master->lock, flags); 365 __fsi_reg_mask_set(master->base + reg, mask, data); 366 spin_unlock_irqrestore(&master->lock, flags); 367 } 368 369 /* 370 * basic function 371 */ 372 static int fsi_version(struct fsi_master *master) 373 { 374 return master->core->ver; 375 } 376 377 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) 378 { 379 return fsi->master; 380 } 381 382 static int fsi_is_clk_master(struct fsi_priv *fsi) 383 { 384 return fsi->clk_master; 385 } 386 387 static int fsi_is_port_a(struct fsi_priv *fsi) 388 { 389 return fsi->master->base == fsi->base; 390 } 391 392 static int fsi_is_spdif(struct fsi_priv *fsi) 393 { 394 return fsi->spdif; 395 } 396 397 static int fsi_is_enable_stream(struct fsi_priv *fsi) 398 { 399 return fsi->enable_stream; 400 } 401 402 static int fsi_is_play(struct snd_pcm_substream *substream) 403 { 404 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 405 } 406 407 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) 408 { 409 struct snd_soc_pcm_runtime *rtd = substream->private_data; 410 411 return asoc_rtd_to_cpu(rtd, 0); 412 } 413 414 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) 415 { 416 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); 417 418 if (dai->id == 0) 419 return &master->fsia; 420 else 421 return &master->fsib; 422 } 423 424 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) 425 { 426 return fsi_get_priv_frm_dai(fsi_get_dai(substream)); 427 } 428 429 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) 430 { 431 int is_play = fsi_stream_is_play(fsi, io); 432 int is_porta = fsi_is_port_a(fsi); 433 u32 shift; 434 435 if (is_porta) 436 shift = is_play ? AO_SHIFT : AI_SHIFT; 437 else 438 shift = is_play ? BO_SHIFT : BI_SHIFT; 439 440 return shift; 441 } 442 443 static int fsi_frame2sample(struct fsi_priv *fsi, int frames) 444 { 445 return frames * fsi->chan_num; 446 } 447 448 static int fsi_sample2frame(struct fsi_priv *fsi, int samples) 449 { 450 return samples / fsi->chan_num; 451 } 452 453 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, 454 struct fsi_stream *io) 455 { 456 int is_play = fsi_stream_is_play(fsi, io); 457 u32 status; 458 int frames; 459 460 status = is_play ? 461 fsi_reg_read(fsi, DOFF_ST) : 462 fsi_reg_read(fsi, DIFF_ST); 463 464 frames = 0x1ff & (status >> 8); 465 466 return fsi_frame2sample(fsi, frames); 467 } 468 469 static void fsi_count_fifo_err(struct fsi_priv *fsi) 470 { 471 u32 ostatus = fsi_reg_read(fsi, DOFF_ST); 472 u32 istatus = fsi_reg_read(fsi, DIFF_ST); 473 474 if (ostatus & ERR_OVER) 475 fsi->playback.oerr_num++; 476 477 if (ostatus & ERR_UNDER) 478 fsi->playback.uerr_num++; 479 480 if (istatus & ERR_OVER) 481 fsi->capture.oerr_num++; 482 483 if (istatus & ERR_UNDER) 484 fsi->capture.uerr_num++; 485 486 fsi_reg_write(fsi, DOFF_ST, 0); 487 fsi_reg_write(fsi, DIFF_ST, 0); 488 } 489 490 /* 491 * fsi_stream_xx() function 492 */ 493 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, 494 struct snd_pcm_substream *substream) 495 { 496 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; 497 } 498 499 static int fsi_stream_is_working(struct fsi_priv *fsi, 500 struct fsi_stream *io) 501 { 502 struct fsi_master *master = fsi_get_master(fsi); 503 unsigned long flags; 504 int ret; 505 506 spin_lock_irqsave(&master->lock, flags); 507 ret = !!(io->substream && io->substream->runtime); 508 spin_unlock_irqrestore(&master->lock, flags); 509 510 return ret; 511 } 512 513 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) 514 { 515 return io->priv; 516 } 517 518 static void fsi_stream_init(struct fsi_priv *fsi, 519 struct fsi_stream *io, 520 struct snd_pcm_substream *substream) 521 { 522 struct snd_pcm_runtime *runtime = substream->runtime; 523 struct fsi_master *master = fsi_get_master(fsi); 524 unsigned long flags; 525 526 spin_lock_irqsave(&master->lock, flags); 527 io->substream = substream; 528 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); 529 io->buff_sample_pos = 0; 530 io->period_samples = fsi_frame2sample(fsi, runtime->period_size); 531 io->period_pos = 0; 532 io->sample_width = samples_to_bytes(runtime, 1); 533 io->bus_option = 0; 534 io->oerr_num = -1; /* ignore 1st err */ 535 io->uerr_num = -1; /* ignore 1st err */ 536 fsi_stream_handler_call(io, init, fsi, io); 537 spin_unlock_irqrestore(&master->lock, flags); 538 } 539 540 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) 541 { 542 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 543 struct fsi_master *master = fsi_get_master(fsi); 544 unsigned long flags; 545 546 spin_lock_irqsave(&master->lock, flags); 547 548 if (io->oerr_num > 0) 549 dev_err(dai->dev, "over_run = %d\n", io->oerr_num); 550 551 if (io->uerr_num > 0) 552 dev_err(dai->dev, "under_run = %d\n", io->uerr_num); 553 554 fsi_stream_handler_call(io, quit, fsi, io); 555 io->substream = NULL; 556 io->buff_sample_capa = 0; 557 io->buff_sample_pos = 0; 558 io->period_samples = 0; 559 io->period_pos = 0; 560 io->sample_width = 0; 561 io->bus_option = 0; 562 io->oerr_num = 0; 563 io->uerr_num = 0; 564 spin_unlock_irqrestore(&master->lock, flags); 565 } 566 567 static int fsi_stream_transfer(struct fsi_stream *io) 568 { 569 struct fsi_priv *fsi = fsi_stream_to_priv(io); 570 if (!fsi) 571 return -EIO; 572 573 return fsi_stream_handler_call(io, transfer, fsi, io); 574 } 575 576 #define fsi_stream_start(fsi, io)\ 577 fsi_stream_handler_call(io, start_stop, fsi, io, 1) 578 579 #define fsi_stream_stop(fsi, io)\ 580 fsi_stream_handler_call(io, start_stop, fsi, io, 0) 581 582 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) 583 { 584 struct fsi_stream *io; 585 int ret1, ret2; 586 587 io = &fsi->playback; 588 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); 589 590 io = &fsi->capture; 591 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); 592 593 if (ret1 < 0) 594 return ret1; 595 if (ret2 < 0) 596 return ret2; 597 598 return 0; 599 } 600 601 static int fsi_stream_remove(struct fsi_priv *fsi) 602 { 603 struct fsi_stream *io; 604 int ret1, ret2; 605 606 io = &fsi->playback; 607 ret1 = fsi_stream_handler_call(io, remove, fsi, io); 608 609 io = &fsi->capture; 610 ret2 = fsi_stream_handler_call(io, remove, fsi, io); 611 612 if (ret1 < 0) 613 return ret1; 614 if (ret2 < 0) 615 return ret2; 616 617 return 0; 618 } 619 620 /* 621 * format/bus/dma setting 622 */ 623 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, 624 u32 bus, struct device *dev) 625 { 626 struct fsi_master *master = fsi_get_master(fsi); 627 int is_play = fsi_stream_is_play(fsi, io); 628 u32 fmt = fsi->fmt; 629 630 if (fsi_version(master) >= 2) { 631 u32 dma = 0; 632 633 /* 634 * FSI2 needs DMA/Bus setting 635 */ 636 switch (bus) { 637 case PACKAGE_24BITBUS_FRONT: 638 fmt |= CR_BWS_24; 639 dma |= VDMD_FRONT; 640 dev_dbg(dev, "24bit bus / package in front\n"); 641 break; 642 case PACKAGE_16BITBUS_STREAM: 643 fmt |= CR_BWS_16; 644 dma |= VDMD_STREAM; 645 dev_dbg(dev, "16bit bus / stream mode\n"); 646 break; 647 case PACKAGE_24BITBUS_BACK: 648 default: 649 fmt |= CR_BWS_24; 650 dma |= VDMD_BACK; 651 dev_dbg(dev, "24bit bus / package in back\n"); 652 break; 653 } 654 655 if (is_play) 656 fsi_reg_write(fsi, OUT_DMAC, dma); 657 else 658 fsi_reg_write(fsi, IN_DMAC, dma); 659 } 660 661 if (is_play) 662 fsi_reg_write(fsi, DO_FMT, fmt); 663 else 664 fsi_reg_write(fsi, DI_FMT, fmt); 665 } 666 667 /* 668 * irq function 669 */ 670 671 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) 672 { 673 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 674 struct fsi_master *master = fsi_get_master(fsi); 675 676 fsi_core_mask_set(master, imsk, data, data); 677 fsi_core_mask_set(master, iemsk, data, data); 678 } 679 680 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) 681 { 682 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 683 struct fsi_master *master = fsi_get_master(fsi); 684 685 fsi_core_mask_set(master, imsk, data, 0); 686 fsi_core_mask_set(master, iemsk, data, 0); 687 } 688 689 static u32 fsi_irq_get_status(struct fsi_master *master) 690 { 691 return fsi_core_read(master, int_st); 692 } 693 694 static void fsi_irq_clear_status(struct fsi_priv *fsi) 695 { 696 u32 data = 0; 697 struct fsi_master *master = fsi_get_master(fsi); 698 699 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); 700 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); 701 702 /* clear interrupt factor */ 703 fsi_core_mask_set(master, int_st, data, 0); 704 } 705 706 /* 707 * SPDIF master clock function 708 * 709 * These functions are used later FSI2 710 */ 711 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) 712 { 713 struct fsi_master *master = fsi_get_master(fsi); 714 u32 mask, val; 715 716 mask = BP | SE; 717 val = enable ? mask : 0; 718 719 fsi_is_port_a(fsi) ? 720 fsi_core_mask_set(master, a_mclk, mask, val) : 721 fsi_core_mask_set(master, b_mclk, mask, val); 722 } 723 724 /* 725 * clock function 726 */ 727 static int fsi_clk_init(struct device *dev, 728 struct fsi_priv *fsi, 729 int xck, 730 int ick, 731 int div, 732 int (*set_rate)(struct device *dev, 733 struct fsi_priv *fsi)) 734 { 735 struct fsi_clk *clock = &fsi->clock; 736 int is_porta = fsi_is_port_a(fsi); 737 738 clock->xck = NULL; 739 clock->ick = NULL; 740 clock->div = NULL; 741 clock->rate = 0; 742 clock->count = 0; 743 clock->set_rate = set_rate; 744 745 clock->own = devm_clk_get(dev, NULL); 746 if (IS_ERR(clock->own)) 747 return -EINVAL; 748 749 /* external clock */ 750 if (xck) { 751 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); 752 if (IS_ERR(clock->xck)) { 753 dev_err(dev, "can't get xck clock\n"); 754 return -EINVAL; 755 } 756 if (clock->xck == clock->own) { 757 dev_err(dev, "cpu doesn't support xck clock\n"); 758 return -EINVAL; 759 } 760 } 761 762 /* FSIACLK/FSIBCLK */ 763 if (ick) { 764 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); 765 if (IS_ERR(clock->ick)) { 766 dev_err(dev, "can't get ick clock\n"); 767 return -EINVAL; 768 } 769 if (clock->ick == clock->own) { 770 dev_err(dev, "cpu doesn't support ick clock\n"); 771 return -EINVAL; 772 } 773 } 774 775 /* FSI-DIV */ 776 if (div) { 777 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); 778 if (IS_ERR(clock->div)) { 779 dev_err(dev, "can't get div clock\n"); 780 return -EINVAL; 781 } 782 if (clock->div == clock->own) { 783 dev_err(dev, "cpu doesn't support div clock\n"); 784 return -EINVAL; 785 } 786 } 787 788 return 0; 789 } 790 791 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) 792 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) 793 { 794 fsi->clock.rate = rate; 795 } 796 797 static int fsi_clk_is_valid(struct fsi_priv *fsi) 798 { 799 return fsi->clock.set_rate && 800 fsi->clock.rate; 801 } 802 803 static int fsi_clk_enable(struct device *dev, 804 struct fsi_priv *fsi) 805 { 806 struct fsi_clk *clock = &fsi->clock; 807 int ret = -EINVAL; 808 809 if (!fsi_clk_is_valid(fsi)) 810 return ret; 811 812 if (0 == clock->count) { 813 ret = clock->set_rate(dev, fsi); 814 if (ret < 0) { 815 fsi_clk_invalid(fsi); 816 return ret; 817 } 818 819 clk_enable(clock->xck); 820 clk_enable(clock->ick); 821 clk_enable(clock->div); 822 823 clock->count++; 824 } 825 826 return ret; 827 } 828 829 static int fsi_clk_disable(struct device *dev, 830 struct fsi_priv *fsi) 831 { 832 struct fsi_clk *clock = &fsi->clock; 833 834 if (!fsi_clk_is_valid(fsi)) 835 return -EINVAL; 836 837 if (1 == clock->count--) { 838 clk_disable(clock->xck); 839 clk_disable(clock->ick); 840 clk_disable(clock->div); 841 } 842 843 return 0; 844 } 845 846 static int fsi_clk_set_ackbpf(struct device *dev, 847 struct fsi_priv *fsi, 848 int ackmd, int bpfmd) 849 { 850 u32 data = 0; 851 852 /* check ackmd/bpfmd relationship */ 853 if (bpfmd > ackmd) { 854 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); 855 return -EINVAL; 856 } 857 858 /* ACKMD */ 859 switch (ackmd) { 860 case 512: 861 data |= (0x0 << 12); 862 break; 863 case 256: 864 data |= (0x1 << 12); 865 break; 866 case 128: 867 data |= (0x2 << 12); 868 break; 869 case 64: 870 data |= (0x3 << 12); 871 break; 872 case 32: 873 data |= (0x4 << 12); 874 break; 875 default: 876 dev_err(dev, "unsupported ackmd (%d)\n", ackmd); 877 return -EINVAL; 878 } 879 880 /* BPFMD */ 881 switch (bpfmd) { 882 case 32: 883 data |= (0x0 << 8); 884 break; 885 case 64: 886 data |= (0x1 << 8); 887 break; 888 case 128: 889 data |= (0x2 << 8); 890 break; 891 case 256: 892 data |= (0x3 << 8); 893 break; 894 case 512: 895 data |= (0x4 << 8); 896 break; 897 case 16: 898 data |= (0x7 << 8); 899 break; 900 default: 901 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); 902 return -EINVAL; 903 } 904 905 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); 906 907 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 908 udelay(10); 909 910 return 0; 911 } 912 913 static int fsi_clk_set_rate_external(struct device *dev, 914 struct fsi_priv *fsi) 915 { 916 struct clk *xck = fsi->clock.xck; 917 struct clk *ick = fsi->clock.ick; 918 unsigned long rate = fsi->clock.rate; 919 unsigned long xrate; 920 int ackmd, bpfmd; 921 int ret = 0; 922 923 /* check clock rate */ 924 xrate = clk_get_rate(xck); 925 if (xrate % rate) { 926 dev_err(dev, "unsupported clock rate\n"); 927 return -EINVAL; 928 } 929 930 clk_set_parent(ick, xck); 931 clk_set_rate(ick, xrate); 932 933 bpfmd = fsi->chan_num * 32; 934 ackmd = xrate / rate; 935 936 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); 937 938 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 939 if (ret < 0) 940 dev_err(dev, "%s failed", __func__); 941 942 return ret; 943 } 944 945 static int fsi_clk_set_rate_cpg(struct device *dev, 946 struct fsi_priv *fsi) 947 { 948 struct clk *ick = fsi->clock.ick; 949 struct clk *div = fsi->clock.div; 950 unsigned long rate = fsi->clock.rate; 951 unsigned long target = 0; /* 12288000 or 11289600 */ 952 unsigned long actual, cout; 953 unsigned long diff, min; 954 unsigned long best_cout, best_act; 955 int adj; 956 int ackmd, bpfmd; 957 int ret = -EINVAL; 958 959 if (!(12288000 % rate)) 960 target = 12288000; 961 if (!(11289600 % rate)) 962 target = 11289600; 963 if (!target) { 964 dev_err(dev, "unsupported rate\n"); 965 return ret; 966 } 967 968 bpfmd = fsi->chan_num * 32; 969 ackmd = target / rate; 970 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 971 if (ret < 0) { 972 dev_err(dev, "%s failed", __func__); 973 return ret; 974 } 975 976 /* 977 * The clock flow is 978 * 979 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] 980 * 981 * But, it needs to find best match of CPG and FSI_DIV 982 * combination, since it is difficult to generate correct 983 * frequency of audio clock from ick clock only. 984 * Because ick is created from its parent clock. 985 * 986 * target = rate x [512/256/128/64]fs 987 * cout = round(target x adjustment) 988 * actual = cout / adjustment (by FSI-DIV) ~= target 989 * audio = actual 990 */ 991 min = ~0; 992 best_cout = 0; 993 best_act = 0; 994 for (adj = 1; adj < 0xffff; adj++) { 995 996 cout = target * adj; 997 if (cout > 100000000) /* max clock = 100MHz */ 998 break; 999 1000 /* cout/actual audio clock */ 1001 cout = clk_round_rate(ick, cout); 1002 actual = cout / adj; 1003 1004 /* find best frequency */ 1005 diff = abs(actual - target); 1006 if (diff < min) { 1007 min = diff; 1008 best_cout = cout; 1009 best_act = actual; 1010 } 1011 } 1012 1013 ret = clk_set_rate(ick, best_cout); 1014 if (ret < 0) { 1015 dev_err(dev, "ick clock failed\n"); 1016 return -EIO; 1017 } 1018 1019 ret = clk_set_rate(div, clk_round_rate(div, best_act)); 1020 if (ret < 0) { 1021 dev_err(dev, "div clock failed\n"); 1022 return -EIO; 1023 } 1024 1025 dev_dbg(dev, "ick/div = %ld/%ld\n", 1026 clk_get_rate(ick), clk_get_rate(div)); 1027 1028 return ret; 1029 } 1030 1031 static void fsi_pointer_update(struct fsi_stream *io, int size) 1032 { 1033 io->buff_sample_pos += size; 1034 1035 if (io->buff_sample_pos >= 1036 io->period_samples * (io->period_pos + 1)) { 1037 struct snd_pcm_substream *substream = io->substream; 1038 struct snd_pcm_runtime *runtime = substream->runtime; 1039 1040 io->period_pos++; 1041 1042 if (io->period_pos >= runtime->periods) { 1043 io->buff_sample_pos = 0; 1044 io->period_pos = 0; 1045 } 1046 1047 snd_pcm_period_elapsed(substream); 1048 } 1049 } 1050 1051 /* 1052 * pio data transfer handler 1053 */ 1054 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) 1055 { 1056 int i; 1057 1058 if (fsi_is_enable_stream(fsi)) { 1059 /* 1060 * stream mode 1061 * see 1062 * fsi_pio_push_init() 1063 */ 1064 u32 *buf = (u32 *)_buf; 1065 1066 for (i = 0; i < samples / 2; i++) 1067 fsi_reg_write(fsi, DODT, buf[i]); 1068 } else { 1069 /* normal mode */ 1070 u16 *buf = (u16 *)_buf; 1071 1072 for (i = 0; i < samples; i++) 1073 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); 1074 } 1075 } 1076 1077 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) 1078 { 1079 u16 *buf = (u16 *)_buf; 1080 int i; 1081 1082 for (i = 0; i < samples; i++) 1083 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); 1084 } 1085 1086 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) 1087 { 1088 u32 *buf = (u32 *)_buf; 1089 int i; 1090 1091 for (i = 0; i < samples; i++) 1092 fsi_reg_write(fsi, DODT, *(buf + i)); 1093 } 1094 1095 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) 1096 { 1097 u32 *buf = (u32 *)_buf; 1098 int i; 1099 1100 for (i = 0; i < samples; i++) 1101 *(buf + i) = fsi_reg_read(fsi, DIDT); 1102 } 1103 1104 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) 1105 { 1106 struct snd_pcm_runtime *runtime = io->substream->runtime; 1107 1108 return runtime->dma_area + 1109 samples_to_bytes(runtime, io->buff_sample_pos); 1110 } 1111 1112 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, 1113 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), 1114 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), 1115 int samples) 1116 { 1117 u8 *buf; 1118 1119 if (!fsi_stream_is_working(fsi, io)) 1120 return -EINVAL; 1121 1122 buf = fsi_pio_get_area(fsi, io); 1123 1124 switch (io->sample_width) { 1125 case 2: 1126 run16(fsi, buf, samples); 1127 break; 1128 case 4: 1129 run32(fsi, buf, samples); 1130 break; 1131 default: 1132 return -EINVAL; 1133 } 1134 1135 fsi_pointer_update(io, samples); 1136 1137 return 0; 1138 } 1139 1140 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) 1141 { 1142 int sample_residues; /* samples in FSI fifo */ 1143 int sample_space; /* ALSA free samples space */ 1144 int samples; 1145 1146 sample_residues = fsi_get_current_fifo_samples(fsi, io); 1147 sample_space = io->buff_sample_capa - io->buff_sample_pos; 1148 1149 samples = min(sample_residues, sample_space); 1150 1151 return fsi_pio_transfer(fsi, io, 1152 fsi_pio_pop16, 1153 fsi_pio_pop32, 1154 samples); 1155 } 1156 1157 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) 1158 { 1159 int sample_residues; /* ALSA residue samples */ 1160 int sample_space; /* FSI fifo free samples space */ 1161 int samples; 1162 1163 sample_residues = io->buff_sample_capa - io->buff_sample_pos; 1164 sample_space = io->fifo_sample_capa - 1165 fsi_get_current_fifo_samples(fsi, io); 1166 1167 samples = min(sample_residues, sample_space); 1168 1169 return fsi_pio_transfer(fsi, io, 1170 fsi_pio_push16, 1171 fsi_pio_push32, 1172 samples); 1173 } 1174 1175 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1176 int enable) 1177 { 1178 struct fsi_master *master = fsi_get_master(fsi); 1179 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1180 1181 if (enable) 1182 fsi_irq_enable(fsi, io); 1183 else 1184 fsi_irq_disable(fsi, io); 1185 1186 if (fsi_is_clk_master(fsi)) 1187 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1188 1189 return 0; 1190 } 1191 1192 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) 1193 { 1194 /* 1195 * we can use 16bit stream mode 1196 * when "playback" and "16bit data" 1197 * and platform allows "stream mode" 1198 * see 1199 * fsi_pio_push16() 1200 */ 1201 if (fsi_is_enable_stream(fsi)) 1202 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1203 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1204 else 1205 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1206 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1207 return 0; 1208 } 1209 1210 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) 1211 { 1212 /* 1213 * always 24bit bus, package back when "capture" 1214 */ 1215 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1216 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1217 return 0; 1218 } 1219 1220 static struct fsi_stream_handler fsi_pio_push_handler = { 1221 .init = fsi_pio_push_init, 1222 .transfer = fsi_pio_push, 1223 .start_stop = fsi_pio_start_stop, 1224 }; 1225 1226 static struct fsi_stream_handler fsi_pio_pop_handler = { 1227 .init = fsi_pio_pop_init, 1228 .transfer = fsi_pio_pop, 1229 .start_stop = fsi_pio_start_stop, 1230 }; 1231 1232 static irqreturn_t fsi_interrupt(int irq, void *data) 1233 { 1234 struct fsi_master *master = data; 1235 u32 int_st = fsi_irq_get_status(master); 1236 1237 /* clear irq status */ 1238 fsi_master_mask_set(master, SOFT_RST, IR, 0); 1239 fsi_master_mask_set(master, SOFT_RST, IR, IR); 1240 1241 if (int_st & AB_IO(1, AO_SHIFT)) 1242 fsi_stream_transfer(&master->fsia.playback); 1243 if (int_st & AB_IO(1, BO_SHIFT)) 1244 fsi_stream_transfer(&master->fsib.playback); 1245 if (int_st & AB_IO(1, AI_SHIFT)) 1246 fsi_stream_transfer(&master->fsia.capture); 1247 if (int_st & AB_IO(1, BI_SHIFT)) 1248 fsi_stream_transfer(&master->fsib.capture); 1249 1250 fsi_count_fifo_err(&master->fsia); 1251 fsi_count_fifo_err(&master->fsib); 1252 1253 fsi_irq_clear_status(&master->fsia); 1254 fsi_irq_clear_status(&master->fsib); 1255 1256 return IRQ_HANDLED; 1257 } 1258 1259 /* 1260 * dma data transfer handler 1261 */ 1262 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) 1263 { 1264 /* 1265 * 24bit data : 24bit bus / package in back 1266 * 16bit data : 16bit bus / stream mode 1267 */ 1268 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1269 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1270 1271 return 0; 1272 } 1273 1274 static void fsi_dma_complete(void *data) 1275 { 1276 struct fsi_stream *io = (struct fsi_stream *)data; 1277 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1278 1279 fsi_pointer_update(io, io->period_samples); 1280 1281 fsi_count_fifo_err(fsi); 1282 } 1283 1284 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) 1285 { 1286 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1287 struct snd_pcm_substream *substream = io->substream; 1288 struct dma_async_tx_descriptor *desc; 1289 int is_play = fsi_stream_is_play(fsi, io); 1290 enum dma_transfer_direction dir; 1291 int ret = -EIO; 1292 1293 if (is_play) 1294 dir = DMA_MEM_TO_DEV; 1295 else 1296 dir = DMA_DEV_TO_MEM; 1297 1298 desc = dmaengine_prep_dma_cyclic(io->chan, 1299 substream->runtime->dma_addr, 1300 snd_pcm_lib_buffer_bytes(substream), 1301 snd_pcm_lib_period_bytes(substream), 1302 dir, 1303 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1304 if (!desc) { 1305 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n"); 1306 goto fsi_dma_transfer_err; 1307 } 1308 1309 desc->callback = fsi_dma_complete; 1310 desc->callback_param = io; 1311 1312 if (dmaengine_submit(desc) < 0) { 1313 dev_err(dai->dev, "tx_submit() fail\n"); 1314 goto fsi_dma_transfer_err; 1315 } 1316 1317 dma_async_issue_pending(io->chan); 1318 1319 /* 1320 * FIXME 1321 * 1322 * In DMAEngine case, codec and FSI cannot be started simultaneously 1323 * since FSI is using the scheduler work queue. 1324 * Therefore, in capture case, probably FSI FIFO will have got 1325 * overflow error in this point. 1326 * in that case, DMA cannot start transfer until error was cleared. 1327 */ 1328 if (!is_play) { 1329 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { 1330 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1331 fsi_reg_write(fsi, DIFF_ST, 0); 1332 } 1333 } 1334 1335 ret = 0; 1336 1337 fsi_dma_transfer_err: 1338 return ret; 1339 } 1340 1341 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1342 int start) 1343 { 1344 struct fsi_master *master = fsi_get_master(fsi); 1345 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1346 u32 enable = start ? DMA_ON : 0; 1347 1348 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); 1349 1350 dmaengine_terminate_all(io->chan); 1351 1352 if (fsi_is_clk_master(fsi)) 1353 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1354 1355 return 0; 1356 } 1357 1358 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) 1359 { 1360 int is_play = fsi_stream_is_play(fsi, io); 1361 1362 #ifdef CONFIG_SUPERH 1363 dma_cap_mask_t mask; 1364 dma_cap_zero(mask); 1365 dma_cap_set(DMA_SLAVE, mask); 1366 1367 io->chan = dma_request_channel(mask, shdma_chan_filter, 1368 (void *)io->dma_id); 1369 #else 1370 io->chan = dma_request_slave_channel(dev, is_play ? "tx" : "rx"); 1371 #endif 1372 if (io->chan) { 1373 struct dma_slave_config cfg = {}; 1374 int ret; 1375 1376 if (is_play) { 1377 cfg.dst_addr = fsi->phys + REG_DODT; 1378 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1379 cfg.direction = DMA_MEM_TO_DEV; 1380 } else { 1381 cfg.src_addr = fsi->phys + REG_DIDT; 1382 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1383 cfg.direction = DMA_DEV_TO_MEM; 1384 } 1385 1386 ret = dmaengine_slave_config(io->chan, &cfg); 1387 if (ret < 0) { 1388 dma_release_channel(io->chan); 1389 io->chan = NULL; 1390 } 1391 } 1392 1393 if (!io->chan) { 1394 1395 /* switch to PIO handler */ 1396 if (is_play) 1397 fsi->playback.handler = &fsi_pio_push_handler; 1398 else 1399 fsi->capture.handler = &fsi_pio_pop_handler; 1400 1401 dev_info(dev, "switch handler (dma => pio)\n"); 1402 1403 /* probe again */ 1404 return fsi_stream_probe(fsi, dev); 1405 } 1406 1407 return 0; 1408 } 1409 1410 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) 1411 { 1412 fsi_stream_stop(fsi, io); 1413 1414 if (io->chan) 1415 dma_release_channel(io->chan); 1416 1417 io->chan = NULL; 1418 return 0; 1419 } 1420 1421 static struct fsi_stream_handler fsi_dma_push_handler = { 1422 .init = fsi_dma_init, 1423 .probe = fsi_dma_probe, 1424 .transfer = fsi_dma_transfer, 1425 .remove = fsi_dma_remove, 1426 .start_stop = fsi_dma_push_start_stop, 1427 }; 1428 1429 /* 1430 * dai ops 1431 */ 1432 static void fsi_fifo_init(struct fsi_priv *fsi, 1433 struct fsi_stream *io, 1434 struct device *dev) 1435 { 1436 struct fsi_master *master = fsi_get_master(fsi); 1437 int is_play = fsi_stream_is_play(fsi, io); 1438 u32 shift, i; 1439 int frame_capa; 1440 1441 /* get on-chip RAM capacity */ 1442 shift = fsi_master_read(master, FIFO_SZ); 1443 shift >>= fsi_get_port_shift(fsi, io); 1444 shift &= FIFO_SZ_MASK; 1445 frame_capa = 256 << shift; 1446 dev_dbg(dev, "fifo = %d words\n", frame_capa); 1447 1448 /* 1449 * The maximum number of sample data varies depending 1450 * on the number of channels selected for the format. 1451 * 1452 * FIFOs are used in 4-channel units in 3-channel mode 1453 * and in 8-channel units in 5- to 7-channel mode 1454 * meaning that more FIFOs than the required size of DPRAM 1455 * are used. 1456 * 1457 * ex) if 256 words of DP-RAM is connected 1458 * 1 channel: 256 (256 x 1 = 256) 1459 * 2 channels: 128 (128 x 2 = 256) 1460 * 3 channels: 64 ( 64 x 3 = 192) 1461 * 4 channels: 64 ( 64 x 4 = 256) 1462 * 5 channels: 32 ( 32 x 5 = 160) 1463 * 6 channels: 32 ( 32 x 6 = 192) 1464 * 7 channels: 32 ( 32 x 7 = 224) 1465 * 8 channels: 32 ( 32 x 8 = 256) 1466 */ 1467 for (i = 1; i < fsi->chan_num; i <<= 1) 1468 frame_capa >>= 1; 1469 dev_dbg(dev, "%d channel %d store\n", 1470 fsi->chan_num, frame_capa); 1471 1472 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); 1473 1474 /* 1475 * set interrupt generation factor 1476 * clear FIFO 1477 */ 1478 if (is_play) { 1479 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); 1480 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); 1481 } else { 1482 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); 1483 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1484 } 1485 } 1486 1487 static int fsi_hw_startup(struct fsi_priv *fsi, 1488 struct fsi_stream *io, 1489 struct device *dev) 1490 { 1491 u32 data = 0; 1492 1493 /* clock setting */ 1494 if (fsi_is_clk_master(fsi)) 1495 data = DIMD | DOMD; 1496 1497 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); 1498 1499 /* clock inversion (CKG2) */ 1500 data = 0; 1501 if (fsi->bit_clk_inv) 1502 data |= (1 << 0); 1503 if (fsi->lr_clk_inv) 1504 data |= (1 << 4); 1505 if (fsi_is_clk_master(fsi)) 1506 data <<= 8; 1507 fsi_reg_write(fsi, CKG2, data); 1508 1509 /* spdif ? */ 1510 if (fsi_is_spdif(fsi)) { 1511 fsi_spdif_clk_ctrl(fsi, 1); 1512 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); 1513 } 1514 1515 /* 1516 * get bus settings 1517 */ 1518 data = 0; 1519 switch (io->sample_width) { 1520 case 2: 1521 data = BUSOP_GET(16, io->bus_option); 1522 break; 1523 case 4: 1524 data = BUSOP_GET(24, io->bus_option); 1525 break; 1526 } 1527 fsi_format_bus_setup(fsi, io, data, dev); 1528 1529 /* irq clear */ 1530 fsi_irq_disable(fsi, io); 1531 fsi_irq_clear_status(fsi); 1532 1533 /* fifo init */ 1534 fsi_fifo_init(fsi, io, dev); 1535 1536 /* start master clock */ 1537 if (fsi_is_clk_master(fsi)) 1538 return fsi_clk_enable(dev, fsi); 1539 1540 return 0; 1541 } 1542 1543 static int fsi_hw_shutdown(struct fsi_priv *fsi, 1544 struct device *dev) 1545 { 1546 /* stop master clock */ 1547 if (fsi_is_clk_master(fsi)) 1548 return fsi_clk_disable(dev, fsi); 1549 1550 return 0; 1551 } 1552 1553 static int fsi_dai_startup(struct snd_pcm_substream *substream, 1554 struct snd_soc_dai *dai) 1555 { 1556 struct fsi_priv *fsi = fsi_get_priv(substream); 1557 1558 fsi_clk_invalid(fsi); 1559 1560 return 0; 1561 } 1562 1563 static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 1564 struct snd_soc_dai *dai) 1565 { 1566 struct fsi_priv *fsi = fsi_get_priv(substream); 1567 1568 fsi_clk_invalid(fsi); 1569 } 1570 1571 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 1572 struct snd_soc_dai *dai) 1573 { 1574 struct fsi_priv *fsi = fsi_get_priv(substream); 1575 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1576 int ret = 0; 1577 1578 switch (cmd) { 1579 case SNDRV_PCM_TRIGGER_START: 1580 fsi_stream_init(fsi, io, substream); 1581 if (!ret) 1582 ret = fsi_hw_startup(fsi, io, dai->dev); 1583 if (!ret) 1584 ret = fsi_stream_start(fsi, io); 1585 if (!ret) 1586 ret = fsi_stream_transfer(io); 1587 break; 1588 case SNDRV_PCM_TRIGGER_STOP: 1589 if (!ret) 1590 ret = fsi_hw_shutdown(fsi, dai->dev); 1591 fsi_stream_stop(fsi, io); 1592 fsi_stream_quit(fsi, io); 1593 break; 1594 } 1595 1596 return ret; 1597 } 1598 1599 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) 1600 { 1601 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1602 case SND_SOC_DAIFMT_I2S: 1603 fsi->fmt = CR_I2S; 1604 fsi->chan_num = 2; 1605 break; 1606 case SND_SOC_DAIFMT_LEFT_J: 1607 fsi->fmt = CR_PCM; 1608 fsi->chan_num = 2; 1609 break; 1610 default: 1611 return -EINVAL; 1612 } 1613 1614 return 0; 1615 } 1616 1617 static int fsi_set_fmt_spdif(struct fsi_priv *fsi) 1618 { 1619 struct fsi_master *master = fsi_get_master(fsi); 1620 1621 if (fsi_version(master) < 2) 1622 return -EINVAL; 1623 1624 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; 1625 fsi->chan_num = 2; 1626 1627 return 0; 1628 } 1629 1630 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1631 { 1632 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); 1633 int ret; 1634 1635 /* set master/slave audio interface */ 1636 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1637 case SND_SOC_DAIFMT_CBM_CFM: 1638 break; 1639 case SND_SOC_DAIFMT_CBS_CFS: 1640 fsi->clk_master = 1; /* codec is slave, cpu is master */ 1641 break; 1642 default: 1643 return -EINVAL; 1644 } 1645 1646 /* set clock inversion */ 1647 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1648 case SND_SOC_DAIFMT_NB_IF: 1649 fsi->bit_clk_inv = 0; 1650 fsi->lr_clk_inv = 1; 1651 break; 1652 case SND_SOC_DAIFMT_IB_NF: 1653 fsi->bit_clk_inv = 1; 1654 fsi->lr_clk_inv = 0; 1655 break; 1656 case SND_SOC_DAIFMT_IB_IF: 1657 fsi->bit_clk_inv = 1; 1658 fsi->lr_clk_inv = 1; 1659 break; 1660 case SND_SOC_DAIFMT_NB_NF: 1661 default: 1662 fsi->bit_clk_inv = 0; 1663 fsi->lr_clk_inv = 0; 1664 break; 1665 } 1666 1667 if (fsi_is_clk_master(fsi)) { 1668 if (fsi->clk_cpg) 1669 fsi_clk_init(dai->dev, fsi, 0, 1, 1, 1670 fsi_clk_set_rate_cpg); 1671 else 1672 fsi_clk_init(dai->dev, fsi, 1, 1, 0, 1673 fsi_clk_set_rate_external); 1674 } 1675 1676 /* set format */ 1677 if (fsi_is_spdif(fsi)) 1678 ret = fsi_set_fmt_spdif(fsi); 1679 else 1680 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1681 1682 return ret; 1683 } 1684 1685 static int fsi_dai_hw_params(struct snd_pcm_substream *substream, 1686 struct snd_pcm_hw_params *params, 1687 struct snd_soc_dai *dai) 1688 { 1689 struct fsi_priv *fsi = fsi_get_priv(substream); 1690 1691 if (fsi_is_clk_master(fsi)) 1692 fsi_clk_valid(fsi, params_rate(params)); 1693 1694 return 0; 1695 } 1696 1697 static const struct snd_soc_dai_ops fsi_dai_ops = { 1698 .startup = fsi_dai_startup, 1699 .shutdown = fsi_dai_shutdown, 1700 .trigger = fsi_dai_trigger, 1701 .set_fmt = fsi_dai_set_fmt, 1702 .hw_params = fsi_dai_hw_params, 1703 }; 1704 1705 /* 1706 * pcm ops 1707 */ 1708 1709 static const struct snd_pcm_hardware fsi_pcm_hardware = { 1710 .info = SNDRV_PCM_INFO_INTERLEAVED | 1711 SNDRV_PCM_INFO_MMAP | 1712 SNDRV_PCM_INFO_MMAP_VALID, 1713 .buffer_bytes_max = 64 * 1024, 1714 .period_bytes_min = 32, 1715 .period_bytes_max = 8192, 1716 .periods_min = 1, 1717 .periods_max = 32, 1718 .fifo_size = 256, 1719 }; 1720 1721 static int fsi_pcm_open(struct snd_soc_component *component, 1722 struct snd_pcm_substream *substream) 1723 { 1724 struct snd_pcm_runtime *runtime = substream->runtime; 1725 int ret = 0; 1726 1727 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 1728 1729 ret = snd_pcm_hw_constraint_integer(runtime, 1730 SNDRV_PCM_HW_PARAM_PERIODS); 1731 1732 return ret; 1733 } 1734 1735 static snd_pcm_uframes_t fsi_pointer(struct snd_soc_component *component, 1736 struct snd_pcm_substream *substream) 1737 { 1738 struct fsi_priv *fsi = fsi_get_priv(substream); 1739 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1740 1741 return fsi_sample2frame(fsi, io->buff_sample_pos); 1742 } 1743 1744 /* 1745 * snd_soc_component 1746 */ 1747 1748 #define PREALLOC_BUFFER (32 * 1024) 1749 #define PREALLOC_BUFFER_MAX (32 * 1024) 1750 1751 static int fsi_pcm_new(struct snd_soc_component *component, 1752 struct snd_soc_pcm_runtime *rtd) 1753 { 1754 snd_pcm_set_managed_buffer_all( 1755 rtd->pcm, 1756 SNDRV_DMA_TYPE_DEV, 1757 rtd->card->snd_card->dev, 1758 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1759 return 0; 1760 } 1761 1762 /* 1763 * alsa struct 1764 */ 1765 1766 static struct snd_soc_dai_driver fsi_soc_dai[] = { 1767 { 1768 .name = "fsia-dai", 1769 .playback = { 1770 .rates = FSI_RATES, 1771 .formats = FSI_FMTS, 1772 .channels_min = 2, 1773 .channels_max = 2, 1774 }, 1775 .capture = { 1776 .rates = FSI_RATES, 1777 .formats = FSI_FMTS, 1778 .channels_min = 2, 1779 .channels_max = 2, 1780 }, 1781 .ops = &fsi_dai_ops, 1782 }, 1783 { 1784 .name = "fsib-dai", 1785 .playback = { 1786 .rates = FSI_RATES, 1787 .formats = FSI_FMTS, 1788 .channels_min = 2, 1789 .channels_max = 2, 1790 }, 1791 .capture = { 1792 .rates = FSI_RATES, 1793 .formats = FSI_FMTS, 1794 .channels_min = 2, 1795 .channels_max = 2, 1796 }, 1797 .ops = &fsi_dai_ops, 1798 }, 1799 }; 1800 1801 static const struct snd_soc_component_driver fsi_soc_component = { 1802 .name = "fsi", 1803 .open = fsi_pcm_open, 1804 .pointer = fsi_pointer, 1805 .pcm_construct = fsi_pcm_new, 1806 }; 1807 1808 /* 1809 * platform function 1810 */ 1811 static void fsi_of_parse(char *name, 1812 struct device_node *np, 1813 struct sh_fsi_port_info *info, 1814 struct device *dev) 1815 { 1816 int i; 1817 char prop[128]; 1818 unsigned long flags = 0; 1819 struct { 1820 char *name; 1821 unsigned int val; 1822 } of_parse_property[] = { 1823 { "spdif-connection", SH_FSI_FMT_SPDIF }, 1824 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE }, 1825 { "use-internal-clock", SH_FSI_CLK_CPG }, 1826 }; 1827 1828 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) { 1829 sprintf(prop, "%s,%s", name, of_parse_property[i].name); 1830 if (of_get_property(np, prop, NULL)) 1831 flags |= of_parse_property[i].val; 1832 } 1833 info->flags = flags; 1834 1835 dev_dbg(dev, "%s flags : %lx\n", name, info->flags); 1836 } 1837 1838 static void fsi_port_info_init(struct fsi_priv *fsi, 1839 struct sh_fsi_port_info *info) 1840 { 1841 if (info->flags & SH_FSI_FMT_SPDIF) 1842 fsi->spdif = 1; 1843 1844 if (info->flags & SH_FSI_CLK_CPG) 1845 fsi->clk_cpg = 1; 1846 1847 if (info->flags & SH_FSI_ENABLE_STREAM_MODE) 1848 fsi->enable_stream = 1; 1849 } 1850 1851 static void fsi_handler_init(struct fsi_priv *fsi, 1852 struct sh_fsi_port_info *info) 1853 { 1854 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ 1855 fsi->playback.priv = fsi; 1856 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ 1857 fsi->capture.priv = fsi; 1858 1859 if (info->tx_id) { 1860 fsi->playback.dma_id = info->tx_id; 1861 fsi->playback.handler = &fsi_dma_push_handler; 1862 } 1863 } 1864 1865 static const struct fsi_core fsi1_core = { 1866 .ver = 1, 1867 1868 /* Interrupt */ 1869 .int_st = INT_ST, 1870 .iemsk = IEMSK, 1871 .imsk = IMSK, 1872 }; 1873 1874 static const struct fsi_core fsi2_core = { 1875 .ver = 2, 1876 1877 /* Interrupt */ 1878 .int_st = CPU_INT_ST, 1879 .iemsk = CPU_IEMSK, 1880 .imsk = CPU_IMSK, 1881 .a_mclk = A_MST_CTLR, 1882 .b_mclk = B_MST_CTLR, 1883 }; 1884 1885 static const struct of_device_id fsi_of_match[] = { 1886 { .compatible = "renesas,sh_fsi", .data = &fsi1_core}, 1887 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core}, 1888 {}, 1889 }; 1890 MODULE_DEVICE_TABLE(of, fsi_of_match); 1891 1892 static const struct platform_device_id fsi_id_table[] = { 1893 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, 1894 {}, 1895 }; 1896 MODULE_DEVICE_TABLE(platform, fsi_id_table); 1897 1898 static int fsi_probe(struct platform_device *pdev) 1899 { 1900 struct fsi_master *master; 1901 struct device_node *np = pdev->dev.of_node; 1902 struct sh_fsi_platform_info info; 1903 const struct fsi_core *core; 1904 struct fsi_priv *fsi; 1905 struct resource *res; 1906 unsigned int irq; 1907 int ret; 1908 1909 memset(&info, 0, sizeof(info)); 1910 1911 core = NULL; 1912 if (np) { 1913 core = of_device_get_match_data(&pdev->dev); 1914 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev); 1915 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev); 1916 } else { 1917 const struct platform_device_id *id_entry = pdev->id_entry; 1918 if (id_entry) 1919 core = (struct fsi_core *)id_entry->driver_data; 1920 1921 if (pdev->dev.platform_data) 1922 memcpy(&info, pdev->dev.platform_data, sizeof(info)); 1923 } 1924 1925 if (!core) { 1926 dev_err(&pdev->dev, "unknown fsi device\n"); 1927 return -ENODEV; 1928 } 1929 1930 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1931 irq = platform_get_irq(pdev, 0); 1932 if (!res || (int)irq <= 0) { 1933 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 1934 return -ENODEV; 1935 } 1936 1937 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1938 if (!master) 1939 return -ENOMEM; 1940 1941 master->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1942 if (!master->base) { 1943 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 1944 return -ENXIO; 1945 } 1946 1947 /* master setting */ 1948 master->core = core; 1949 spin_lock_init(&master->lock); 1950 1951 /* FSI A setting */ 1952 fsi = &master->fsia; 1953 fsi->base = master->base; 1954 fsi->phys = res->start; 1955 fsi->master = master; 1956 fsi_port_info_init(fsi, &info.port_a); 1957 fsi_handler_init(fsi, &info.port_a); 1958 ret = fsi_stream_probe(fsi, &pdev->dev); 1959 if (ret < 0) { 1960 dev_err(&pdev->dev, "FSIA stream probe failed\n"); 1961 return ret; 1962 } 1963 1964 /* FSI B setting */ 1965 fsi = &master->fsib; 1966 fsi->base = master->base + 0x40; 1967 fsi->phys = res->start + 0x40; 1968 fsi->master = master; 1969 fsi_port_info_init(fsi, &info.port_b); 1970 fsi_handler_init(fsi, &info.port_b); 1971 ret = fsi_stream_probe(fsi, &pdev->dev); 1972 if (ret < 0) { 1973 dev_err(&pdev->dev, "FSIB stream probe failed\n"); 1974 goto exit_fsia; 1975 } 1976 1977 pm_runtime_enable(&pdev->dev); 1978 dev_set_drvdata(&pdev->dev, master); 1979 1980 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, 1981 dev_name(&pdev->dev), master); 1982 if (ret) { 1983 dev_err(&pdev->dev, "irq request err\n"); 1984 goto exit_fsib; 1985 } 1986 1987 ret = devm_snd_soc_register_component(&pdev->dev, &fsi_soc_component, 1988 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 1989 if (ret < 0) { 1990 dev_err(&pdev->dev, "cannot snd component register\n"); 1991 goto exit_fsib; 1992 } 1993 1994 return ret; 1995 1996 exit_fsib: 1997 pm_runtime_disable(&pdev->dev); 1998 fsi_stream_remove(&master->fsib); 1999 exit_fsia: 2000 fsi_stream_remove(&master->fsia); 2001 2002 return ret; 2003 } 2004 2005 static int fsi_remove(struct platform_device *pdev) 2006 { 2007 struct fsi_master *master; 2008 2009 master = dev_get_drvdata(&pdev->dev); 2010 2011 pm_runtime_disable(&pdev->dev); 2012 2013 fsi_stream_remove(&master->fsia); 2014 fsi_stream_remove(&master->fsib); 2015 2016 return 0; 2017 } 2018 2019 static void __fsi_suspend(struct fsi_priv *fsi, 2020 struct fsi_stream *io, 2021 struct device *dev) 2022 { 2023 if (!fsi_stream_is_working(fsi, io)) 2024 return; 2025 2026 fsi_stream_stop(fsi, io); 2027 fsi_hw_shutdown(fsi, dev); 2028 } 2029 2030 static void __fsi_resume(struct fsi_priv *fsi, 2031 struct fsi_stream *io, 2032 struct device *dev) 2033 { 2034 if (!fsi_stream_is_working(fsi, io)) 2035 return; 2036 2037 fsi_hw_startup(fsi, io, dev); 2038 fsi_stream_start(fsi, io); 2039 } 2040 2041 static int fsi_suspend(struct device *dev) 2042 { 2043 struct fsi_master *master = dev_get_drvdata(dev); 2044 struct fsi_priv *fsia = &master->fsia; 2045 struct fsi_priv *fsib = &master->fsib; 2046 2047 __fsi_suspend(fsia, &fsia->playback, dev); 2048 __fsi_suspend(fsia, &fsia->capture, dev); 2049 2050 __fsi_suspend(fsib, &fsib->playback, dev); 2051 __fsi_suspend(fsib, &fsib->capture, dev); 2052 2053 return 0; 2054 } 2055 2056 static int fsi_resume(struct device *dev) 2057 { 2058 struct fsi_master *master = dev_get_drvdata(dev); 2059 struct fsi_priv *fsia = &master->fsia; 2060 struct fsi_priv *fsib = &master->fsib; 2061 2062 __fsi_resume(fsia, &fsia->playback, dev); 2063 __fsi_resume(fsia, &fsia->capture, dev); 2064 2065 __fsi_resume(fsib, &fsib->playback, dev); 2066 __fsi_resume(fsib, &fsib->capture, dev); 2067 2068 return 0; 2069 } 2070 2071 static const struct dev_pm_ops fsi_pm_ops = { 2072 .suspend = fsi_suspend, 2073 .resume = fsi_resume, 2074 }; 2075 2076 static struct platform_driver fsi_driver = { 2077 .driver = { 2078 .name = "fsi-pcm-audio", 2079 .pm = &fsi_pm_ops, 2080 .of_match_table = fsi_of_match, 2081 }, 2082 .probe = fsi_probe, 2083 .remove = fsi_remove, 2084 .id_table = fsi_id_table, 2085 }; 2086 2087 module_platform_driver(fsi_driver); 2088 2089 MODULE_LICENSE("GPL v2"); 2090 MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); 2091 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 2092 MODULE_ALIAS("platform:fsi-pcm-audio"); 2093