1 /* 2 * Fifo-attached Serial Interface (FSI) support for SH7724 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on ssi.c 8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/scatterlist.h> 22 #include <linux/sh_dma.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/workqueue.h> 26 #include <sound/soc.h> 27 #include <sound/pcm_params.h> 28 #include <sound/sh_fsi.h> 29 30 /* PortA/PortB register */ 31 #define REG_DO_FMT 0x0000 32 #define REG_DOFF_CTL 0x0004 33 #define REG_DOFF_ST 0x0008 34 #define REG_DI_FMT 0x000C 35 #define REG_DIFF_CTL 0x0010 36 #define REG_DIFF_ST 0x0014 37 #define REG_CKG1 0x0018 38 #define REG_CKG2 0x001C 39 #define REG_DIDT 0x0020 40 #define REG_DODT 0x0024 41 #define REG_MUTE_ST 0x0028 42 #define REG_OUT_DMAC 0x002C 43 #define REG_OUT_SEL 0x0030 44 #define REG_IN_DMAC 0x0038 45 46 /* master register */ 47 #define MST_CLK_RST 0x0210 48 #define MST_SOFT_RST 0x0214 49 #define MST_FIFO_SZ 0x0218 50 51 /* core register (depend on FSI version) */ 52 #define A_MST_CTLR 0x0180 53 #define B_MST_CTLR 0x01A0 54 #define CPU_INT_ST 0x01F4 55 #define CPU_IEMSK 0x01F8 56 #define CPU_IMSK 0x01FC 57 #define INT_ST 0x0200 58 #define IEMSK 0x0204 59 #define IMSK 0x0208 60 61 /* DO_FMT */ 62 /* DI_FMT */ 63 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */ 64 #define CR_BWS_24 (0x0 << 20) /* FSI2 */ 65 #define CR_BWS_16 (0x1 << 20) /* FSI2 */ 66 #define CR_BWS_20 (0x2 << 20) /* FSI2 */ 67 68 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ 69 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ 70 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ 71 72 #define CR_MONO (0x0 << 4) 73 #define CR_MONO_D (0x1 << 4) 74 #define CR_PCM (0x2 << 4) 75 #define CR_I2S (0x3 << 4) 76 #define CR_TDM (0x4 << 4) 77 #define CR_TDM_D (0x5 << 4) 78 79 /* OUT_DMAC */ 80 /* IN_DMAC */ 81 #define VDMD_MASK (0x3 << 4) 82 #define VDMD_FRONT (0x0 << 4) /* Package in front */ 83 #define VDMD_BACK (0x1 << 4) /* Package in back */ 84 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ 85 86 #define DMA_ON (0x1 << 0) 87 88 /* DOFF_CTL */ 89 /* DIFF_CTL */ 90 #define IRQ_HALF 0x00100000 91 #define FIFO_CLR 0x00000001 92 93 /* DOFF_ST */ 94 #define ERR_OVER 0x00000010 95 #define ERR_UNDER 0x00000001 96 #define ST_ERR (ERR_OVER | ERR_UNDER) 97 98 /* CKG1 */ 99 #define ACKMD_MASK 0x00007000 100 #define BPFMD_MASK 0x00000700 101 #define DIMD (1 << 4) 102 #define DOMD (1 << 0) 103 104 /* A/B MST_CTLR */ 105 #define BP (1 << 4) /* Fix the signal of Biphase output */ 106 #define SE (1 << 0) /* Fix the master clock */ 107 108 /* CLK_RST */ 109 #define CRB (1 << 4) 110 #define CRA (1 << 0) 111 112 /* IO SHIFT / MACRO */ 113 #define BI_SHIFT 12 114 #define BO_SHIFT 8 115 #define AI_SHIFT 4 116 #define AO_SHIFT 0 117 #define AB_IO(param, shift) (param << shift) 118 119 /* SOFT_RST */ 120 #define PBSR (1 << 12) /* Port B Software Reset */ 121 #define PASR (1 << 8) /* Port A Software Reset */ 122 #define IR (1 << 4) /* Interrupt Reset */ 123 #define FSISR (1 << 0) /* Software Reset */ 124 125 /* OUT_SEL (FSI2) */ 126 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ 127 /* 1: Biphase and serial */ 128 129 /* FIFO_SZ */ 130 #define FIFO_SZ_MASK 0x7 131 132 #define FSI_RATES SNDRV_PCM_RATE_8000_96000 133 134 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 135 136 /* 137 * bus options 138 * 139 * 0x000000BA 140 * 141 * A : sample widtht 16bit setting 142 * B : sample widtht 24bit setting 143 */ 144 145 #define SHIFT_16DATA 0 146 #define SHIFT_24DATA 4 147 148 #define PACKAGE_24BITBUS_BACK 0 149 #define PACKAGE_24BITBUS_FRONT 1 150 #define PACKAGE_16BITBUS_STREAM 2 151 152 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) 153 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) 154 155 /* 156 * FSI driver use below type name for variable 157 * 158 * xxx_num : number of data 159 * xxx_pos : position of data 160 * xxx_capa : capacity of data 161 */ 162 163 /* 164 * period/frame/sample image 165 * 166 * ex) PCM (2ch) 167 * 168 * period pos period pos 169 * [n] [n + 1] 170 * |<-------------------- period--------------------->| 171 * ==|============================================ ... =|== 172 * | | 173 * ||<----- frame ----->|<------ frame ----->| ... | 174 * |+--------------------+--------------------+- ... | 175 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | 176 * |+--------------------+--------------------+- ... | 177 * ==|============================================ ... =|== 178 */ 179 180 /* 181 * FSI FIFO image 182 * 183 * | | 184 * | | 185 * | [ sample ] | 186 * | [ sample ] | 187 * | [ sample ] | 188 * | [ sample ] | 189 * --> go to codecs 190 */ 191 192 /* 193 * FSI clock 194 * 195 * FSIxCLK [CPG] (ick) -------> | 196 * |-> FSI_DIV (div)-> FSI2 197 * FSIxCK [external] (xck) ---> | 198 */ 199 200 /* 201 * struct 202 */ 203 204 struct fsi_stream_handler; 205 struct fsi_stream { 206 207 /* 208 * these are initialized by fsi_stream_init() 209 */ 210 struct snd_pcm_substream *substream; 211 int fifo_sample_capa; /* sample capacity of FSI FIFO */ 212 int buff_sample_capa; /* sample capacity of ALSA buffer */ 213 int buff_sample_pos; /* sample position of ALSA buffer */ 214 int period_samples; /* sample number / 1 period */ 215 int period_pos; /* current period position */ 216 int sample_width; /* sample width */ 217 int uerr_num; 218 int oerr_num; 219 220 /* 221 * bus options 222 */ 223 u32 bus_option; 224 225 /* 226 * thse are initialized by fsi_handler_init() 227 */ 228 struct fsi_stream_handler *handler; 229 struct fsi_priv *priv; 230 231 /* 232 * these are for DMAEngine 233 */ 234 struct dma_chan *chan; 235 int dma_id; 236 }; 237 238 struct fsi_clk { 239 /* see [FSI clock] */ 240 struct clk *own; 241 struct clk *xck; 242 struct clk *ick; 243 struct clk *div; 244 int (*set_rate)(struct device *dev, 245 struct fsi_priv *fsi); 246 247 unsigned long rate; 248 unsigned int count; 249 }; 250 251 struct fsi_priv { 252 void __iomem *base; 253 phys_addr_t phys; 254 struct fsi_master *master; 255 256 struct fsi_stream playback; 257 struct fsi_stream capture; 258 259 struct fsi_clk clock; 260 261 u32 fmt; 262 263 int chan_num:16; 264 unsigned int clk_master:1; 265 unsigned int clk_cpg:1; 266 unsigned int spdif:1; 267 unsigned int enable_stream:1; 268 unsigned int bit_clk_inv:1; 269 unsigned int lr_clk_inv:1; 270 }; 271 272 struct fsi_stream_handler { 273 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); 274 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); 275 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); 276 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); 277 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); 278 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, 279 int enable); 280 }; 281 #define fsi_stream_handler_call(io, func, args...) \ 282 (!(io) ? -ENODEV : \ 283 !((io)->handler->func) ? 0 : \ 284 (io)->handler->func(args)) 285 286 struct fsi_core { 287 int ver; 288 289 u32 int_st; 290 u32 iemsk; 291 u32 imsk; 292 u32 a_mclk; 293 u32 b_mclk; 294 }; 295 296 struct fsi_master { 297 void __iomem *base; 298 struct fsi_priv fsia; 299 struct fsi_priv fsib; 300 const struct fsi_core *core; 301 spinlock_t lock; 302 }; 303 304 static inline int fsi_stream_is_play(struct fsi_priv *fsi, 305 struct fsi_stream *io) 306 { 307 return &fsi->playback == io; 308 } 309 310 311 /* 312 * basic read write function 313 */ 314 315 static void __fsi_reg_write(u32 __iomem *reg, u32 data) 316 { 317 /* valid data area is 24bit */ 318 data &= 0x00ffffff; 319 320 __raw_writel(data, reg); 321 } 322 323 static u32 __fsi_reg_read(u32 __iomem *reg) 324 { 325 return __raw_readl(reg); 326 } 327 328 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) 329 { 330 u32 val = __fsi_reg_read(reg); 331 332 val &= ~mask; 333 val |= data & mask; 334 335 __fsi_reg_write(reg, val); 336 } 337 338 #define fsi_reg_write(p, r, d)\ 339 __fsi_reg_write((p->base + REG_##r), d) 340 341 #define fsi_reg_read(p, r)\ 342 __fsi_reg_read((p->base + REG_##r)) 343 344 #define fsi_reg_mask_set(p, r, m, d)\ 345 __fsi_reg_mask_set((p->base + REG_##r), m, d) 346 347 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) 348 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) 349 static u32 _fsi_master_read(struct fsi_master *master, u32 reg) 350 { 351 u32 ret; 352 unsigned long flags; 353 354 spin_lock_irqsave(&master->lock, flags); 355 ret = __fsi_reg_read(master->base + reg); 356 spin_unlock_irqrestore(&master->lock, flags); 357 358 return ret; 359 } 360 361 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) 362 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) 363 static void _fsi_master_mask_set(struct fsi_master *master, 364 u32 reg, u32 mask, u32 data) 365 { 366 unsigned long flags; 367 368 spin_lock_irqsave(&master->lock, flags); 369 __fsi_reg_mask_set(master->base + reg, mask, data); 370 spin_unlock_irqrestore(&master->lock, flags); 371 } 372 373 /* 374 * basic function 375 */ 376 static int fsi_version(struct fsi_master *master) 377 { 378 return master->core->ver; 379 } 380 381 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) 382 { 383 return fsi->master; 384 } 385 386 static int fsi_is_clk_master(struct fsi_priv *fsi) 387 { 388 return fsi->clk_master; 389 } 390 391 static int fsi_is_port_a(struct fsi_priv *fsi) 392 { 393 return fsi->master->base == fsi->base; 394 } 395 396 static int fsi_is_spdif(struct fsi_priv *fsi) 397 { 398 return fsi->spdif; 399 } 400 401 static int fsi_is_enable_stream(struct fsi_priv *fsi) 402 { 403 return fsi->enable_stream; 404 } 405 406 static int fsi_is_play(struct snd_pcm_substream *substream) 407 { 408 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 409 } 410 411 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) 412 { 413 struct snd_soc_pcm_runtime *rtd = substream->private_data; 414 415 return rtd->cpu_dai; 416 } 417 418 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) 419 { 420 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); 421 422 if (dai->id == 0) 423 return &master->fsia; 424 else 425 return &master->fsib; 426 } 427 428 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) 429 { 430 return fsi_get_priv_frm_dai(fsi_get_dai(substream)); 431 } 432 433 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) 434 { 435 int is_play = fsi_stream_is_play(fsi, io); 436 int is_porta = fsi_is_port_a(fsi); 437 u32 shift; 438 439 if (is_porta) 440 shift = is_play ? AO_SHIFT : AI_SHIFT; 441 else 442 shift = is_play ? BO_SHIFT : BI_SHIFT; 443 444 return shift; 445 } 446 447 static int fsi_frame2sample(struct fsi_priv *fsi, int frames) 448 { 449 return frames * fsi->chan_num; 450 } 451 452 static int fsi_sample2frame(struct fsi_priv *fsi, int samples) 453 { 454 return samples / fsi->chan_num; 455 } 456 457 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, 458 struct fsi_stream *io) 459 { 460 int is_play = fsi_stream_is_play(fsi, io); 461 u32 status; 462 int frames; 463 464 status = is_play ? 465 fsi_reg_read(fsi, DOFF_ST) : 466 fsi_reg_read(fsi, DIFF_ST); 467 468 frames = 0x1ff & (status >> 8); 469 470 return fsi_frame2sample(fsi, frames); 471 } 472 473 static void fsi_count_fifo_err(struct fsi_priv *fsi) 474 { 475 u32 ostatus = fsi_reg_read(fsi, DOFF_ST); 476 u32 istatus = fsi_reg_read(fsi, DIFF_ST); 477 478 if (ostatus & ERR_OVER) 479 fsi->playback.oerr_num++; 480 481 if (ostatus & ERR_UNDER) 482 fsi->playback.uerr_num++; 483 484 if (istatus & ERR_OVER) 485 fsi->capture.oerr_num++; 486 487 if (istatus & ERR_UNDER) 488 fsi->capture.uerr_num++; 489 490 fsi_reg_write(fsi, DOFF_ST, 0); 491 fsi_reg_write(fsi, DIFF_ST, 0); 492 } 493 494 /* 495 * fsi_stream_xx() function 496 */ 497 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, 498 struct snd_pcm_substream *substream) 499 { 500 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; 501 } 502 503 static int fsi_stream_is_working(struct fsi_priv *fsi, 504 struct fsi_stream *io) 505 { 506 struct fsi_master *master = fsi_get_master(fsi); 507 unsigned long flags; 508 int ret; 509 510 spin_lock_irqsave(&master->lock, flags); 511 ret = !!(io->substream && io->substream->runtime); 512 spin_unlock_irqrestore(&master->lock, flags); 513 514 return ret; 515 } 516 517 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) 518 { 519 return io->priv; 520 } 521 522 static void fsi_stream_init(struct fsi_priv *fsi, 523 struct fsi_stream *io, 524 struct snd_pcm_substream *substream) 525 { 526 struct snd_pcm_runtime *runtime = substream->runtime; 527 struct fsi_master *master = fsi_get_master(fsi); 528 unsigned long flags; 529 530 spin_lock_irqsave(&master->lock, flags); 531 io->substream = substream; 532 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); 533 io->buff_sample_pos = 0; 534 io->period_samples = fsi_frame2sample(fsi, runtime->period_size); 535 io->period_pos = 0; 536 io->sample_width = samples_to_bytes(runtime, 1); 537 io->bus_option = 0; 538 io->oerr_num = -1; /* ignore 1st err */ 539 io->uerr_num = -1; /* ignore 1st err */ 540 fsi_stream_handler_call(io, init, fsi, io); 541 spin_unlock_irqrestore(&master->lock, flags); 542 } 543 544 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) 545 { 546 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 547 struct fsi_master *master = fsi_get_master(fsi); 548 unsigned long flags; 549 550 spin_lock_irqsave(&master->lock, flags); 551 552 if (io->oerr_num > 0) 553 dev_err(dai->dev, "over_run = %d\n", io->oerr_num); 554 555 if (io->uerr_num > 0) 556 dev_err(dai->dev, "under_run = %d\n", io->uerr_num); 557 558 fsi_stream_handler_call(io, quit, fsi, io); 559 io->substream = NULL; 560 io->buff_sample_capa = 0; 561 io->buff_sample_pos = 0; 562 io->period_samples = 0; 563 io->period_pos = 0; 564 io->sample_width = 0; 565 io->bus_option = 0; 566 io->oerr_num = 0; 567 io->uerr_num = 0; 568 spin_unlock_irqrestore(&master->lock, flags); 569 } 570 571 static int fsi_stream_transfer(struct fsi_stream *io) 572 { 573 struct fsi_priv *fsi = fsi_stream_to_priv(io); 574 if (!fsi) 575 return -EIO; 576 577 return fsi_stream_handler_call(io, transfer, fsi, io); 578 } 579 580 #define fsi_stream_start(fsi, io)\ 581 fsi_stream_handler_call(io, start_stop, fsi, io, 1) 582 583 #define fsi_stream_stop(fsi, io)\ 584 fsi_stream_handler_call(io, start_stop, fsi, io, 0) 585 586 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) 587 { 588 struct fsi_stream *io; 589 int ret1, ret2; 590 591 io = &fsi->playback; 592 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); 593 594 io = &fsi->capture; 595 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); 596 597 if (ret1 < 0) 598 return ret1; 599 if (ret2 < 0) 600 return ret2; 601 602 return 0; 603 } 604 605 static int fsi_stream_remove(struct fsi_priv *fsi) 606 { 607 struct fsi_stream *io; 608 int ret1, ret2; 609 610 io = &fsi->playback; 611 ret1 = fsi_stream_handler_call(io, remove, fsi, io); 612 613 io = &fsi->capture; 614 ret2 = fsi_stream_handler_call(io, remove, fsi, io); 615 616 if (ret1 < 0) 617 return ret1; 618 if (ret2 < 0) 619 return ret2; 620 621 return 0; 622 } 623 624 /* 625 * format/bus/dma setting 626 */ 627 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, 628 u32 bus, struct device *dev) 629 { 630 struct fsi_master *master = fsi_get_master(fsi); 631 int is_play = fsi_stream_is_play(fsi, io); 632 u32 fmt = fsi->fmt; 633 634 if (fsi_version(master) >= 2) { 635 u32 dma = 0; 636 637 /* 638 * FSI2 needs DMA/Bus setting 639 */ 640 switch (bus) { 641 case PACKAGE_24BITBUS_FRONT: 642 fmt |= CR_BWS_24; 643 dma |= VDMD_FRONT; 644 dev_dbg(dev, "24bit bus / package in front\n"); 645 break; 646 case PACKAGE_16BITBUS_STREAM: 647 fmt |= CR_BWS_16; 648 dma |= VDMD_STREAM; 649 dev_dbg(dev, "16bit bus / stream mode\n"); 650 break; 651 case PACKAGE_24BITBUS_BACK: 652 default: 653 fmt |= CR_BWS_24; 654 dma |= VDMD_BACK; 655 dev_dbg(dev, "24bit bus / package in back\n"); 656 break; 657 } 658 659 if (is_play) 660 fsi_reg_write(fsi, OUT_DMAC, dma); 661 else 662 fsi_reg_write(fsi, IN_DMAC, dma); 663 } 664 665 if (is_play) 666 fsi_reg_write(fsi, DO_FMT, fmt); 667 else 668 fsi_reg_write(fsi, DI_FMT, fmt); 669 } 670 671 /* 672 * irq function 673 */ 674 675 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) 676 { 677 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 678 struct fsi_master *master = fsi_get_master(fsi); 679 680 fsi_core_mask_set(master, imsk, data, data); 681 fsi_core_mask_set(master, iemsk, data, data); 682 } 683 684 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) 685 { 686 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 687 struct fsi_master *master = fsi_get_master(fsi); 688 689 fsi_core_mask_set(master, imsk, data, 0); 690 fsi_core_mask_set(master, iemsk, data, 0); 691 } 692 693 static u32 fsi_irq_get_status(struct fsi_master *master) 694 { 695 return fsi_core_read(master, int_st); 696 } 697 698 static void fsi_irq_clear_status(struct fsi_priv *fsi) 699 { 700 u32 data = 0; 701 struct fsi_master *master = fsi_get_master(fsi); 702 703 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); 704 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); 705 706 /* clear interrupt factor */ 707 fsi_core_mask_set(master, int_st, data, 0); 708 } 709 710 /* 711 * SPDIF master clock function 712 * 713 * These functions are used later FSI2 714 */ 715 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) 716 { 717 struct fsi_master *master = fsi_get_master(fsi); 718 u32 mask, val; 719 720 mask = BP | SE; 721 val = enable ? mask : 0; 722 723 fsi_is_port_a(fsi) ? 724 fsi_core_mask_set(master, a_mclk, mask, val) : 725 fsi_core_mask_set(master, b_mclk, mask, val); 726 } 727 728 /* 729 * clock function 730 */ 731 static int fsi_clk_init(struct device *dev, 732 struct fsi_priv *fsi, 733 int xck, 734 int ick, 735 int div, 736 int (*set_rate)(struct device *dev, 737 struct fsi_priv *fsi)) 738 { 739 struct fsi_clk *clock = &fsi->clock; 740 int is_porta = fsi_is_port_a(fsi); 741 742 clock->xck = NULL; 743 clock->ick = NULL; 744 clock->div = NULL; 745 clock->rate = 0; 746 clock->count = 0; 747 clock->set_rate = set_rate; 748 749 clock->own = devm_clk_get(dev, NULL); 750 if (IS_ERR(clock->own)) 751 return -EINVAL; 752 753 /* external clock */ 754 if (xck) { 755 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); 756 if (IS_ERR(clock->xck)) { 757 dev_err(dev, "can't get xck clock\n"); 758 return -EINVAL; 759 } 760 if (clock->xck == clock->own) { 761 dev_err(dev, "cpu doesn't support xck clock\n"); 762 return -EINVAL; 763 } 764 } 765 766 /* FSIACLK/FSIBCLK */ 767 if (ick) { 768 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); 769 if (IS_ERR(clock->ick)) { 770 dev_err(dev, "can't get ick clock\n"); 771 return -EINVAL; 772 } 773 if (clock->ick == clock->own) { 774 dev_err(dev, "cpu doesn't support ick clock\n"); 775 return -EINVAL; 776 } 777 } 778 779 /* FSI-DIV */ 780 if (div) { 781 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); 782 if (IS_ERR(clock->div)) { 783 dev_err(dev, "can't get div clock\n"); 784 return -EINVAL; 785 } 786 if (clock->div == clock->own) { 787 dev_err(dev, "cpu doens't support div clock\n"); 788 return -EINVAL; 789 } 790 } 791 792 return 0; 793 } 794 795 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) 796 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) 797 { 798 fsi->clock.rate = rate; 799 } 800 801 static int fsi_clk_is_valid(struct fsi_priv *fsi) 802 { 803 return fsi->clock.set_rate && 804 fsi->clock.rate; 805 } 806 807 static int fsi_clk_enable(struct device *dev, 808 struct fsi_priv *fsi) 809 { 810 struct fsi_clk *clock = &fsi->clock; 811 int ret = -EINVAL; 812 813 if (!fsi_clk_is_valid(fsi)) 814 return ret; 815 816 if (0 == clock->count) { 817 ret = clock->set_rate(dev, fsi); 818 if (ret < 0) { 819 fsi_clk_invalid(fsi); 820 return ret; 821 } 822 823 clk_enable(clock->xck); 824 clk_enable(clock->ick); 825 clk_enable(clock->div); 826 827 clock->count++; 828 } 829 830 return ret; 831 } 832 833 static int fsi_clk_disable(struct device *dev, 834 struct fsi_priv *fsi) 835 { 836 struct fsi_clk *clock = &fsi->clock; 837 838 if (!fsi_clk_is_valid(fsi)) 839 return -EINVAL; 840 841 if (1 == clock->count--) { 842 clk_disable(clock->xck); 843 clk_disable(clock->ick); 844 clk_disable(clock->div); 845 } 846 847 return 0; 848 } 849 850 static int fsi_clk_set_ackbpf(struct device *dev, 851 struct fsi_priv *fsi, 852 int ackmd, int bpfmd) 853 { 854 u32 data = 0; 855 856 /* check ackmd/bpfmd relationship */ 857 if (bpfmd > ackmd) { 858 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); 859 return -EINVAL; 860 } 861 862 /* ACKMD */ 863 switch (ackmd) { 864 case 512: 865 data |= (0x0 << 12); 866 break; 867 case 256: 868 data |= (0x1 << 12); 869 break; 870 case 128: 871 data |= (0x2 << 12); 872 break; 873 case 64: 874 data |= (0x3 << 12); 875 break; 876 case 32: 877 data |= (0x4 << 12); 878 break; 879 default: 880 dev_err(dev, "unsupported ackmd (%d)\n", ackmd); 881 return -EINVAL; 882 } 883 884 /* BPFMD */ 885 switch (bpfmd) { 886 case 32: 887 data |= (0x0 << 8); 888 break; 889 case 64: 890 data |= (0x1 << 8); 891 break; 892 case 128: 893 data |= (0x2 << 8); 894 break; 895 case 256: 896 data |= (0x3 << 8); 897 break; 898 case 512: 899 data |= (0x4 << 8); 900 break; 901 case 16: 902 data |= (0x7 << 8); 903 break; 904 default: 905 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); 906 return -EINVAL; 907 } 908 909 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); 910 911 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 912 udelay(10); 913 914 return 0; 915 } 916 917 static int fsi_clk_set_rate_external(struct device *dev, 918 struct fsi_priv *fsi) 919 { 920 struct clk *xck = fsi->clock.xck; 921 struct clk *ick = fsi->clock.ick; 922 unsigned long rate = fsi->clock.rate; 923 unsigned long xrate; 924 int ackmd, bpfmd; 925 int ret = 0; 926 927 /* check clock rate */ 928 xrate = clk_get_rate(xck); 929 if (xrate % rate) { 930 dev_err(dev, "unsupported clock rate\n"); 931 return -EINVAL; 932 } 933 934 clk_set_parent(ick, xck); 935 clk_set_rate(ick, xrate); 936 937 bpfmd = fsi->chan_num * 32; 938 ackmd = xrate / rate; 939 940 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); 941 942 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 943 if (ret < 0) 944 dev_err(dev, "%s failed", __func__); 945 946 return ret; 947 } 948 949 static int fsi_clk_set_rate_cpg(struct device *dev, 950 struct fsi_priv *fsi) 951 { 952 struct clk *ick = fsi->clock.ick; 953 struct clk *div = fsi->clock.div; 954 unsigned long rate = fsi->clock.rate; 955 unsigned long target = 0; /* 12288000 or 11289600 */ 956 unsigned long actual, cout; 957 unsigned long diff, min; 958 unsigned long best_cout, best_act; 959 int adj; 960 int ackmd, bpfmd; 961 int ret = -EINVAL; 962 963 if (!(12288000 % rate)) 964 target = 12288000; 965 if (!(11289600 % rate)) 966 target = 11289600; 967 if (!target) { 968 dev_err(dev, "unsupported rate\n"); 969 return ret; 970 } 971 972 bpfmd = fsi->chan_num * 32; 973 ackmd = target / rate; 974 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 975 if (ret < 0) { 976 dev_err(dev, "%s failed", __func__); 977 return ret; 978 } 979 980 /* 981 * The clock flow is 982 * 983 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] 984 * 985 * But, it needs to find best match of CPG and FSI_DIV 986 * combination, since it is difficult to generate correct 987 * frequency of audio clock from ick clock only. 988 * Because ick is created from its parent clock. 989 * 990 * target = rate x [512/256/128/64]fs 991 * cout = round(target x adjustment) 992 * actual = cout / adjustment (by FSI-DIV) ~= target 993 * audio = actual 994 */ 995 min = ~0; 996 best_cout = 0; 997 best_act = 0; 998 for (adj = 1; adj < 0xffff; adj++) { 999 1000 cout = target * adj; 1001 if (cout > 100000000) /* max clock = 100MHz */ 1002 break; 1003 1004 /* cout/actual audio clock */ 1005 cout = clk_round_rate(ick, cout); 1006 actual = cout / adj; 1007 1008 /* find best frequency */ 1009 diff = abs(actual - target); 1010 if (diff < min) { 1011 min = diff; 1012 best_cout = cout; 1013 best_act = actual; 1014 } 1015 } 1016 1017 ret = clk_set_rate(ick, best_cout); 1018 if (ret < 0) { 1019 dev_err(dev, "ick clock failed\n"); 1020 return -EIO; 1021 } 1022 1023 ret = clk_set_rate(div, clk_round_rate(div, best_act)); 1024 if (ret < 0) { 1025 dev_err(dev, "div clock failed\n"); 1026 return -EIO; 1027 } 1028 1029 dev_dbg(dev, "ick/div = %ld/%ld\n", 1030 clk_get_rate(ick), clk_get_rate(div)); 1031 1032 return ret; 1033 } 1034 1035 static void fsi_pointer_update(struct fsi_stream *io, int size) 1036 { 1037 io->buff_sample_pos += size; 1038 1039 if (io->buff_sample_pos >= 1040 io->period_samples * (io->period_pos + 1)) { 1041 struct snd_pcm_substream *substream = io->substream; 1042 struct snd_pcm_runtime *runtime = substream->runtime; 1043 1044 io->period_pos++; 1045 1046 if (io->period_pos >= runtime->periods) { 1047 io->buff_sample_pos = 0; 1048 io->period_pos = 0; 1049 } 1050 1051 snd_pcm_period_elapsed(substream); 1052 } 1053 } 1054 1055 /* 1056 * pio data transfer handler 1057 */ 1058 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) 1059 { 1060 int i; 1061 1062 if (fsi_is_enable_stream(fsi)) { 1063 /* 1064 * stream mode 1065 * see 1066 * fsi_pio_push_init() 1067 */ 1068 u32 *buf = (u32 *)_buf; 1069 1070 for (i = 0; i < samples / 2; i++) 1071 fsi_reg_write(fsi, DODT, buf[i]); 1072 } else { 1073 /* normal mode */ 1074 u16 *buf = (u16 *)_buf; 1075 1076 for (i = 0; i < samples; i++) 1077 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); 1078 } 1079 } 1080 1081 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) 1082 { 1083 u16 *buf = (u16 *)_buf; 1084 int i; 1085 1086 for (i = 0; i < samples; i++) 1087 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); 1088 } 1089 1090 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) 1091 { 1092 u32 *buf = (u32 *)_buf; 1093 int i; 1094 1095 for (i = 0; i < samples; i++) 1096 fsi_reg_write(fsi, DODT, *(buf + i)); 1097 } 1098 1099 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) 1100 { 1101 u32 *buf = (u32 *)_buf; 1102 int i; 1103 1104 for (i = 0; i < samples; i++) 1105 *(buf + i) = fsi_reg_read(fsi, DIDT); 1106 } 1107 1108 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) 1109 { 1110 struct snd_pcm_runtime *runtime = io->substream->runtime; 1111 1112 return runtime->dma_area + 1113 samples_to_bytes(runtime, io->buff_sample_pos); 1114 } 1115 1116 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, 1117 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), 1118 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), 1119 int samples) 1120 { 1121 u8 *buf; 1122 1123 if (!fsi_stream_is_working(fsi, io)) 1124 return -EINVAL; 1125 1126 buf = fsi_pio_get_area(fsi, io); 1127 1128 switch (io->sample_width) { 1129 case 2: 1130 run16(fsi, buf, samples); 1131 break; 1132 case 4: 1133 run32(fsi, buf, samples); 1134 break; 1135 default: 1136 return -EINVAL; 1137 } 1138 1139 fsi_pointer_update(io, samples); 1140 1141 return 0; 1142 } 1143 1144 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) 1145 { 1146 int sample_residues; /* samples in FSI fifo */ 1147 int sample_space; /* ALSA free samples space */ 1148 int samples; 1149 1150 sample_residues = fsi_get_current_fifo_samples(fsi, io); 1151 sample_space = io->buff_sample_capa - io->buff_sample_pos; 1152 1153 samples = min(sample_residues, sample_space); 1154 1155 return fsi_pio_transfer(fsi, io, 1156 fsi_pio_pop16, 1157 fsi_pio_pop32, 1158 samples); 1159 } 1160 1161 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) 1162 { 1163 int sample_residues; /* ALSA residue samples */ 1164 int sample_space; /* FSI fifo free samples space */ 1165 int samples; 1166 1167 sample_residues = io->buff_sample_capa - io->buff_sample_pos; 1168 sample_space = io->fifo_sample_capa - 1169 fsi_get_current_fifo_samples(fsi, io); 1170 1171 samples = min(sample_residues, sample_space); 1172 1173 return fsi_pio_transfer(fsi, io, 1174 fsi_pio_push16, 1175 fsi_pio_push32, 1176 samples); 1177 } 1178 1179 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1180 int enable) 1181 { 1182 struct fsi_master *master = fsi_get_master(fsi); 1183 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1184 1185 if (enable) 1186 fsi_irq_enable(fsi, io); 1187 else 1188 fsi_irq_disable(fsi, io); 1189 1190 if (fsi_is_clk_master(fsi)) 1191 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1192 1193 return 0; 1194 } 1195 1196 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) 1197 { 1198 /* 1199 * we can use 16bit stream mode 1200 * when "playback" and "16bit data" 1201 * and platform allows "stream mode" 1202 * see 1203 * fsi_pio_push16() 1204 */ 1205 if (fsi_is_enable_stream(fsi)) 1206 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1207 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1208 else 1209 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1210 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1211 return 0; 1212 } 1213 1214 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) 1215 { 1216 /* 1217 * always 24bit bus, package back when "capture" 1218 */ 1219 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1220 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1221 return 0; 1222 } 1223 1224 static struct fsi_stream_handler fsi_pio_push_handler = { 1225 .init = fsi_pio_push_init, 1226 .transfer = fsi_pio_push, 1227 .start_stop = fsi_pio_start_stop, 1228 }; 1229 1230 static struct fsi_stream_handler fsi_pio_pop_handler = { 1231 .init = fsi_pio_pop_init, 1232 .transfer = fsi_pio_pop, 1233 .start_stop = fsi_pio_start_stop, 1234 }; 1235 1236 static irqreturn_t fsi_interrupt(int irq, void *data) 1237 { 1238 struct fsi_master *master = data; 1239 u32 int_st = fsi_irq_get_status(master); 1240 1241 /* clear irq status */ 1242 fsi_master_mask_set(master, SOFT_RST, IR, 0); 1243 fsi_master_mask_set(master, SOFT_RST, IR, IR); 1244 1245 if (int_st & AB_IO(1, AO_SHIFT)) 1246 fsi_stream_transfer(&master->fsia.playback); 1247 if (int_st & AB_IO(1, BO_SHIFT)) 1248 fsi_stream_transfer(&master->fsib.playback); 1249 if (int_st & AB_IO(1, AI_SHIFT)) 1250 fsi_stream_transfer(&master->fsia.capture); 1251 if (int_st & AB_IO(1, BI_SHIFT)) 1252 fsi_stream_transfer(&master->fsib.capture); 1253 1254 fsi_count_fifo_err(&master->fsia); 1255 fsi_count_fifo_err(&master->fsib); 1256 1257 fsi_irq_clear_status(&master->fsia); 1258 fsi_irq_clear_status(&master->fsib); 1259 1260 return IRQ_HANDLED; 1261 } 1262 1263 /* 1264 * dma data transfer handler 1265 */ 1266 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) 1267 { 1268 /* 1269 * 24bit data : 24bit bus / package in back 1270 * 16bit data : 16bit bus / stream mode 1271 */ 1272 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1273 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1274 1275 return 0; 1276 } 1277 1278 static void fsi_dma_complete(void *data) 1279 { 1280 struct fsi_stream *io = (struct fsi_stream *)data; 1281 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1282 1283 fsi_pointer_update(io, io->period_samples); 1284 1285 fsi_count_fifo_err(fsi); 1286 } 1287 1288 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) 1289 { 1290 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1291 struct snd_pcm_substream *substream = io->substream; 1292 struct dma_async_tx_descriptor *desc; 1293 int is_play = fsi_stream_is_play(fsi, io); 1294 enum dma_transfer_direction dir; 1295 int ret = -EIO; 1296 1297 if (is_play) 1298 dir = DMA_MEM_TO_DEV; 1299 else 1300 dir = DMA_DEV_TO_MEM; 1301 1302 desc = dmaengine_prep_dma_cyclic(io->chan, 1303 substream->runtime->dma_addr, 1304 snd_pcm_lib_buffer_bytes(substream), 1305 snd_pcm_lib_period_bytes(substream), 1306 dir, 1307 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1308 if (!desc) { 1309 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n"); 1310 goto fsi_dma_transfer_err; 1311 } 1312 1313 desc->callback = fsi_dma_complete; 1314 desc->callback_param = io; 1315 1316 if (dmaengine_submit(desc) < 0) { 1317 dev_err(dai->dev, "tx_submit() fail\n"); 1318 goto fsi_dma_transfer_err; 1319 } 1320 1321 dma_async_issue_pending(io->chan); 1322 1323 /* 1324 * FIXME 1325 * 1326 * In DMAEngine case, codec and FSI cannot be started simultaneously 1327 * since FSI is using the scheduler work queue. 1328 * Therefore, in capture case, probably FSI FIFO will have got 1329 * overflow error in this point. 1330 * in that case, DMA cannot start transfer until error was cleared. 1331 */ 1332 if (!is_play) { 1333 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { 1334 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1335 fsi_reg_write(fsi, DIFF_ST, 0); 1336 } 1337 } 1338 1339 ret = 0; 1340 1341 fsi_dma_transfer_err: 1342 return ret; 1343 } 1344 1345 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1346 int start) 1347 { 1348 struct fsi_master *master = fsi_get_master(fsi); 1349 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1350 u32 enable = start ? DMA_ON : 0; 1351 1352 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); 1353 1354 dmaengine_terminate_all(io->chan); 1355 1356 if (fsi_is_clk_master(fsi)) 1357 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1358 1359 return 0; 1360 } 1361 1362 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) 1363 { 1364 int is_play = fsi_stream_is_play(fsi, io); 1365 1366 #ifdef CONFIG_SUPERH 1367 dma_cap_mask_t mask; 1368 dma_cap_zero(mask); 1369 dma_cap_set(DMA_SLAVE, mask); 1370 1371 io->chan = dma_request_channel(mask, shdma_chan_filter, 1372 (void *)io->dma_id); 1373 #else 1374 io->chan = dma_request_slave_channel(dev, is_play ? "tx" : "rx"); 1375 #endif 1376 if (io->chan) { 1377 struct dma_slave_config cfg = {}; 1378 int ret; 1379 1380 if (is_play) { 1381 cfg.dst_addr = fsi->phys + REG_DODT; 1382 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1383 cfg.direction = DMA_MEM_TO_DEV; 1384 } else { 1385 cfg.src_addr = fsi->phys + REG_DIDT; 1386 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1387 cfg.direction = DMA_DEV_TO_MEM; 1388 } 1389 1390 ret = dmaengine_slave_config(io->chan, &cfg); 1391 if (ret < 0) { 1392 dma_release_channel(io->chan); 1393 io->chan = NULL; 1394 } 1395 } 1396 1397 if (!io->chan) { 1398 1399 /* switch to PIO handler */ 1400 if (is_play) 1401 fsi->playback.handler = &fsi_pio_push_handler; 1402 else 1403 fsi->capture.handler = &fsi_pio_pop_handler; 1404 1405 dev_info(dev, "switch handler (dma => pio)\n"); 1406 1407 /* probe again */ 1408 return fsi_stream_probe(fsi, dev); 1409 } 1410 1411 return 0; 1412 } 1413 1414 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) 1415 { 1416 fsi_stream_stop(fsi, io); 1417 1418 if (io->chan) 1419 dma_release_channel(io->chan); 1420 1421 io->chan = NULL; 1422 return 0; 1423 } 1424 1425 static struct fsi_stream_handler fsi_dma_push_handler = { 1426 .init = fsi_dma_init, 1427 .probe = fsi_dma_probe, 1428 .transfer = fsi_dma_transfer, 1429 .remove = fsi_dma_remove, 1430 .start_stop = fsi_dma_push_start_stop, 1431 }; 1432 1433 /* 1434 * dai ops 1435 */ 1436 static void fsi_fifo_init(struct fsi_priv *fsi, 1437 struct fsi_stream *io, 1438 struct device *dev) 1439 { 1440 struct fsi_master *master = fsi_get_master(fsi); 1441 int is_play = fsi_stream_is_play(fsi, io); 1442 u32 shift, i; 1443 int frame_capa; 1444 1445 /* get on-chip RAM capacity */ 1446 shift = fsi_master_read(master, FIFO_SZ); 1447 shift >>= fsi_get_port_shift(fsi, io); 1448 shift &= FIFO_SZ_MASK; 1449 frame_capa = 256 << shift; 1450 dev_dbg(dev, "fifo = %d words\n", frame_capa); 1451 1452 /* 1453 * The maximum number of sample data varies depending 1454 * on the number of channels selected for the format. 1455 * 1456 * FIFOs are used in 4-channel units in 3-channel mode 1457 * and in 8-channel units in 5- to 7-channel mode 1458 * meaning that more FIFOs than the required size of DPRAM 1459 * are used. 1460 * 1461 * ex) if 256 words of DP-RAM is connected 1462 * 1 channel: 256 (256 x 1 = 256) 1463 * 2 channels: 128 (128 x 2 = 256) 1464 * 3 channels: 64 ( 64 x 3 = 192) 1465 * 4 channels: 64 ( 64 x 4 = 256) 1466 * 5 channels: 32 ( 32 x 5 = 160) 1467 * 6 channels: 32 ( 32 x 6 = 192) 1468 * 7 channels: 32 ( 32 x 7 = 224) 1469 * 8 channels: 32 ( 32 x 8 = 256) 1470 */ 1471 for (i = 1; i < fsi->chan_num; i <<= 1) 1472 frame_capa >>= 1; 1473 dev_dbg(dev, "%d channel %d store\n", 1474 fsi->chan_num, frame_capa); 1475 1476 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); 1477 1478 /* 1479 * set interrupt generation factor 1480 * clear FIFO 1481 */ 1482 if (is_play) { 1483 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); 1484 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); 1485 } else { 1486 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); 1487 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1488 } 1489 } 1490 1491 static int fsi_hw_startup(struct fsi_priv *fsi, 1492 struct fsi_stream *io, 1493 struct device *dev) 1494 { 1495 u32 data = 0; 1496 1497 /* clock setting */ 1498 if (fsi_is_clk_master(fsi)) 1499 data = DIMD | DOMD; 1500 1501 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); 1502 1503 /* clock inversion (CKG2) */ 1504 data = 0; 1505 if (fsi->bit_clk_inv) 1506 data |= (1 << 0); 1507 if (fsi->lr_clk_inv) 1508 data |= (1 << 4); 1509 if (fsi_is_clk_master(fsi)) 1510 data <<= 8; 1511 fsi_reg_write(fsi, CKG2, data); 1512 1513 /* spdif ? */ 1514 if (fsi_is_spdif(fsi)) { 1515 fsi_spdif_clk_ctrl(fsi, 1); 1516 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); 1517 } 1518 1519 /* 1520 * get bus settings 1521 */ 1522 data = 0; 1523 switch (io->sample_width) { 1524 case 2: 1525 data = BUSOP_GET(16, io->bus_option); 1526 break; 1527 case 4: 1528 data = BUSOP_GET(24, io->bus_option); 1529 break; 1530 } 1531 fsi_format_bus_setup(fsi, io, data, dev); 1532 1533 /* irq clear */ 1534 fsi_irq_disable(fsi, io); 1535 fsi_irq_clear_status(fsi); 1536 1537 /* fifo init */ 1538 fsi_fifo_init(fsi, io, dev); 1539 1540 /* start master clock */ 1541 if (fsi_is_clk_master(fsi)) 1542 return fsi_clk_enable(dev, fsi); 1543 1544 return 0; 1545 } 1546 1547 static int fsi_hw_shutdown(struct fsi_priv *fsi, 1548 struct device *dev) 1549 { 1550 /* stop master clock */ 1551 if (fsi_is_clk_master(fsi)) 1552 return fsi_clk_disable(dev, fsi); 1553 1554 return 0; 1555 } 1556 1557 static int fsi_dai_startup(struct snd_pcm_substream *substream, 1558 struct snd_soc_dai *dai) 1559 { 1560 struct fsi_priv *fsi = fsi_get_priv(substream); 1561 1562 fsi_clk_invalid(fsi); 1563 1564 return 0; 1565 } 1566 1567 static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 1568 struct snd_soc_dai *dai) 1569 { 1570 struct fsi_priv *fsi = fsi_get_priv(substream); 1571 1572 fsi_clk_invalid(fsi); 1573 } 1574 1575 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 1576 struct snd_soc_dai *dai) 1577 { 1578 struct fsi_priv *fsi = fsi_get_priv(substream); 1579 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1580 int ret = 0; 1581 1582 switch (cmd) { 1583 case SNDRV_PCM_TRIGGER_START: 1584 fsi_stream_init(fsi, io, substream); 1585 if (!ret) 1586 ret = fsi_hw_startup(fsi, io, dai->dev); 1587 if (!ret) 1588 ret = fsi_stream_start(fsi, io); 1589 if (!ret) 1590 ret = fsi_stream_transfer(io); 1591 break; 1592 case SNDRV_PCM_TRIGGER_STOP: 1593 if (!ret) 1594 ret = fsi_hw_shutdown(fsi, dai->dev); 1595 fsi_stream_stop(fsi, io); 1596 fsi_stream_quit(fsi, io); 1597 break; 1598 } 1599 1600 return ret; 1601 } 1602 1603 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) 1604 { 1605 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1606 case SND_SOC_DAIFMT_I2S: 1607 fsi->fmt = CR_I2S; 1608 fsi->chan_num = 2; 1609 break; 1610 case SND_SOC_DAIFMT_LEFT_J: 1611 fsi->fmt = CR_PCM; 1612 fsi->chan_num = 2; 1613 break; 1614 default: 1615 return -EINVAL; 1616 } 1617 1618 return 0; 1619 } 1620 1621 static int fsi_set_fmt_spdif(struct fsi_priv *fsi) 1622 { 1623 struct fsi_master *master = fsi_get_master(fsi); 1624 1625 if (fsi_version(master) < 2) 1626 return -EINVAL; 1627 1628 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; 1629 fsi->chan_num = 2; 1630 1631 return 0; 1632 } 1633 1634 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1635 { 1636 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); 1637 int ret; 1638 1639 /* set master/slave audio interface */ 1640 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1641 case SND_SOC_DAIFMT_CBM_CFM: 1642 break; 1643 case SND_SOC_DAIFMT_CBS_CFS: 1644 fsi->clk_master = 1; /* codec is slave, cpu is master */ 1645 break; 1646 default: 1647 return -EINVAL; 1648 } 1649 1650 /* set clock inversion */ 1651 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1652 case SND_SOC_DAIFMT_NB_IF: 1653 fsi->bit_clk_inv = 0; 1654 fsi->lr_clk_inv = 1; 1655 break; 1656 case SND_SOC_DAIFMT_IB_NF: 1657 fsi->bit_clk_inv = 1; 1658 fsi->lr_clk_inv = 0; 1659 break; 1660 case SND_SOC_DAIFMT_IB_IF: 1661 fsi->bit_clk_inv = 1; 1662 fsi->lr_clk_inv = 1; 1663 break; 1664 case SND_SOC_DAIFMT_NB_NF: 1665 default: 1666 fsi->bit_clk_inv = 0; 1667 fsi->lr_clk_inv = 0; 1668 break; 1669 } 1670 1671 if (fsi_is_clk_master(fsi)) { 1672 if (fsi->clk_cpg) 1673 fsi_clk_init(dai->dev, fsi, 0, 1, 1, 1674 fsi_clk_set_rate_cpg); 1675 else 1676 fsi_clk_init(dai->dev, fsi, 1, 1, 0, 1677 fsi_clk_set_rate_external); 1678 } 1679 1680 /* set format */ 1681 if (fsi_is_spdif(fsi)) 1682 ret = fsi_set_fmt_spdif(fsi); 1683 else 1684 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1685 1686 return ret; 1687 } 1688 1689 static int fsi_dai_hw_params(struct snd_pcm_substream *substream, 1690 struct snd_pcm_hw_params *params, 1691 struct snd_soc_dai *dai) 1692 { 1693 struct fsi_priv *fsi = fsi_get_priv(substream); 1694 1695 if (fsi_is_clk_master(fsi)) 1696 fsi_clk_valid(fsi, params_rate(params)); 1697 1698 return 0; 1699 } 1700 1701 static const struct snd_soc_dai_ops fsi_dai_ops = { 1702 .startup = fsi_dai_startup, 1703 .shutdown = fsi_dai_shutdown, 1704 .trigger = fsi_dai_trigger, 1705 .set_fmt = fsi_dai_set_fmt, 1706 .hw_params = fsi_dai_hw_params, 1707 }; 1708 1709 /* 1710 * pcm ops 1711 */ 1712 1713 static struct snd_pcm_hardware fsi_pcm_hardware = { 1714 .info = SNDRV_PCM_INFO_INTERLEAVED | 1715 SNDRV_PCM_INFO_MMAP | 1716 SNDRV_PCM_INFO_MMAP_VALID, 1717 .buffer_bytes_max = 64 * 1024, 1718 .period_bytes_min = 32, 1719 .period_bytes_max = 8192, 1720 .periods_min = 1, 1721 .periods_max = 32, 1722 .fifo_size = 256, 1723 }; 1724 1725 static int fsi_pcm_open(struct snd_pcm_substream *substream) 1726 { 1727 struct snd_pcm_runtime *runtime = substream->runtime; 1728 int ret = 0; 1729 1730 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 1731 1732 ret = snd_pcm_hw_constraint_integer(runtime, 1733 SNDRV_PCM_HW_PARAM_PERIODS); 1734 1735 return ret; 1736 } 1737 1738 static int fsi_hw_params(struct snd_pcm_substream *substream, 1739 struct snd_pcm_hw_params *hw_params) 1740 { 1741 return snd_pcm_lib_malloc_pages(substream, 1742 params_buffer_bytes(hw_params)); 1743 } 1744 1745 static int fsi_hw_free(struct snd_pcm_substream *substream) 1746 { 1747 return snd_pcm_lib_free_pages(substream); 1748 } 1749 1750 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) 1751 { 1752 struct fsi_priv *fsi = fsi_get_priv(substream); 1753 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1754 1755 return fsi_sample2frame(fsi, io->buff_sample_pos); 1756 } 1757 1758 static struct snd_pcm_ops fsi_pcm_ops = { 1759 .open = fsi_pcm_open, 1760 .ioctl = snd_pcm_lib_ioctl, 1761 .hw_params = fsi_hw_params, 1762 .hw_free = fsi_hw_free, 1763 .pointer = fsi_pointer, 1764 }; 1765 1766 /* 1767 * snd_soc_platform 1768 */ 1769 1770 #define PREALLOC_BUFFER (32 * 1024) 1771 #define PREALLOC_BUFFER_MAX (32 * 1024) 1772 1773 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) 1774 { 1775 return snd_pcm_lib_preallocate_pages_for_all( 1776 rtd->pcm, 1777 SNDRV_DMA_TYPE_DEV, 1778 rtd->card->snd_card->dev, 1779 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1780 } 1781 1782 /* 1783 * alsa struct 1784 */ 1785 1786 static struct snd_soc_dai_driver fsi_soc_dai[] = { 1787 { 1788 .name = "fsia-dai", 1789 .playback = { 1790 .rates = FSI_RATES, 1791 .formats = FSI_FMTS, 1792 .channels_min = 2, 1793 .channels_max = 2, 1794 }, 1795 .capture = { 1796 .rates = FSI_RATES, 1797 .formats = FSI_FMTS, 1798 .channels_min = 2, 1799 .channels_max = 2, 1800 }, 1801 .ops = &fsi_dai_ops, 1802 }, 1803 { 1804 .name = "fsib-dai", 1805 .playback = { 1806 .rates = FSI_RATES, 1807 .formats = FSI_FMTS, 1808 .channels_min = 2, 1809 .channels_max = 2, 1810 }, 1811 .capture = { 1812 .rates = FSI_RATES, 1813 .formats = FSI_FMTS, 1814 .channels_min = 2, 1815 .channels_max = 2, 1816 }, 1817 .ops = &fsi_dai_ops, 1818 }, 1819 }; 1820 1821 static struct snd_soc_platform_driver fsi_soc_platform = { 1822 .ops = &fsi_pcm_ops, 1823 .pcm_new = fsi_pcm_new, 1824 }; 1825 1826 static const struct snd_soc_component_driver fsi_soc_component = { 1827 .name = "fsi", 1828 }; 1829 1830 /* 1831 * platform function 1832 */ 1833 static void fsi_of_parse(char *name, 1834 struct device_node *np, 1835 struct sh_fsi_port_info *info, 1836 struct device *dev) 1837 { 1838 int i; 1839 char prop[128]; 1840 unsigned long flags = 0; 1841 struct { 1842 char *name; 1843 unsigned int val; 1844 } of_parse_property[] = { 1845 { "spdif-connection", SH_FSI_FMT_SPDIF }, 1846 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE }, 1847 { "use-internal-clock", SH_FSI_CLK_CPG }, 1848 }; 1849 1850 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) { 1851 sprintf(prop, "%s,%s", name, of_parse_property[i].name); 1852 if (of_get_property(np, prop, NULL)) 1853 flags |= of_parse_property[i].val; 1854 } 1855 info->flags = flags; 1856 1857 dev_dbg(dev, "%s flags : %lx\n", name, info->flags); 1858 } 1859 1860 static void fsi_port_info_init(struct fsi_priv *fsi, 1861 struct sh_fsi_port_info *info) 1862 { 1863 if (info->flags & SH_FSI_FMT_SPDIF) 1864 fsi->spdif = 1; 1865 1866 if (info->flags & SH_FSI_CLK_CPG) 1867 fsi->clk_cpg = 1; 1868 1869 if (info->flags & SH_FSI_ENABLE_STREAM_MODE) 1870 fsi->enable_stream = 1; 1871 } 1872 1873 static void fsi_handler_init(struct fsi_priv *fsi, 1874 struct sh_fsi_port_info *info) 1875 { 1876 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ 1877 fsi->playback.priv = fsi; 1878 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ 1879 fsi->capture.priv = fsi; 1880 1881 if (info->tx_id) { 1882 fsi->playback.dma_id = info->tx_id; 1883 fsi->playback.handler = &fsi_dma_push_handler; 1884 } 1885 } 1886 1887 static const struct fsi_core fsi1_core = { 1888 .ver = 1, 1889 1890 /* Interrupt */ 1891 .int_st = INT_ST, 1892 .iemsk = IEMSK, 1893 .imsk = IMSK, 1894 }; 1895 1896 static const struct fsi_core fsi2_core = { 1897 .ver = 2, 1898 1899 /* Interrupt */ 1900 .int_st = CPU_INT_ST, 1901 .iemsk = CPU_IEMSK, 1902 .imsk = CPU_IMSK, 1903 .a_mclk = A_MST_CTLR, 1904 .b_mclk = B_MST_CTLR, 1905 }; 1906 1907 static const struct of_device_id fsi_of_match[] = { 1908 { .compatible = "renesas,sh_fsi", .data = &fsi1_core}, 1909 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core}, 1910 {}, 1911 }; 1912 MODULE_DEVICE_TABLE(of, fsi_of_match); 1913 1914 static const struct platform_device_id fsi_id_table[] = { 1915 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, 1916 {}, 1917 }; 1918 MODULE_DEVICE_TABLE(platform, fsi_id_table); 1919 1920 static int fsi_probe(struct platform_device *pdev) 1921 { 1922 struct fsi_master *master; 1923 struct device_node *np = pdev->dev.of_node; 1924 struct sh_fsi_platform_info info; 1925 const struct fsi_core *core; 1926 struct fsi_priv *fsi; 1927 struct resource *res; 1928 unsigned int irq; 1929 int ret; 1930 1931 memset(&info, 0, sizeof(info)); 1932 1933 core = NULL; 1934 if (np) { 1935 const struct of_device_id *of_id; 1936 1937 of_id = of_match_device(fsi_of_match, &pdev->dev); 1938 if (of_id) { 1939 core = of_id->data; 1940 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev); 1941 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev); 1942 } 1943 } else { 1944 const struct platform_device_id *id_entry = pdev->id_entry; 1945 if (id_entry) 1946 core = (struct fsi_core *)id_entry->driver_data; 1947 1948 if (pdev->dev.platform_data) 1949 memcpy(&info, pdev->dev.platform_data, sizeof(info)); 1950 } 1951 1952 if (!core) { 1953 dev_err(&pdev->dev, "unknown fsi device\n"); 1954 return -ENODEV; 1955 } 1956 1957 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1958 irq = platform_get_irq(pdev, 0); 1959 if (!res || (int)irq <= 0) { 1960 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 1961 return -ENODEV; 1962 } 1963 1964 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1965 if (!master) { 1966 dev_err(&pdev->dev, "Could not allocate master\n"); 1967 return -ENOMEM; 1968 } 1969 1970 master->base = devm_ioremap_nocache(&pdev->dev, 1971 res->start, resource_size(res)); 1972 if (!master->base) { 1973 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 1974 return -ENXIO; 1975 } 1976 1977 /* master setting */ 1978 master->core = core; 1979 spin_lock_init(&master->lock); 1980 1981 /* FSI A setting */ 1982 fsi = &master->fsia; 1983 fsi->base = master->base; 1984 fsi->phys = res->start; 1985 fsi->master = master; 1986 fsi_port_info_init(fsi, &info.port_a); 1987 fsi_handler_init(fsi, &info.port_a); 1988 ret = fsi_stream_probe(fsi, &pdev->dev); 1989 if (ret < 0) { 1990 dev_err(&pdev->dev, "FSIA stream probe failed\n"); 1991 return ret; 1992 } 1993 1994 /* FSI B setting */ 1995 fsi = &master->fsib; 1996 fsi->base = master->base + 0x40; 1997 fsi->phys = res->start + 0x40; 1998 fsi->master = master; 1999 fsi_port_info_init(fsi, &info.port_b); 2000 fsi_handler_init(fsi, &info.port_b); 2001 ret = fsi_stream_probe(fsi, &pdev->dev); 2002 if (ret < 0) { 2003 dev_err(&pdev->dev, "FSIB stream probe failed\n"); 2004 goto exit_fsia; 2005 } 2006 2007 pm_runtime_enable(&pdev->dev); 2008 dev_set_drvdata(&pdev->dev, master); 2009 2010 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, 2011 dev_name(&pdev->dev), master); 2012 if (ret) { 2013 dev_err(&pdev->dev, "irq request err\n"); 2014 goto exit_fsib; 2015 } 2016 2017 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); 2018 if (ret < 0) { 2019 dev_err(&pdev->dev, "cannot snd soc register\n"); 2020 goto exit_fsib; 2021 } 2022 2023 ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component, 2024 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 2025 if (ret < 0) { 2026 dev_err(&pdev->dev, "cannot snd component register\n"); 2027 goto exit_snd_soc; 2028 } 2029 2030 return ret; 2031 2032 exit_snd_soc: 2033 snd_soc_unregister_platform(&pdev->dev); 2034 exit_fsib: 2035 pm_runtime_disable(&pdev->dev); 2036 fsi_stream_remove(&master->fsib); 2037 exit_fsia: 2038 fsi_stream_remove(&master->fsia); 2039 2040 return ret; 2041 } 2042 2043 static int fsi_remove(struct platform_device *pdev) 2044 { 2045 struct fsi_master *master; 2046 2047 master = dev_get_drvdata(&pdev->dev); 2048 2049 pm_runtime_disable(&pdev->dev); 2050 2051 snd_soc_unregister_component(&pdev->dev); 2052 snd_soc_unregister_platform(&pdev->dev); 2053 2054 fsi_stream_remove(&master->fsia); 2055 fsi_stream_remove(&master->fsib); 2056 2057 return 0; 2058 } 2059 2060 static void __fsi_suspend(struct fsi_priv *fsi, 2061 struct fsi_stream *io, 2062 struct device *dev) 2063 { 2064 if (!fsi_stream_is_working(fsi, io)) 2065 return; 2066 2067 fsi_stream_stop(fsi, io); 2068 fsi_hw_shutdown(fsi, dev); 2069 } 2070 2071 static void __fsi_resume(struct fsi_priv *fsi, 2072 struct fsi_stream *io, 2073 struct device *dev) 2074 { 2075 if (!fsi_stream_is_working(fsi, io)) 2076 return; 2077 2078 fsi_hw_startup(fsi, io, dev); 2079 fsi_stream_start(fsi, io); 2080 } 2081 2082 static int fsi_suspend(struct device *dev) 2083 { 2084 struct fsi_master *master = dev_get_drvdata(dev); 2085 struct fsi_priv *fsia = &master->fsia; 2086 struct fsi_priv *fsib = &master->fsib; 2087 2088 __fsi_suspend(fsia, &fsia->playback, dev); 2089 __fsi_suspend(fsia, &fsia->capture, dev); 2090 2091 __fsi_suspend(fsib, &fsib->playback, dev); 2092 __fsi_suspend(fsib, &fsib->capture, dev); 2093 2094 return 0; 2095 } 2096 2097 static int fsi_resume(struct device *dev) 2098 { 2099 struct fsi_master *master = dev_get_drvdata(dev); 2100 struct fsi_priv *fsia = &master->fsia; 2101 struct fsi_priv *fsib = &master->fsib; 2102 2103 __fsi_resume(fsia, &fsia->playback, dev); 2104 __fsi_resume(fsia, &fsia->capture, dev); 2105 2106 __fsi_resume(fsib, &fsib->playback, dev); 2107 __fsi_resume(fsib, &fsib->capture, dev); 2108 2109 return 0; 2110 } 2111 2112 static struct dev_pm_ops fsi_pm_ops = { 2113 .suspend = fsi_suspend, 2114 .resume = fsi_resume, 2115 }; 2116 2117 static struct platform_driver fsi_driver = { 2118 .driver = { 2119 .name = "fsi-pcm-audio", 2120 .pm = &fsi_pm_ops, 2121 .of_match_table = fsi_of_match, 2122 }, 2123 .probe = fsi_probe, 2124 .remove = fsi_remove, 2125 .id_table = fsi_id_table, 2126 }; 2127 2128 module_platform_driver(fsi_driver); 2129 2130 MODULE_LICENSE("GPL v2"); 2131 MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); 2132 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 2133 MODULE_ALIAS("platform:fsi-pcm-audio"); 2134