1 /* 2 * Fifo-attached Serial Interface (FSI) support for SH7724 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on ssi.c 8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/delay.h> 19 #include <linux/list.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/io.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/initval.h> 25 #include <sound/soc.h> 26 #include <sound/pcm_params.h> 27 #include <sound/sh_fsi.h> 28 #include <asm/atomic.h> 29 30 #define DO_FMT 0x0000 31 #define DOFF_CTL 0x0004 32 #define DOFF_ST 0x0008 33 #define DI_FMT 0x000C 34 #define DIFF_CTL 0x0010 35 #define DIFF_ST 0x0014 36 #define CKG1 0x0018 37 #define CKG2 0x001C 38 #define DIDT 0x0020 39 #define DODT 0x0024 40 #define MUTE_ST 0x0028 41 #define REG_END MUTE_ST 42 43 #define INT_ST 0x0200 44 #define IEMSK 0x0204 45 #define IMSK 0x0208 46 #define MUTE 0x020C 47 #define CLK_RST 0x0210 48 #define SOFT_RST 0x0214 49 #define MREG_START INT_ST 50 #define MREG_END SOFT_RST 51 52 /* DO_FMT */ 53 /* DI_FMT */ 54 #define CR_FMT(param) ((param) << 4) 55 # define CR_MONO 0x0 56 # define CR_MONO_D 0x1 57 # define CR_PCM 0x2 58 # define CR_I2S 0x3 59 # define CR_TDM 0x4 60 # define CR_TDM_D 0x5 61 62 /* DOFF_CTL */ 63 /* DIFF_CTL */ 64 #define IRQ_HALF 0x00100000 65 #define FIFO_CLR 0x00000001 66 67 /* DOFF_ST */ 68 #define ERR_OVER 0x00000010 69 #define ERR_UNDER 0x00000001 70 71 /* CLK_RST */ 72 #define B_CLK 0x00000010 73 #define A_CLK 0x00000001 74 75 /* INT_ST */ 76 #define INT_B_IN (1 << 12) 77 #define INT_B_OUT (1 << 8) 78 #define INT_A_IN (1 << 4) 79 #define INT_A_OUT (1 << 0) 80 81 #define FSI_RATES SNDRV_PCM_RATE_8000_96000 82 83 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 84 85 /************************************************************************ 86 87 88 struct 89 90 91 ************************************************************************/ 92 struct fsi_priv { 93 void __iomem *base; 94 struct snd_pcm_substream *substream; 95 96 int fifo_max; 97 int chan; 98 99 int byte_offset; 100 int period_len; 101 int buffer_len; 102 int periods; 103 }; 104 105 struct fsi_master { 106 void __iomem *base; 107 int irq; 108 struct fsi_priv fsia; 109 struct fsi_priv fsib; 110 struct sh_fsi_platform_info *info; 111 }; 112 113 static struct fsi_master *master; 114 115 /************************************************************************ 116 117 118 basic read write function 119 120 121 ************************************************************************/ 122 static int __fsi_reg_write(u32 reg, u32 data) 123 { 124 /* valid data area is 24bit */ 125 data &= 0x00ffffff; 126 127 return ctrl_outl(data, reg); 128 } 129 130 static u32 __fsi_reg_read(u32 reg) 131 { 132 return ctrl_inl(reg); 133 } 134 135 static int __fsi_reg_mask_set(u32 reg, u32 mask, u32 data) 136 { 137 u32 val = __fsi_reg_read(reg); 138 139 val &= ~mask; 140 val |= data & mask; 141 142 return __fsi_reg_write(reg, val); 143 } 144 145 static int fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data) 146 { 147 if (reg > REG_END) 148 return -1; 149 150 return __fsi_reg_write((u32)(fsi->base + reg), data); 151 } 152 153 static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg) 154 { 155 if (reg > REG_END) 156 return 0; 157 158 return __fsi_reg_read((u32)(fsi->base + reg)); 159 } 160 161 static int fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data) 162 { 163 if (reg > REG_END) 164 return -1; 165 166 return __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data); 167 } 168 169 static int fsi_master_write(u32 reg, u32 data) 170 { 171 if ((reg < MREG_START) || 172 (reg > MREG_END)) 173 return -1; 174 175 return __fsi_reg_write((u32)(master->base + reg), data); 176 } 177 178 static u32 fsi_master_read(u32 reg) 179 { 180 if ((reg < MREG_START) || 181 (reg > MREG_END)) 182 return 0; 183 184 return __fsi_reg_read((u32)(master->base + reg)); 185 } 186 187 static int fsi_master_mask_set(u32 reg, u32 mask, u32 data) 188 { 189 if ((reg < MREG_START) || 190 (reg > MREG_END)) 191 return -1; 192 193 return __fsi_reg_mask_set((u32)(master->base + reg), mask, data); 194 } 195 196 /************************************************************************ 197 198 199 basic function 200 201 202 ************************************************************************/ 203 static struct fsi_priv *fsi_get(struct snd_pcm_substream *substream) 204 { 205 struct snd_soc_pcm_runtime *rtd; 206 struct fsi_priv *fsi = NULL; 207 208 if (!substream || !master) 209 return NULL; 210 211 rtd = substream->private_data; 212 switch (rtd->dai->cpu_dai->id) { 213 case 0: 214 fsi = &master->fsia; 215 break; 216 case 1: 217 fsi = &master->fsib; 218 break; 219 } 220 221 return fsi; 222 } 223 224 static int fsi_is_port_a(struct fsi_priv *fsi) 225 { 226 /* return 227 * 1 : port a 228 * 0 : port b 229 */ 230 231 if (fsi == &master->fsia) 232 return 1; 233 234 return 0; 235 } 236 237 static u32 fsi_get_info_flags(struct fsi_priv *fsi) 238 { 239 int is_porta = fsi_is_port_a(fsi); 240 241 return is_porta ? master->info->porta_flags : 242 master->info->portb_flags; 243 } 244 245 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play) 246 { 247 u32 mode; 248 u32 flags = fsi_get_info_flags(fsi); 249 250 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE; 251 252 /* return 253 * 1 : master mode 254 * 0 : slave mode 255 */ 256 257 return (mode & flags) != mode; 258 } 259 260 static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play) 261 { 262 int is_porta = fsi_is_port_a(fsi); 263 u32 data; 264 265 if (is_porta) 266 data = is_play ? (1 << 0) : (1 << 4); 267 else 268 data = is_play ? (1 << 8) : (1 << 12); 269 270 return data; 271 } 272 273 static void fsi_stream_push(struct fsi_priv *fsi, 274 struct snd_pcm_substream *substream, 275 u32 buffer_len, 276 u32 period_len) 277 { 278 fsi->substream = substream; 279 fsi->buffer_len = buffer_len; 280 fsi->period_len = period_len; 281 fsi->byte_offset = 0; 282 fsi->periods = 0; 283 } 284 285 static void fsi_stream_pop(struct fsi_priv *fsi) 286 { 287 fsi->substream = NULL; 288 fsi->buffer_len = 0; 289 fsi->period_len = 0; 290 fsi->byte_offset = 0; 291 fsi->periods = 0; 292 } 293 294 static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play) 295 { 296 u32 status; 297 u32 reg = is_play ? DOFF_ST : DIFF_ST; 298 int residue; 299 300 status = fsi_reg_read(fsi, reg); 301 residue = 0x1ff & (status >> 8); 302 residue *= fsi->chan; 303 304 return residue; 305 } 306 307 /************************************************************************ 308 309 310 ctrl function 311 312 313 ************************************************************************/ 314 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play) 315 { 316 u32 data = fsi_port_ab_io_bit(fsi, is_play); 317 318 fsi_master_mask_set(IMSK, data, data); 319 fsi_master_mask_set(IEMSK, data, data); 320 } 321 322 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play) 323 { 324 u32 data = fsi_port_ab_io_bit(fsi, is_play); 325 326 fsi_master_mask_set(IMSK, data, 0); 327 fsi_master_mask_set(IEMSK, data, 0); 328 } 329 330 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable) 331 { 332 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4); 333 334 if (enable) 335 fsi_master_mask_set(CLK_RST, val, val); 336 else 337 fsi_master_mask_set(CLK_RST, val, 0); 338 } 339 340 static void fsi_irq_init(struct fsi_priv *fsi, int is_play) 341 { 342 u32 data; 343 u32 ctrl; 344 345 data = fsi_port_ab_io_bit(fsi, is_play); 346 ctrl = is_play ? DOFF_CTL : DIFF_CTL; 347 348 /* set IMSK */ 349 fsi_irq_disable(fsi, is_play); 350 351 /* set interrupt generation factor */ 352 fsi_reg_write(fsi, ctrl, IRQ_HALF); 353 354 /* clear FIFO */ 355 fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR); 356 357 /* clear interrupt factor */ 358 fsi_master_mask_set(INT_ST, data, 0); 359 } 360 361 static void fsi_soft_all_reset(void) 362 { 363 u32 status = fsi_master_read(SOFT_RST); 364 365 /* port AB reset */ 366 status &= 0x000000ff; 367 fsi_master_write(SOFT_RST, status); 368 mdelay(10); 369 370 /* soft reset */ 371 status &= 0x000000f0; 372 fsi_master_write(SOFT_RST, status); 373 status |= 0x00000001; 374 fsi_master_write(SOFT_RST, status); 375 mdelay(10); 376 } 377 378 /* playback interrupt */ 379 static int fsi_data_push(struct fsi_priv *fsi) 380 { 381 struct snd_pcm_runtime *runtime; 382 struct snd_pcm_substream *substream = NULL; 383 int send; 384 int fifo_free; 385 int width; 386 u8 *start; 387 int i; 388 389 if (!fsi || 390 !fsi->substream || 391 !fsi->substream->runtime) 392 return -EINVAL; 393 394 runtime = fsi->substream->runtime; 395 396 /* FSI FIFO has limit. 397 * So, this driver can not send periods data at a time 398 */ 399 if (fsi->byte_offset >= 400 fsi->period_len * (fsi->periods + 1)) { 401 402 substream = fsi->substream; 403 fsi->periods = (fsi->periods + 1) % runtime->periods; 404 405 if (0 == fsi->periods) 406 fsi->byte_offset = 0; 407 } 408 409 /* get 1 channel data width */ 410 width = frames_to_bytes(runtime, 1) / fsi->chan; 411 412 /* get send size for alsa */ 413 send = (fsi->buffer_len - fsi->byte_offset) / width; 414 415 /* get FIFO free size */ 416 fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1); 417 418 /* size check */ 419 if (fifo_free < send) 420 send = fifo_free; 421 422 start = runtime->dma_area; 423 start += fsi->byte_offset; 424 425 switch (width) { 426 case 2: 427 for (i = 0; i < send; i++) 428 fsi_reg_write(fsi, DODT, 429 ((u32)*((u16 *)start + i) << 8)); 430 break; 431 case 4: 432 for (i = 0; i < send; i++) 433 fsi_reg_write(fsi, DODT, *((u32 *)start + i)); 434 break; 435 default: 436 return -EINVAL; 437 } 438 439 fsi->byte_offset += send * width; 440 441 fsi_irq_enable(fsi, 1); 442 443 if (substream) 444 snd_pcm_period_elapsed(substream); 445 446 return 0; 447 } 448 449 static int fsi_data_pop(struct fsi_priv *fsi) 450 { 451 struct snd_pcm_runtime *runtime; 452 struct snd_pcm_substream *substream = NULL; 453 int free; 454 int fifo_fill; 455 int width; 456 u8 *start; 457 int i; 458 459 if (!fsi || 460 !fsi->substream || 461 !fsi->substream->runtime) 462 return -EINVAL; 463 464 runtime = fsi->substream->runtime; 465 466 /* FSI FIFO has limit. 467 * So, this driver can not send periods data at a time 468 */ 469 if (fsi->byte_offset >= 470 fsi->period_len * (fsi->periods + 1)) { 471 472 substream = fsi->substream; 473 fsi->periods = (fsi->periods + 1) % runtime->periods; 474 475 if (0 == fsi->periods) 476 fsi->byte_offset = 0; 477 } 478 479 /* get 1 channel data width */ 480 width = frames_to_bytes(runtime, 1) / fsi->chan; 481 482 /* get free space for alsa */ 483 free = (fsi->buffer_len - fsi->byte_offset) / width; 484 485 /* get recv size */ 486 fifo_fill = fsi_get_fifo_residue(fsi, 0); 487 488 if (free < fifo_fill) 489 fifo_fill = free; 490 491 start = runtime->dma_area; 492 start += fsi->byte_offset; 493 494 switch (width) { 495 case 2: 496 for (i = 0; i < fifo_fill; i++) 497 *((u16 *)start + i) = 498 (u16)(fsi_reg_read(fsi, DIDT) >> 8); 499 break; 500 case 4: 501 for (i = 0; i < fifo_fill; i++) 502 *((u32 *)start + i) = fsi_reg_read(fsi, DIDT); 503 break; 504 default: 505 return -EINVAL; 506 } 507 508 fsi->byte_offset += fifo_fill * width; 509 510 fsi_irq_enable(fsi, 0); 511 512 if (substream) 513 snd_pcm_period_elapsed(substream); 514 515 return 0; 516 } 517 518 static irqreturn_t fsi_interrupt(int irq, void *data) 519 { 520 u32 status = fsi_master_read(SOFT_RST) & ~0x00000010; 521 u32 int_st = fsi_master_read(INT_ST); 522 523 /* clear irq status */ 524 fsi_master_write(SOFT_RST, status); 525 fsi_master_write(SOFT_RST, status | 0x00000010); 526 527 if (int_st & INT_A_OUT) 528 fsi_data_push(&master->fsia); 529 if (int_st & INT_B_OUT) 530 fsi_data_push(&master->fsib); 531 if (int_st & INT_A_IN) 532 fsi_data_pop(&master->fsia); 533 if (int_st & INT_B_IN) 534 fsi_data_pop(&master->fsib); 535 536 fsi_master_write(INT_ST, 0x0000000); 537 538 return IRQ_HANDLED; 539 } 540 541 /************************************************************************ 542 543 544 dai ops 545 546 547 ************************************************************************/ 548 static int fsi_dai_startup(struct snd_pcm_substream *substream, 549 struct snd_soc_dai *dai) 550 { 551 struct fsi_priv *fsi = fsi_get(substream); 552 const char *msg; 553 u32 flags = fsi_get_info_flags(fsi); 554 u32 fmt; 555 u32 reg; 556 u32 data; 557 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 558 int is_master; 559 int ret = 0; 560 561 pm_runtime_get_sync(dai->dev); 562 563 /* CKG1 */ 564 data = is_play ? (1 << 0) : (1 << 4); 565 is_master = fsi_is_master_mode(fsi, is_play); 566 if (is_master) 567 fsi_reg_mask_set(fsi, CKG1, data, data); 568 else 569 fsi_reg_mask_set(fsi, CKG1, data, 0); 570 571 /* clock inversion (CKG2) */ 572 data = 0; 573 switch (SH_FSI_INVERSION_MASK & flags) { 574 case SH_FSI_LRM_INV: 575 data = 1 << 12; 576 break; 577 case SH_FSI_BRM_INV: 578 data = 1 << 8; 579 break; 580 case SH_FSI_LRS_INV: 581 data = 1 << 4; 582 break; 583 case SH_FSI_BRS_INV: 584 data = 1 << 0; 585 break; 586 } 587 fsi_reg_write(fsi, CKG2, data); 588 589 /* do fmt, di fmt */ 590 data = 0; 591 reg = is_play ? DO_FMT : DI_FMT; 592 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags); 593 switch (fmt) { 594 case SH_FSI_FMT_MONO: 595 msg = "MONO"; 596 data = CR_FMT(CR_MONO); 597 fsi->chan = 1; 598 break; 599 case SH_FSI_FMT_MONO_DELAY: 600 msg = "MONO Delay"; 601 data = CR_FMT(CR_MONO_D); 602 fsi->chan = 1; 603 break; 604 case SH_FSI_FMT_PCM: 605 msg = "PCM"; 606 data = CR_FMT(CR_PCM); 607 fsi->chan = 2; 608 break; 609 case SH_FSI_FMT_I2S: 610 msg = "I2S"; 611 data = CR_FMT(CR_I2S); 612 fsi->chan = 2; 613 break; 614 case SH_FSI_FMT_TDM: 615 msg = "TDM"; 616 data = CR_FMT(CR_TDM) | (fsi->chan - 1); 617 fsi->chan = is_play ? 618 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); 619 break; 620 case SH_FSI_FMT_TDM_DELAY: 621 msg = "TDM Delay"; 622 data = CR_FMT(CR_TDM_D) | (fsi->chan - 1); 623 fsi->chan = is_play ? 624 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags); 625 break; 626 default: 627 dev_err(dai->dev, "unknown format.\n"); 628 return -EINVAL; 629 } 630 631 switch (fsi->chan) { 632 case 1: 633 fsi->fifo_max = 256; 634 break; 635 case 2: 636 fsi->fifo_max = 128; 637 break; 638 case 3: 639 case 4: 640 fsi->fifo_max = 64; 641 break; 642 case 5: 643 case 6: 644 case 7: 645 case 8: 646 fsi->fifo_max = 32; 647 break; 648 default: 649 dev_err(dai->dev, "channel size error.\n"); 650 return -EINVAL; 651 } 652 653 fsi_reg_write(fsi, reg, data); 654 655 /* 656 * clear clk reset if master mode 657 */ 658 if (is_master) 659 fsi_clk_ctrl(fsi, 1); 660 661 /* irq setting */ 662 fsi_irq_init(fsi, is_play); 663 664 return ret; 665 } 666 667 static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 668 struct snd_soc_dai *dai) 669 { 670 struct fsi_priv *fsi = fsi_get(substream); 671 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 672 673 fsi_irq_disable(fsi, is_play); 674 fsi_clk_ctrl(fsi, 0); 675 676 pm_runtime_put_sync(dai->dev); 677 } 678 679 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 680 struct snd_soc_dai *dai) 681 { 682 struct fsi_priv *fsi = fsi_get(substream); 683 struct snd_pcm_runtime *runtime = substream->runtime; 684 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 685 int ret = 0; 686 687 switch (cmd) { 688 case SNDRV_PCM_TRIGGER_START: 689 fsi_stream_push(fsi, substream, 690 frames_to_bytes(runtime, runtime->buffer_size), 691 frames_to_bytes(runtime, runtime->period_size)); 692 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); 693 break; 694 case SNDRV_PCM_TRIGGER_STOP: 695 fsi_irq_disable(fsi, is_play); 696 fsi_stream_pop(fsi); 697 break; 698 } 699 700 return ret; 701 } 702 703 static struct snd_soc_dai_ops fsi_dai_ops = { 704 .startup = fsi_dai_startup, 705 .shutdown = fsi_dai_shutdown, 706 .trigger = fsi_dai_trigger, 707 }; 708 709 /************************************************************************ 710 711 712 pcm ops 713 714 715 ************************************************************************/ 716 static struct snd_pcm_hardware fsi_pcm_hardware = { 717 .info = SNDRV_PCM_INFO_INTERLEAVED | 718 SNDRV_PCM_INFO_MMAP | 719 SNDRV_PCM_INFO_MMAP_VALID | 720 SNDRV_PCM_INFO_PAUSE, 721 .formats = FSI_FMTS, 722 .rates = FSI_RATES, 723 .rate_min = 8000, 724 .rate_max = 192000, 725 .channels_min = 1, 726 .channels_max = 2, 727 .buffer_bytes_max = 64 * 1024, 728 .period_bytes_min = 32, 729 .period_bytes_max = 8192, 730 .periods_min = 1, 731 .periods_max = 32, 732 .fifo_size = 256, 733 }; 734 735 static int fsi_pcm_open(struct snd_pcm_substream *substream) 736 { 737 struct snd_pcm_runtime *runtime = substream->runtime; 738 int ret = 0; 739 740 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 741 742 ret = snd_pcm_hw_constraint_integer(runtime, 743 SNDRV_PCM_HW_PARAM_PERIODS); 744 745 return ret; 746 } 747 748 static int fsi_hw_params(struct snd_pcm_substream *substream, 749 struct snd_pcm_hw_params *hw_params) 750 { 751 return snd_pcm_lib_malloc_pages(substream, 752 params_buffer_bytes(hw_params)); 753 } 754 755 static int fsi_hw_free(struct snd_pcm_substream *substream) 756 { 757 return snd_pcm_lib_free_pages(substream); 758 } 759 760 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) 761 { 762 struct snd_pcm_runtime *runtime = substream->runtime; 763 struct fsi_priv *fsi = fsi_get(substream); 764 long location; 765 766 location = (fsi->byte_offset - 1); 767 if (location < 0) 768 location = 0; 769 770 return bytes_to_frames(runtime, location); 771 } 772 773 static struct snd_pcm_ops fsi_pcm_ops = { 774 .open = fsi_pcm_open, 775 .ioctl = snd_pcm_lib_ioctl, 776 .hw_params = fsi_hw_params, 777 .hw_free = fsi_hw_free, 778 .pointer = fsi_pointer, 779 }; 780 781 /************************************************************************ 782 783 784 snd_soc_platform 785 786 787 ************************************************************************/ 788 #define PREALLOC_BUFFER (32 * 1024) 789 #define PREALLOC_BUFFER_MAX (32 * 1024) 790 791 static void fsi_pcm_free(struct snd_pcm *pcm) 792 { 793 snd_pcm_lib_preallocate_free_for_all(pcm); 794 } 795 796 static int fsi_pcm_new(struct snd_card *card, 797 struct snd_soc_dai *dai, 798 struct snd_pcm *pcm) 799 { 800 /* 801 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel 802 * in MMAP mode (i.e. aplay -M) 803 */ 804 return snd_pcm_lib_preallocate_pages_for_all( 805 pcm, 806 SNDRV_DMA_TYPE_CONTINUOUS, 807 snd_dma_continuous_data(GFP_KERNEL), 808 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 809 } 810 811 /************************************************************************ 812 813 814 alsa struct 815 816 817 ************************************************************************/ 818 struct snd_soc_dai fsi_soc_dai[] = { 819 { 820 .name = "FSIA", 821 .id = 0, 822 .playback = { 823 .rates = FSI_RATES, 824 .formats = FSI_FMTS, 825 .channels_min = 1, 826 .channels_max = 8, 827 }, 828 .capture = { 829 .rates = FSI_RATES, 830 .formats = FSI_FMTS, 831 .channels_min = 1, 832 .channels_max = 8, 833 }, 834 .ops = &fsi_dai_ops, 835 }, 836 { 837 .name = "FSIB", 838 .id = 1, 839 .playback = { 840 .rates = FSI_RATES, 841 .formats = FSI_FMTS, 842 .channels_min = 1, 843 .channels_max = 8, 844 }, 845 .capture = { 846 .rates = FSI_RATES, 847 .formats = FSI_FMTS, 848 .channels_min = 1, 849 .channels_max = 8, 850 }, 851 .ops = &fsi_dai_ops, 852 }, 853 }; 854 EXPORT_SYMBOL_GPL(fsi_soc_dai); 855 856 struct snd_soc_platform fsi_soc_platform = { 857 .name = "fsi-pcm", 858 .pcm_ops = &fsi_pcm_ops, 859 .pcm_new = fsi_pcm_new, 860 .pcm_free = fsi_pcm_free, 861 }; 862 EXPORT_SYMBOL_GPL(fsi_soc_platform); 863 864 /************************************************************************ 865 866 867 platform function 868 869 870 ************************************************************************/ 871 static int fsi_probe(struct platform_device *pdev) 872 { 873 struct resource *res; 874 unsigned int irq; 875 int ret; 876 877 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 878 irq = platform_get_irq(pdev, 0); 879 if (!res || (int)irq <= 0) { 880 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 881 ret = -ENODEV; 882 goto exit; 883 } 884 885 master = kzalloc(sizeof(*master), GFP_KERNEL); 886 if (!master) { 887 dev_err(&pdev->dev, "Could not allocate master\n"); 888 ret = -ENOMEM; 889 goto exit; 890 } 891 892 master->base = ioremap_nocache(res->start, resource_size(res)); 893 if (!master->base) { 894 ret = -ENXIO; 895 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 896 goto exit_kfree; 897 } 898 899 master->irq = irq; 900 master->info = pdev->dev.platform_data; 901 master->fsia.base = master->base; 902 master->fsib.base = master->base + 0x40; 903 904 pm_runtime_enable(&pdev->dev); 905 pm_runtime_resume(&pdev->dev); 906 907 fsi_soc_dai[0].dev = &pdev->dev; 908 fsi_soc_dai[1].dev = &pdev->dev; 909 910 fsi_soft_all_reset(); 911 912 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, "fsi", master); 913 if (ret) { 914 dev_err(&pdev->dev, "irq request err\n"); 915 goto exit_iounmap; 916 } 917 918 ret = snd_soc_register_platform(&fsi_soc_platform); 919 if (ret < 0) { 920 dev_err(&pdev->dev, "cannot snd soc register\n"); 921 goto exit_free_irq; 922 } 923 924 return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 925 926 exit_free_irq: 927 free_irq(irq, master); 928 exit_iounmap: 929 iounmap(master->base); 930 pm_runtime_disable(&pdev->dev); 931 exit_kfree: 932 kfree(master); 933 master = NULL; 934 exit: 935 return ret; 936 } 937 938 static int fsi_remove(struct platform_device *pdev) 939 { 940 snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 941 snd_soc_unregister_platform(&fsi_soc_platform); 942 943 pm_runtime_disable(&pdev->dev); 944 945 free_irq(master->irq, master); 946 947 iounmap(master->base); 948 kfree(master); 949 master = NULL; 950 return 0; 951 } 952 953 static int fsi_runtime_nop(struct device *dev) 954 { 955 /* Runtime PM callback shared between ->runtime_suspend() 956 * and ->runtime_resume(). Simply returns success. 957 * 958 * This driver re-initializes all registers after 959 * pm_runtime_get_sync() anyway so there is no need 960 * to save and restore registers here. 961 */ 962 return 0; 963 } 964 965 static struct dev_pm_ops fsi_pm_ops = { 966 .runtime_suspend = fsi_runtime_nop, 967 .runtime_resume = fsi_runtime_nop, 968 }; 969 970 static struct platform_driver fsi_driver = { 971 .driver = { 972 .name = "sh_fsi", 973 .pm = &fsi_pm_ops, 974 }, 975 .probe = fsi_probe, 976 .remove = fsi_remove, 977 }; 978 979 static int __init fsi_mobile_init(void) 980 { 981 return platform_driver_register(&fsi_driver); 982 } 983 984 static void __exit fsi_mobile_exit(void) 985 { 986 platform_driver_unregister(&fsi_driver); 987 } 988 module_init(fsi_mobile_init); 989 module_exit(fsi_mobile_exit); 990 991 MODULE_LICENSE("GPL"); 992 MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); 993 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 994