1 /* 2 * Fifo-attached Serial Interface (FSI) support for SH7724 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on ssi.c 8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/scatterlist.h> 22 #include <linux/sh_dma.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/workqueue.h> 26 #include <sound/soc.h> 27 #include <sound/pcm_params.h> 28 #include <sound/sh_fsi.h> 29 30 /* PortA/PortB register */ 31 #define REG_DO_FMT 0x0000 32 #define REG_DOFF_CTL 0x0004 33 #define REG_DOFF_ST 0x0008 34 #define REG_DI_FMT 0x000C 35 #define REG_DIFF_CTL 0x0010 36 #define REG_DIFF_ST 0x0014 37 #define REG_CKG1 0x0018 38 #define REG_CKG2 0x001C 39 #define REG_DIDT 0x0020 40 #define REG_DODT 0x0024 41 #define REG_MUTE_ST 0x0028 42 #define REG_OUT_DMAC 0x002C 43 #define REG_OUT_SEL 0x0030 44 #define REG_IN_DMAC 0x0038 45 46 /* master register */ 47 #define MST_CLK_RST 0x0210 48 #define MST_SOFT_RST 0x0214 49 #define MST_FIFO_SZ 0x0218 50 51 /* core register (depend on FSI version) */ 52 #define A_MST_CTLR 0x0180 53 #define B_MST_CTLR 0x01A0 54 #define CPU_INT_ST 0x01F4 55 #define CPU_IEMSK 0x01F8 56 #define CPU_IMSK 0x01FC 57 #define INT_ST 0x0200 58 #define IEMSK 0x0204 59 #define IMSK 0x0208 60 61 /* DO_FMT */ 62 /* DI_FMT */ 63 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */ 64 #define CR_BWS_24 (0x0 << 20) /* FSI2 */ 65 #define CR_BWS_16 (0x1 << 20) /* FSI2 */ 66 #define CR_BWS_20 (0x2 << 20) /* FSI2 */ 67 68 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ 69 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ 70 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ 71 72 #define CR_MONO (0x0 << 4) 73 #define CR_MONO_D (0x1 << 4) 74 #define CR_PCM (0x2 << 4) 75 #define CR_I2S (0x3 << 4) 76 #define CR_TDM (0x4 << 4) 77 #define CR_TDM_D (0x5 << 4) 78 79 /* OUT_DMAC */ 80 /* IN_DMAC */ 81 #define VDMD_MASK (0x3 << 4) 82 #define VDMD_FRONT (0x0 << 4) /* Package in front */ 83 #define VDMD_BACK (0x1 << 4) /* Package in back */ 84 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ 85 86 #define DMA_ON (0x1 << 0) 87 88 /* DOFF_CTL */ 89 /* DIFF_CTL */ 90 #define IRQ_HALF 0x00100000 91 #define FIFO_CLR 0x00000001 92 93 /* DOFF_ST */ 94 #define ERR_OVER 0x00000010 95 #define ERR_UNDER 0x00000001 96 #define ST_ERR (ERR_OVER | ERR_UNDER) 97 98 /* CKG1 */ 99 #define ACKMD_MASK 0x00007000 100 #define BPFMD_MASK 0x00000700 101 #define DIMD (1 << 4) 102 #define DOMD (1 << 0) 103 104 /* A/B MST_CTLR */ 105 #define BP (1 << 4) /* Fix the signal of Biphase output */ 106 #define SE (1 << 0) /* Fix the master clock */ 107 108 /* CLK_RST */ 109 #define CRB (1 << 4) 110 #define CRA (1 << 0) 111 112 /* IO SHIFT / MACRO */ 113 #define BI_SHIFT 12 114 #define BO_SHIFT 8 115 #define AI_SHIFT 4 116 #define AO_SHIFT 0 117 #define AB_IO(param, shift) (param << shift) 118 119 /* SOFT_RST */ 120 #define PBSR (1 << 12) /* Port B Software Reset */ 121 #define PASR (1 << 8) /* Port A Software Reset */ 122 #define IR (1 << 4) /* Interrupt Reset */ 123 #define FSISR (1 << 0) /* Software Reset */ 124 125 /* OUT_SEL (FSI2) */ 126 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ 127 /* 1: Biphase and serial */ 128 129 /* FIFO_SZ */ 130 #define FIFO_SZ_MASK 0x7 131 132 #define FSI_RATES SNDRV_PCM_RATE_8000_96000 133 134 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 135 136 /* 137 * bus options 138 * 139 * 0x000000BA 140 * 141 * A : sample widtht 16bit setting 142 * B : sample widtht 24bit setting 143 */ 144 145 #define SHIFT_16DATA 0 146 #define SHIFT_24DATA 4 147 148 #define PACKAGE_24BITBUS_BACK 0 149 #define PACKAGE_24BITBUS_FRONT 1 150 #define PACKAGE_16BITBUS_STREAM 2 151 152 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) 153 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) 154 155 /* 156 * FSI driver use below type name for variable 157 * 158 * xxx_num : number of data 159 * xxx_pos : position of data 160 * xxx_capa : capacity of data 161 */ 162 163 /* 164 * period/frame/sample image 165 * 166 * ex) PCM (2ch) 167 * 168 * period pos period pos 169 * [n] [n + 1] 170 * |<-------------------- period--------------------->| 171 * ==|============================================ ... =|== 172 * | | 173 * ||<----- frame ----->|<------ frame ----->| ... | 174 * |+--------------------+--------------------+- ... | 175 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | 176 * |+--------------------+--------------------+- ... | 177 * ==|============================================ ... =|== 178 */ 179 180 /* 181 * FSI FIFO image 182 * 183 * | | 184 * | | 185 * | [ sample ] | 186 * | [ sample ] | 187 * | [ sample ] | 188 * | [ sample ] | 189 * --> go to codecs 190 */ 191 192 /* 193 * FSI clock 194 * 195 * FSIxCLK [CPG] (ick) -------> | 196 * |-> FSI_DIV (div)-> FSI2 197 * FSIxCK [external] (xck) ---> | 198 */ 199 200 /* 201 * struct 202 */ 203 204 struct fsi_stream_handler; 205 struct fsi_stream { 206 207 /* 208 * these are initialized by fsi_stream_init() 209 */ 210 struct snd_pcm_substream *substream; 211 int fifo_sample_capa; /* sample capacity of FSI FIFO */ 212 int buff_sample_capa; /* sample capacity of ALSA buffer */ 213 int buff_sample_pos; /* sample position of ALSA buffer */ 214 int period_samples; /* sample number / 1 period */ 215 int period_pos; /* current period position */ 216 int sample_width; /* sample width */ 217 int uerr_num; 218 int oerr_num; 219 220 /* 221 * bus options 222 */ 223 u32 bus_option; 224 225 /* 226 * thse are initialized by fsi_handler_init() 227 */ 228 struct fsi_stream_handler *handler; 229 struct fsi_priv *priv; 230 231 /* 232 * these are for DMAEngine 233 */ 234 struct dma_chan *chan; 235 struct work_struct work; 236 dma_addr_t dma; 237 int dma_id; 238 int loop_cnt; 239 int additional_pos; 240 }; 241 242 struct fsi_clk { 243 /* see [FSI clock] */ 244 struct clk *own; 245 struct clk *xck; 246 struct clk *ick; 247 struct clk *div; 248 int (*set_rate)(struct device *dev, 249 struct fsi_priv *fsi); 250 251 unsigned long rate; 252 unsigned int count; 253 }; 254 255 struct fsi_priv { 256 void __iomem *base; 257 struct fsi_master *master; 258 259 struct fsi_stream playback; 260 struct fsi_stream capture; 261 262 struct fsi_clk clock; 263 264 u32 fmt; 265 266 int chan_num:16; 267 int clk_master:1; 268 int clk_cpg:1; 269 int spdif:1; 270 int enable_stream:1; 271 int bit_clk_inv:1; 272 int lr_clk_inv:1; 273 }; 274 275 struct fsi_stream_handler { 276 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); 277 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); 278 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); 279 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); 280 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); 281 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, 282 int enable); 283 }; 284 #define fsi_stream_handler_call(io, func, args...) \ 285 (!(io) ? -ENODEV : \ 286 !((io)->handler->func) ? 0 : \ 287 (io)->handler->func(args)) 288 289 struct fsi_core { 290 int ver; 291 292 u32 int_st; 293 u32 iemsk; 294 u32 imsk; 295 u32 a_mclk; 296 u32 b_mclk; 297 }; 298 299 struct fsi_master { 300 void __iomem *base; 301 struct fsi_priv fsia; 302 struct fsi_priv fsib; 303 const struct fsi_core *core; 304 spinlock_t lock; 305 }; 306 307 static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io); 308 309 /* 310 * basic read write function 311 */ 312 313 static void __fsi_reg_write(u32 __iomem *reg, u32 data) 314 { 315 /* valid data area is 24bit */ 316 data &= 0x00ffffff; 317 318 __raw_writel(data, reg); 319 } 320 321 static u32 __fsi_reg_read(u32 __iomem *reg) 322 { 323 return __raw_readl(reg); 324 } 325 326 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) 327 { 328 u32 val = __fsi_reg_read(reg); 329 330 val &= ~mask; 331 val |= data & mask; 332 333 __fsi_reg_write(reg, val); 334 } 335 336 #define fsi_reg_write(p, r, d)\ 337 __fsi_reg_write((p->base + REG_##r), d) 338 339 #define fsi_reg_read(p, r)\ 340 __fsi_reg_read((p->base + REG_##r)) 341 342 #define fsi_reg_mask_set(p, r, m, d)\ 343 __fsi_reg_mask_set((p->base + REG_##r), m, d) 344 345 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) 346 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) 347 static u32 _fsi_master_read(struct fsi_master *master, u32 reg) 348 { 349 u32 ret; 350 unsigned long flags; 351 352 spin_lock_irqsave(&master->lock, flags); 353 ret = __fsi_reg_read(master->base + reg); 354 spin_unlock_irqrestore(&master->lock, flags); 355 356 return ret; 357 } 358 359 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) 360 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) 361 static void _fsi_master_mask_set(struct fsi_master *master, 362 u32 reg, u32 mask, u32 data) 363 { 364 unsigned long flags; 365 366 spin_lock_irqsave(&master->lock, flags); 367 __fsi_reg_mask_set(master->base + reg, mask, data); 368 spin_unlock_irqrestore(&master->lock, flags); 369 } 370 371 /* 372 * basic function 373 */ 374 static int fsi_version(struct fsi_master *master) 375 { 376 return master->core->ver; 377 } 378 379 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) 380 { 381 return fsi->master; 382 } 383 384 static int fsi_is_clk_master(struct fsi_priv *fsi) 385 { 386 return fsi->clk_master; 387 } 388 389 static int fsi_is_port_a(struct fsi_priv *fsi) 390 { 391 return fsi->master->base == fsi->base; 392 } 393 394 static int fsi_is_spdif(struct fsi_priv *fsi) 395 { 396 return fsi->spdif; 397 } 398 399 static int fsi_is_enable_stream(struct fsi_priv *fsi) 400 { 401 return fsi->enable_stream; 402 } 403 404 static int fsi_is_play(struct snd_pcm_substream *substream) 405 { 406 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 407 } 408 409 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) 410 { 411 struct snd_soc_pcm_runtime *rtd = substream->private_data; 412 413 return rtd->cpu_dai; 414 } 415 416 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) 417 { 418 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); 419 420 if (dai->id == 0) 421 return &master->fsia; 422 else 423 return &master->fsib; 424 } 425 426 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) 427 { 428 return fsi_get_priv_frm_dai(fsi_get_dai(substream)); 429 } 430 431 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) 432 { 433 int is_play = fsi_stream_is_play(fsi, io); 434 int is_porta = fsi_is_port_a(fsi); 435 u32 shift; 436 437 if (is_porta) 438 shift = is_play ? AO_SHIFT : AI_SHIFT; 439 else 440 shift = is_play ? BO_SHIFT : BI_SHIFT; 441 442 return shift; 443 } 444 445 static int fsi_frame2sample(struct fsi_priv *fsi, int frames) 446 { 447 return frames * fsi->chan_num; 448 } 449 450 static int fsi_sample2frame(struct fsi_priv *fsi, int samples) 451 { 452 return samples / fsi->chan_num; 453 } 454 455 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, 456 struct fsi_stream *io) 457 { 458 int is_play = fsi_stream_is_play(fsi, io); 459 u32 status; 460 int frames; 461 462 status = is_play ? 463 fsi_reg_read(fsi, DOFF_ST) : 464 fsi_reg_read(fsi, DIFF_ST); 465 466 frames = 0x1ff & (status >> 8); 467 468 return fsi_frame2sample(fsi, frames); 469 } 470 471 static void fsi_count_fifo_err(struct fsi_priv *fsi) 472 { 473 u32 ostatus = fsi_reg_read(fsi, DOFF_ST); 474 u32 istatus = fsi_reg_read(fsi, DIFF_ST); 475 476 if (ostatus & ERR_OVER) 477 fsi->playback.oerr_num++; 478 479 if (ostatus & ERR_UNDER) 480 fsi->playback.uerr_num++; 481 482 if (istatus & ERR_OVER) 483 fsi->capture.oerr_num++; 484 485 if (istatus & ERR_UNDER) 486 fsi->capture.uerr_num++; 487 488 fsi_reg_write(fsi, DOFF_ST, 0); 489 fsi_reg_write(fsi, DIFF_ST, 0); 490 } 491 492 /* 493 * fsi_stream_xx() function 494 */ 495 static inline int fsi_stream_is_play(struct fsi_priv *fsi, 496 struct fsi_stream *io) 497 { 498 return &fsi->playback == io; 499 } 500 501 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, 502 struct snd_pcm_substream *substream) 503 { 504 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; 505 } 506 507 static int fsi_stream_is_working(struct fsi_priv *fsi, 508 struct fsi_stream *io) 509 { 510 struct fsi_master *master = fsi_get_master(fsi); 511 unsigned long flags; 512 int ret; 513 514 spin_lock_irqsave(&master->lock, flags); 515 ret = !!(io->substream && io->substream->runtime); 516 spin_unlock_irqrestore(&master->lock, flags); 517 518 return ret; 519 } 520 521 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) 522 { 523 return io->priv; 524 } 525 526 static void fsi_stream_init(struct fsi_priv *fsi, 527 struct fsi_stream *io, 528 struct snd_pcm_substream *substream) 529 { 530 struct snd_pcm_runtime *runtime = substream->runtime; 531 struct fsi_master *master = fsi_get_master(fsi); 532 unsigned long flags; 533 534 spin_lock_irqsave(&master->lock, flags); 535 io->substream = substream; 536 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); 537 io->buff_sample_pos = 0; 538 io->period_samples = fsi_frame2sample(fsi, runtime->period_size); 539 io->period_pos = 0; 540 io->sample_width = samples_to_bytes(runtime, 1); 541 io->bus_option = 0; 542 io->oerr_num = -1; /* ignore 1st err */ 543 io->uerr_num = -1; /* ignore 1st err */ 544 fsi_stream_handler_call(io, init, fsi, io); 545 spin_unlock_irqrestore(&master->lock, flags); 546 } 547 548 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) 549 { 550 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 551 struct fsi_master *master = fsi_get_master(fsi); 552 unsigned long flags; 553 554 spin_lock_irqsave(&master->lock, flags); 555 556 if (io->oerr_num > 0) 557 dev_err(dai->dev, "over_run = %d\n", io->oerr_num); 558 559 if (io->uerr_num > 0) 560 dev_err(dai->dev, "under_run = %d\n", io->uerr_num); 561 562 fsi_stream_handler_call(io, quit, fsi, io); 563 io->substream = NULL; 564 io->buff_sample_capa = 0; 565 io->buff_sample_pos = 0; 566 io->period_samples = 0; 567 io->period_pos = 0; 568 io->sample_width = 0; 569 io->bus_option = 0; 570 io->oerr_num = 0; 571 io->uerr_num = 0; 572 spin_unlock_irqrestore(&master->lock, flags); 573 } 574 575 static int fsi_stream_transfer(struct fsi_stream *io) 576 { 577 struct fsi_priv *fsi = fsi_stream_to_priv(io); 578 if (!fsi) 579 return -EIO; 580 581 return fsi_stream_handler_call(io, transfer, fsi, io); 582 } 583 584 #define fsi_stream_start(fsi, io)\ 585 fsi_stream_handler_call(io, start_stop, fsi, io, 1) 586 587 #define fsi_stream_stop(fsi, io)\ 588 fsi_stream_handler_call(io, start_stop, fsi, io, 0) 589 590 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) 591 { 592 struct fsi_stream *io; 593 int ret1, ret2; 594 595 io = &fsi->playback; 596 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); 597 598 io = &fsi->capture; 599 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); 600 601 if (ret1 < 0) 602 return ret1; 603 if (ret2 < 0) 604 return ret2; 605 606 return 0; 607 } 608 609 static int fsi_stream_remove(struct fsi_priv *fsi) 610 { 611 struct fsi_stream *io; 612 int ret1, ret2; 613 614 io = &fsi->playback; 615 ret1 = fsi_stream_handler_call(io, remove, fsi, io); 616 617 io = &fsi->capture; 618 ret2 = fsi_stream_handler_call(io, remove, fsi, io); 619 620 if (ret1 < 0) 621 return ret1; 622 if (ret2 < 0) 623 return ret2; 624 625 return 0; 626 } 627 628 /* 629 * format/bus/dma setting 630 */ 631 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, 632 u32 bus, struct device *dev) 633 { 634 struct fsi_master *master = fsi_get_master(fsi); 635 int is_play = fsi_stream_is_play(fsi, io); 636 u32 fmt = fsi->fmt; 637 638 if (fsi_version(master) >= 2) { 639 u32 dma = 0; 640 641 /* 642 * FSI2 needs DMA/Bus setting 643 */ 644 switch (bus) { 645 case PACKAGE_24BITBUS_FRONT: 646 fmt |= CR_BWS_24; 647 dma |= VDMD_FRONT; 648 dev_dbg(dev, "24bit bus / package in front\n"); 649 break; 650 case PACKAGE_16BITBUS_STREAM: 651 fmt |= CR_BWS_16; 652 dma |= VDMD_STREAM; 653 dev_dbg(dev, "16bit bus / stream mode\n"); 654 break; 655 case PACKAGE_24BITBUS_BACK: 656 default: 657 fmt |= CR_BWS_24; 658 dma |= VDMD_BACK; 659 dev_dbg(dev, "24bit bus / package in back\n"); 660 break; 661 } 662 663 if (is_play) 664 fsi_reg_write(fsi, OUT_DMAC, dma); 665 else 666 fsi_reg_write(fsi, IN_DMAC, dma); 667 } 668 669 if (is_play) 670 fsi_reg_write(fsi, DO_FMT, fmt); 671 else 672 fsi_reg_write(fsi, DI_FMT, fmt); 673 } 674 675 /* 676 * irq function 677 */ 678 679 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) 680 { 681 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 682 struct fsi_master *master = fsi_get_master(fsi); 683 684 fsi_core_mask_set(master, imsk, data, data); 685 fsi_core_mask_set(master, iemsk, data, data); 686 } 687 688 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) 689 { 690 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 691 struct fsi_master *master = fsi_get_master(fsi); 692 693 fsi_core_mask_set(master, imsk, data, 0); 694 fsi_core_mask_set(master, iemsk, data, 0); 695 } 696 697 static u32 fsi_irq_get_status(struct fsi_master *master) 698 { 699 return fsi_core_read(master, int_st); 700 } 701 702 static void fsi_irq_clear_status(struct fsi_priv *fsi) 703 { 704 u32 data = 0; 705 struct fsi_master *master = fsi_get_master(fsi); 706 707 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); 708 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); 709 710 /* clear interrupt factor */ 711 fsi_core_mask_set(master, int_st, data, 0); 712 } 713 714 /* 715 * SPDIF master clock function 716 * 717 * These functions are used later FSI2 718 */ 719 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) 720 { 721 struct fsi_master *master = fsi_get_master(fsi); 722 u32 mask, val; 723 724 mask = BP | SE; 725 val = enable ? mask : 0; 726 727 fsi_is_port_a(fsi) ? 728 fsi_core_mask_set(master, a_mclk, mask, val) : 729 fsi_core_mask_set(master, b_mclk, mask, val); 730 } 731 732 /* 733 * clock function 734 */ 735 static int fsi_clk_init(struct device *dev, 736 struct fsi_priv *fsi, 737 int xck, 738 int ick, 739 int div, 740 int (*set_rate)(struct device *dev, 741 struct fsi_priv *fsi)) 742 { 743 struct fsi_clk *clock = &fsi->clock; 744 int is_porta = fsi_is_port_a(fsi); 745 746 clock->xck = NULL; 747 clock->ick = NULL; 748 clock->div = NULL; 749 clock->rate = 0; 750 clock->count = 0; 751 clock->set_rate = set_rate; 752 753 clock->own = devm_clk_get(dev, NULL); 754 if (IS_ERR(clock->own)) 755 return -EINVAL; 756 757 /* external clock */ 758 if (xck) { 759 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); 760 if (IS_ERR(clock->xck)) { 761 dev_err(dev, "can't get xck clock\n"); 762 return -EINVAL; 763 } 764 if (clock->xck == clock->own) { 765 dev_err(dev, "cpu doesn't support xck clock\n"); 766 return -EINVAL; 767 } 768 } 769 770 /* FSIACLK/FSIBCLK */ 771 if (ick) { 772 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); 773 if (IS_ERR(clock->ick)) { 774 dev_err(dev, "can't get ick clock\n"); 775 return -EINVAL; 776 } 777 if (clock->ick == clock->own) { 778 dev_err(dev, "cpu doesn't support ick clock\n"); 779 return -EINVAL; 780 } 781 } 782 783 /* FSI-DIV */ 784 if (div) { 785 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); 786 if (IS_ERR(clock->div)) { 787 dev_err(dev, "can't get div clock\n"); 788 return -EINVAL; 789 } 790 if (clock->div == clock->own) { 791 dev_err(dev, "cpu doens't support div clock\n"); 792 return -EINVAL; 793 } 794 } 795 796 return 0; 797 } 798 799 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) 800 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) 801 { 802 fsi->clock.rate = rate; 803 } 804 805 static int fsi_clk_is_valid(struct fsi_priv *fsi) 806 { 807 return fsi->clock.set_rate && 808 fsi->clock.rate; 809 } 810 811 static int fsi_clk_enable(struct device *dev, 812 struct fsi_priv *fsi) 813 { 814 struct fsi_clk *clock = &fsi->clock; 815 int ret = -EINVAL; 816 817 if (!fsi_clk_is_valid(fsi)) 818 return ret; 819 820 if (0 == clock->count) { 821 ret = clock->set_rate(dev, fsi); 822 if (ret < 0) { 823 fsi_clk_invalid(fsi); 824 return ret; 825 } 826 827 if (clock->xck) 828 clk_enable(clock->xck); 829 if (clock->ick) 830 clk_enable(clock->ick); 831 if (clock->div) 832 clk_enable(clock->div); 833 834 clock->count++; 835 } 836 837 return ret; 838 } 839 840 static int fsi_clk_disable(struct device *dev, 841 struct fsi_priv *fsi) 842 { 843 struct fsi_clk *clock = &fsi->clock; 844 845 if (!fsi_clk_is_valid(fsi)) 846 return -EINVAL; 847 848 if (1 == clock->count--) { 849 if (clock->xck) 850 clk_disable(clock->xck); 851 if (clock->ick) 852 clk_disable(clock->ick); 853 if (clock->div) 854 clk_disable(clock->div); 855 } 856 857 return 0; 858 } 859 860 static int fsi_clk_set_ackbpf(struct device *dev, 861 struct fsi_priv *fsi, 862 int ackmd, int bpfmd) 863 { 864 u32 data = 0; 865 866 /* check ackmd/bpfmd relationship */ 867 if (bpfmd > ackmd) { 868 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); 869 return -EINVAL; 870 } 871 872 /* ACKMD */ 873 switch (ackmd) { 874 case 512: 875 data |= (0x0 << 12); 876 break; 877 case 256: 878 data |= (0x1 << 12); 879 break; 880 case 128: 881 data |= (0x2 << 12); 882 break; 883 case 64: 884 data |= (0x3 << 12); 885 break; 886 case 32: 887 data |= (0x4 << 12); 888 break; 889 default: 890 dev_err(dev, "unsupported ackmd (%d)\n", ackmd); 891 return -EINVAL; 892 } 893 894 /* BPFMD */ 895 switch (bpfmd) { 896 case 32: 897 data |= (0x0 << 8); 898 break; 899 case 64: 900 data |= (0x1 << 8); 901 break; 902 case 128: 903 data |= (0x2 << 8); 904 break; 905 case 256: 906 data |= (0x3 << 8); 907 break; 908 case 512: 909 data |= (0x4 << 8); 910 break; 911 case 16: 912 data |= (0x7 << 8); 913 break; 914 default: 915 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); 916 return -EINVAL; 917 } 918 919 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); 920 921 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 922 udelay(10); 923 924 return 0; 925 } 926 927 static int fsi_clk_set_rate_external(struct device *dev, 928 struct fsi_priv *fsi) 929 { 930 struct clk *xck = fsi->clock.xck; 931 struct clk *ick = fsi->clock.ick; 932 unsigned long rate = fsi->clock.rate; 933 unsigned long xrate; 934 int ackmd, bpfmd; 935 int ret = 0; 936 937 /* check clock rate */ 938 xrate = clk_get_rate(xck); 939 if (xrate % rate) { 940 dev_err(dev, "unsupported clock rate\n"); 941 return -EINVAL; 942 } 943 944 clk_set_parent(ick, xck); 945 clk_set_rate(ick, xrate); 946 947 bpfmd = fsi->chan_num * 32; 948 ackmd = xrate / rate; 949 950 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); 951 952 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 953 if (ret < 0) 954 dev_err(dev, "%s failed", __func__); 955 956 return ret; 957 } 958 959 static int fsi_clk_set_rate_cpg(struct device *dev, 960 struct fsi_priv *fsi) 961 { 962 struct clk *ick = fsi->clock.ick; 963 struct clk *div = fsi->clock.div; 964 unsigned long rate = fsi->clock.rate; 965 unsigned long target = 0; /* 12288000 or 11289600 */ 966 unsigned long actual, cout; 967 unsigned long diff, min; 968 unsigned long best_cout, best_act; 969 int adj; 970 int ackmd, bpfmd; 971 int ret = -EINVAL; 972 973 if (!(12288000 % rate)) 974 target = 12288000; 975 if (!(11289600 % rate)) 976 target = 11289600; 977 if (!target) { 978 dev_err(dev, "unsupported rate\n"); 979 return ret; 980 } 981 982 bpfmd = fsi->chan_num * 32; 983 ackmd = target / rate; 984 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 985 if (ret < 0) { 986 dev_err(dev, "%s failed", __func__); 987 return ret; 988 } 989 990 /* 991 * The clock flow is 992 * 993 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] 994 * 995 * But, it needs to find best match of CPG and FSI_DIV 996 * combination, since it is difficult to generate correct 997 * frequency of audio clock from ick clock only. 998 * Because ick is created from its parent clock. 999 * 1000 * target = rate x [512/256/128/64]fs 1001 * cout = round(target x adjustment) 1002 * actual = cout / adjustment (by FSI-DIV) ~= target 1003 * audio = actual 1004 */ 1005 min = ~0; 1006 best_cout = 0; 1007 best_act = 0; 1008 for (adj = 1; adj < 0xffff; adj++) { 1009 1010 cout = target * adj; 1011 if (cout > 100000000) /* max clock = 100MHz */ 1012 break; 1013 1014 /* cout/actual audio clock */ 1015 cout = clk_round_rate(ick, cout); 1016 actual = cout / adj; 1017 1018 /* find best frequency */ 1019 diff = abs(actual - target); 1020 if (diff < min) { 1021 min = diff; 1022 best_cout = cout; 1023 best_act = actual; 1024 } 1025 } 1026 1027 ret = clk_set_rate(ick, best_cout); 1028 if (ret < 0) { 1029 dev_err(dev, "ick clock failed\n"); 1030 return -EIO; 1031 } 1032 1033 ret = clk_set_rate(div, clk_round_rate(div, best_act)); 1034 if (ret < 0) { 1035 dev_err(dev, "div clock failed\n"); 1036 return -EIO; 1037 } 1038 1039 dev_dbg(dev, "ick/div = %ld/%ld\n", 1040 clk_get_rate(ick), clk_get_rate(div)); 1041 1042 return ret; 1043 } 1044 1045 /* 1046 * pio data transfer handler 1047 */ 1048 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) 1049 { 1050 int i; 1051 1052 if (fsi_is_enable_stream(fsi)) { 1053 /* 1054 * stream mode 1055 * see 1056 * fsi_pio_push_init() 1057 */ 1058 u32 *buf = (u32 *)_buf; 1059 1060 for (i = 0; i < samples / 2; i++) 1061 fsi_reg_write(fsi, DODT, buf[i]); 1062 } else { 1063 /* normal mode */ 1064 u16 *buf = (u16 *)_buf; 1065 1066 for (i = 0; i < samples; i++) 1067 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); 1068 } 1069 } 1070 1071 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) 1072 { 1073 u16 *buf = (u16 *)_buf; 1074 int i; 1075 1076 for (i = 0; i < samples; i++) 1077 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); 1078 } 1079 1080 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) 1081 { 1082 u32 *buf = (u32 *)_buf; 1083 int i; 1084 1085 for (i = 0; i < samples; i++) 1086 fsi_reg_write(fsi, DODT, *(buf + i)); 1087 } 1088 1089 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) 1090 { 1091 u32 *buf = (u32 *)_buf; 1092 int i; 1093 1094 for (i = 0; i < samples; i++) 1095 *(buf + i) = fsi_reg_read(fsi, DIDT); 1096 } 1097 1098 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) 1099 { 1100 struct snd_pcm_runtime *runtime = io->substream->runtime; 1101 1102 return runtime->dma_area + 1103 samples_to_bytes(runtime, io->buff_sample_pos); 1104 } 1105 1106 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, 1107 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), 1108 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), 1109 int samples) 1110 { 1111 struct snd_pcm_runtime *runtime; 1112 struct snd_pcm_substream *substream; 1113 u8 *buf; 1114 int over_period; 1115 1116 if (!fsi_stream_is_working(fsi, io)) 1117 return -EINVAL; 1118 1119 over_period = 0; 1120 substream = io->substream; 1121 runtime = substream->runtime; 1122 1123 /* FSI FIFO has limit. 1124 * So, this driver can not send periods data at a time 1125 */ 1126 if (io->buff_sample_pos >= 1127 io->period_samples * (io->period_pos + 1)) { 1128 1129 over_period = 1; 1130 io->period_pos = (io->period_pos + 1) % runtime->periods; 1131 1132 if (0 == io->period_pos) 1133 io->buff_sample_pos = 0; 1134 } 1135 1136 buf = fsi_pio_get_area(fsi, io); 1137 1138 switch (io->sample_width) { 1139 case 2: 1140 run16(fsi, buf, samples); 1141 break; 1142 case 4: 1143 run32(fsi, buf, samples); 1144 break; 1145 default: 1146 return -EINVAL; 1147 } 1148 1149 /* update buff_sample_pos */ 1150 io->buff_sample_pos += samples; 1151 1152 if (over_period) 1153 snd_pcm_period_elapsed(substream); 1154 1155 return 0; 1156 } 1157 1158 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) 1159 { 1160 int sample_residues; /* samples in FSI fifo */ 1161 int sample_space; /* ALSA free samples space */ 1162 int samples; 1163 1164 sample_residues = fsi_get_current_fifo_samples(fsi, io); 1165 sample_space = io->buff_sample_capa - io->buff_sample_pos; 1166 1167 samples = min(sample_residues, sample_space); 1168 1169 return fsi_pio_transfer(fsi, io, 1170 fsi_pio_pop16, 1171 fsi_pio_pop32, 1172 samples); 1173 } 1174 1175 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) 1176 { 1177 int sample_residues; /* ALSA residue samples */ 1178 int sample_space; /* FSI fifo free samples space */ 1179 int samples; 1180 1181 sample_residues = io->buff_sample_capa - io->buff_sample_pos; 1182 sample_space = io->fifo_sample_capa - 1183 fsi_get_current_fifo_samples(fsi, io); 1184 1185 samples = min(sample_residues, sample_space); 1186 1187 return fsi_pio_transfer(fsi, io, 1188 fsi_pio_push16, 1189 fsi_pio_push32, 1190 samples); 1191 } 1192 1193 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1194 int enable) 1195 { 1196 struct fsi_master *master = fsi_get_master(fsi); 1197 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1198 1199 if (enable) 1200 fsi_irq_enable(fsi, io); 1201 else 1202 fsi_irq_disable(fsi, io); 1203 1204 if (fsi_is_clk_master(fsi)) 1205 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1206 1207 return 0; 1208 } 1209 1210 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) 1211 { 1212 /* 1213 * we can use 16bit stream mode 1214 * when "playback" and "16bit data" 1215 * and platform allows "stream mode" 1216 * see 1217 * fsi_pio_push16() 1218 */ 1219 if (fsi_is_enable_stream(fsi)) 1220 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1221 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1222 else 1223 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1224 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1225 return 0; 1226 } 1227 1228 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) 1229 { 1230 /* 1231 * always 24bit bus, package back when "capture" 1232 */ 1233 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1234 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1235 return 0; 1236 } 1237 1238 static struct fsi_stream_handler fsi_pio_push_handler = { 1239 .init = fsi_pio_push_init, 1240 .transfer = fsi_pio_push, 1241 .start_stop = fsi_pio_start_stop, 1242 }; 1243 1244 static struct fsi_stream_handler fsi_pio_pop_handler = { 1245 .init = fsi_pio_pop_init, 1246 .transfer = fsi_pio_pop, 1247 .start_stop = fsi_pio_start_stop, 1248 }; 1249 1250 static irqreturn_t fsi_interrupt(int irq, void *data) 1251 { 1252 struct fsi_master *master = data; 1253 u32 int_st = fsi_irq_get_status(master); 1254 1255 /* clear irq status */ 1256 fsi_master_mask_set(master, SOFT_RST, IR, 0); 1257 fsi_master_mask_set(master, SOFT_RST, IR, IR); 1258 1259 if (int_st & AB_IO(1, AO_SHIFT)) 1260 fsi_stream_transfer(&master->fsia.playback); 1261 if (int_st & AB_IO(1, BO_SHIFT)) 1262 fsi_stream_transfer(&master->fsib.playback); 1263 if (int_st & AB_IO(1, AI_SHIFT)) 1264 fsi_stream_transfer(&master->fsia.capture); 1265 if (int_st & AB_IO(1, BI_SHIFT)) 1266 fsi_stream_transfer(&master->fsib.capture); 1267 1268 fsi_count_fifo_err(&master->fsia); 1269 fsi_count_fifo_err(&master->fsib); 1270 1271 fsi_irq_clear_status(&master->fsia); 1272 fsi_irq_clear_status(&master->fsib); 1273 1274 return IRQ_HANDLED; 1275 } 1276 1277 /* 1278 * dma data transfer handler 1279 */ 1280 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) 1281 { 1282 struct snd_pcm_runtime *runtime = io->substream->runtime; 1283 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1284 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? 1285 DMA_TO_DEVICE : DMA_FROM_DEVICE; 1286 1287 /* 1288 * 24bit data : 24bit bus / package in back 1289 * 16bit data : 16bit bus / stream mode 1290 */ 1291 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1292 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1293 1294 io->loop_cnt = 2; /* push 1st, 2nd period first, then 3rd, 4th... */ 1295 io->additional_pos = 0; 1296 io->dma = dma_map_single(dai->dev, runtime->dma_area, 1297 snd_pcm_lib_buffer_bytes(io->substream), dir); 1298 return 0; 1299 } 1300 1301 static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io) 1302 { 1303 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1304 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? 1305 DMA_TO_DEVICE : DMA_FROM_DEVICE; 1306 1307 dma_unmap_single(dai->dev, io->dma, 1308 snd_pcm_lib_buffer_bytes(io->substream), dir); 1309 return 0; 1310 } 1311 1312 static dma_addr_t fsi_dma_get_area(struct fsi_stream *io, int additional) 1313 { 1314 struct snd_pcm_runtime *runtime = io->substream->runtime; 1315 int period = io->period_pos + additional; 1316 1317 if (period >= runtime->periods) 1318 period = 0; 1319 1320 return io->dma + samples_to_bytes(runtime, period * io->period_samples); 1321 } 1322 1323 static void fsi_dma_complete(void *data) 1324 { 1325 struct fsi_stream *io = (struct fsi_stream *)data; 1326 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1327 struct snd_pcm_runtime *runtime = io->substream->runtime; 1328 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1329 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? 1330 DMA_TO_DEVICE : DMA_FROM_DEVICE; 1331 1332 dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io, 0), 1333 samples_to_bytes(runtime, io->period_samples), dir); 1334 1335 io->buff_sample_pos += io->period_samples; 1336 io->period_pos++; 1337 1338 if (io->period_pos >= runtime->periods) { 1339 io->period_pos = 0; 1340 io->buff_sample_pos = 0; 1341 } 1342 1343 fsi_count_fifo_err(fsi); 1344 fsi_stream_transfer(io); 1345 1346 snd_pcm_period_elapsed(io->substream); 1347 } 1348 1349 static void fsi_dma_do_work(struct work_struct *work) 1350 { 1351 struct fsi_stream *io = container_of(work, struct fsi_stream, work); 1352 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1353 struct snd_soc_dai *dai; 1354 struct dma_async_tx_descriptor *desc; 1355 struct snd_pcm_runtime *runtime; 1356 enum dma_data_direction dir; 1357 int is_play = fsi_stream_is_play(fsi, io); 1358 int len, i; 1359 dma_addr_t buf; 1360 1361 if (!fsi_stream_is_working(fsi, io)) 1362 return; 1363 1364 dai = fsi_get_dai(io->substream); 1365 runtime = io->substream->runtime; 1366 dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 1367 len = samples_to_bytes(runtime, io->period_samples); 1368 1369 for (i = 0; i < io->loop_cnt; i++) { 1370 buf = fsi_dma_get_area(io, io->additional_pos); 1371 1372 dma_sync_single_for_device(dai->dev, buf, len, dir); 1373 1374 desc = dmaengine_prep_slave_single(io->chan, buf, len, dir, 1375 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1376 if (!desc) { 1377 dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n"); 1378 return; 1379 } 1380 1381 desc->callback = fsi_dma_complete; 1382 desc->callback_param = io; 1383 1384 if (dmaengine_submit(desc) < 0) { 1385 dev_err(dai->dev, "tx_submit() fail\n"); 1386 return; 1387 } 1388 1389 dma_async_issue_pending(io->chan); 1390 1391 io->additional_pos = 1; 1392 } 1393 1394 io->loop_cnt = 1; 1395 1396 /* 1397 * FIXME 1398 * 1399 * In DMAEngine case, codec and FSI cannot be started simultaneously 1400 * since FSI is using the scheduler work queue. 1401 * Therefore, in capture case, probably FSI FIFO will have got 1402 * overflow error in this point. 1403 * in that case, DMA cannot start transfer until error was cleared. 1404 */ 1405 if (!is_play) { 1406 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { 1407 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1408 fsi_reg_write(fsi, DIFF_ST, 0); 1409 } 1410 } 1411 } 1412 1413 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) 1414 { 1415 schedule_work(&io->work); 1416 1417 return 0; 1418 } 1419 1420 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1421 int start) 1422 { 1423 struct fsi_master *master = fsi_get_master(fsi); 1424 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1425 u32 enable = start ? DMA_ON : 0; 1426 1427 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); 1428 1429 dmaengine_terminate_all(io->chan); 1430 1431 if (fsi_is_clk_master(fsi)) 1432 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1433 1434 return 0; 1435 } 1436 1437 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) 1438 { 1439 dma_cap_mask_t mask; 1440 int is_play = fsi_stream_is_play(fsi, io); 1441 1442 dma_cap_zero(mask); 1443 dma_cap_set(DMA_SLAVE, mask); 1444 1445 io->chan = dma_request_slave_channel_compat(mask, 1446 shdma_chan_filter, (void *)io->dma_id, 1447 dev, is_play ? "tx" : "rx"); 1448 if (io->chan) { 1449 struct dma_slave_config cfg; 1450 int ret; 1451 1452 cfg.slave_id = io->dma_id; 1453 cfg.dst_addr = 0; /* use default addr */ 1454 cfg.src_addr = 0; /* use default addr */ 1455 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 1456 1457 ret = dmaengine_slave_config(io->chan, &cfg); 1458 if (ret < 0) { 1459 dma_release_channel(io->chan); 1460 io->chan = NULL; 1461 } 1462 } 1463 1464 if (!io->chan) { 1465 1466 /* switch to PIO handler */ 1467 if (is_play) 1468 fsi->playback.handler = &fsi_pio_push_handler; 1469 else 1470 fsi->capture.handler = &fsi_pio_pop_handler; 1471 1472 dev_info(dev, "switch handler (dma => pio)\n"); 1473 1474 /* probe again */ 1475 return fsi_stream_probe(fsi, dev); 1476 } 1477 1478 INIT_WORK(&io->work, fsi_dma_do_work); 1479 1480 return 0; 1481 } 1482 1483 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) 1484 { 1485 cancel_work_sync(&io->work); 1486 1487 fsi_stream_stop(fsi, io); 1488 1489 if (io->chan) 1490 dma_release_channel(io->chan); 1491 1492 io->chan = NULL; 1493 return 0; 1494 } 1495 1496 static struct fsi_stream_handler fsi_dma_push_handler = { 1497 .init = fsi_dma_init, 1498 .quit = fsi_dma_quit, 1499 .probe = fsi_dma_probe, 1500 .transfer = fsi_dma_transfer, 1501 .remove = fsi_dma_remove, 1502 .start_stop = fsi_dma_push_start_stop, 1503 }; 1504 1505 /* 1506 * dai ops 1507 */ 1508 static void fsi_fifo_init(struct fsi_priv *fsi, 1509 struct fsi_stream *io, 1510 struct device *dev) 1511 { 1512 struct fsi_master *master = fsi_get_master(fsi); 1513 int is_play = fsi_stream_is_play(fsi, io); 1514 u32 shift, i; 1515 int frame_capa; 1516 1517 /* get on-chip RAM capacity */ 1518 shift = fsi_master_read(master, FIFO_SZ); 1519 shift >>= fsi_get_port_shift(fsi, io); 1520 shift &= FIFO_SZ_MASK; 1521 frame_capa = 256 << shift; 1522 dev_dbg(dev, "fifo = %d words\n", frame_capa); 1523 1524 /* 1525 * The maximum number of sample data varies depending 1526 * on the number of channels selected for the format. 1527 * 1528 * FIFOs are used in 4-channel units in 3-channel mode 1529 * and in 8-channel units in 5- to 7-channel mode 1530 * meaning that more FIFOs than the required size of DPRAM 1531 * are used. 1532 * 1533 * ex) if 256 words of DP-RAM is connected 1534 * 1 channel: 256 (256 x 1 = 256) 1535 * 2 channels: 128 (128 x 2 = 256) 1536 * 3 channels: 64 ( 64 x 3 = 192) 1537 * 4 channels: 64 ( 64 x 4 = 256) 1538 * 5 channels: 32 ( 32 x 5 = 160) 1539 * 6 channels: 32 ( 32 x 6 = 192) 1540 * 7 channels: 32 ( 32 x 7 = 224) 1541 * 8 channels: 32 ( 32 x 8 = 256) 1542 */ 1543 for (i = 1; i < fsi->chan_num; i <<= 1) 1544 frame_capa >>= 1; 1545 dev_dbg(dev, "%d channel %d store\n", 1546 fsi->chan_num, frame_capa); 1547 1548 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); 1549 1550 /* 1551 * set interrupt generation factor 1552 * clear FIFO 1553 */ 1554 if (is_play) { 1555 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); 1556 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); 1557 } else { 1558 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); 1559 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1560 } 1561 } 1562 1563 static int fsi_hw_startup(struct fsi_priv *fsi, 1564 struct fsi_stream *io, 1565 struct device *dev) 1566 { 1567 u32 data = 0; 1568 1569 /* clock setting */ 1570 if (fsi_is_clk_master(fsi)) 1571 data = DIMD | DOMD; 1572 1573 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); 1574 1575 /* clock inversion (CKG2) */ 1576 data = 0; 1577 if (fsi->bit_clk_inv) 1578 data |= (1 << 0); 1579 if (fsi->lr_clk_inv) 1580 data |= (1 << 4); 1581 if (fsi_is_clk_master(fsi)) 1582 data <<= 8; 1583 fsi_reg_write(fsi, CKG2, data); 1584 1585 /* spdif ? */ 1586 if (fsi_is_spdif(fsi)) { 1587 fsi_spdif_clk_ctrl(fsi, 1); 1588 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); 1589 } 1590 1591 /* 1592 * get bus settings 1593 */ 1594 data = 0; 1595 switch (io->sample_width) { 1596 case 2: 1597 data = BUSOP_GET(16, io->bus_option); 1598 break; 1599 case 4: 1600 data = BUSOP_GET(24, io->bus_option); 1601 break; 1602 } 1603 fsi_format_bus_setup(fsi, io, data, dev); 1604 1605 /* irq clear */ 1606 fsi_irq_disable(fsi, io); 1607 fsi_irq_clear_status(fsi); 1608 1609 /* fifo init */ 1610 fsi_fifo_init(fsi, io, dev); 1611 1612 /* start master clock */ 1613 if (fsi_is_clk_master(fsi)) 1614 return fsi_clk_enable(dev, fsi); 1615 1616 return 0; 1617 } 1618 1619 static int fsi_hw_shutdown(struct fsi_priv *fsi, 1620 struct device *dev) 1621 { 1622 /* stop master clock */ 1623 if (fsi_is_clk_master(fsi)) 1624 return fsi_clk_disable(dev, fsi); 1625 1626 return 0; 1627 } 1628 1629 static int fsi_dai_startup(struct snd_pcm_substream *substream, 1630 struct snd_soc_dai *dai) 1631 { 1632 struct fsi_priv *fsi = fsi_get_priv(substream); 1633 1634 fsi_clk_invalid(fsi); 1635 1636 return 0; 1637 } 1638 1639 static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 1640 struct snd_soc_dai *dai) 1641 { 1642 struct fsi_priv *fsi = fsi_get_priv(substream); 1643 1644 fsi_clk_invalid(fsi); 1645 } 1646 1647 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 1648 struct snd_soc_dai *dai) 1649 { 1650 struct fsi_priv *fsi = fsi_get_priv(substream); 1651 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1652 int ret = 0; 1653 1654 switch (cmd) { 1655 case SNDRV_PCM_TRIGGER_START: 1656 fsi_stream_init(fsi, io, substream); 1657 if (!ret) 1658 ret = fsi_hw_startup(fsi, io, dai->dev); 1659 if (!ret) 1660 ret = fsi_stream_transfer(io); 1661 if (!ret) 1662 fsi_stream_start(fsi, io); 1663 break; 1664 case SNDRV_PCM_TRIGGER_STOP: 1665 if (!ret) 1666 ret = fsi_hw_shutdown(fsi, dai->dev); 1667 fsi_stream_stop(fsi, io); 1668 fsi_stream_quit(fsi, io); 1669 break; 1670 } 1671 1672 return ret; 1673 } 1674 1675 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) 1676 { 1677 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1678 case SND_SOC_DAIFMT_I2S: 1679 fsi->fmt = CR_I2S; 1680 fsi->chan_num = 2; 1681 break; 1682 case SND_SOC_DAIFMT_LEFT_J: 1683 fsi->fmt = CR_PCM; 1684 fsi->chan_num = 2; 1685 break; 1686 default: 1687 return -EINVAL; 1688 } 1689 1690 return 0; 1691 } 1692 1693 static int fsi_set_fmt_spdif(struct fsi_priv *fsi) 1694 { 1695 struct fsi_master *master = fsi_get_master(fsi); 1696 1697 if (fsi_version(master) < 2) 1698 return -EINVAL; 1699 1700 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; 1701 fsi->chan_num = 2; 1702 1703 return 0; 1704 } 1705 1706 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1707 { 1708 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); 1709 int ret; 1710 1711 /* set master/slave audio interface */ 1712 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1713 case SND_SOC_DAIFMT_CBM_CFM: 1714 break; 1715 case SND_SOC_DAIFMT_CBS_CFS: 1716 fsi->clk_master = 1; /* codec is slave, cpu is master */ 1717 break; 1718 default: 1719 return -EINVAL; 1720 } 1721 1722 /* set clock inversion */ 1723 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1724 case SND_SOC_DAIFMT_NB_IF: 1725 fsi->bit_clk_inv = 0; 1726 fsi->lr_clk_inv = 1; 1727 break; 1728 case SND_SOC_DAIFMT_IB_NF: 1729 fsi->bit_clk_inv = 1; 1730 fsi->lr_clk_inv = 0; 1731 break; 1732 case SND_SOC_DAIFMT_IB_IF: 1733 fsi->bit_clk_inv = 1; 1734 fsi->lr_clk_inv = 1; 1735 break; 1736 case SND_SOC_DAIFMT_NB_NF: 1737 default: 1738 fsi->bit_clk_inv = 0; 1739 fsi->lr_clk_inv = 0; 1740 break; 1741 } 1742 1743 if (fsi_is_clk_master(fsi)) { 1744 if (fsi->clk_cpg) 1745 fsi_clk_init(dai->dev, fsi, 0, 1, 1, 1746 fsi_clk_set_rate_cpg); 1747 else 1748 fsi_clk_init(dai->dev, fsi, 1, 1, 0, 1749 fsi_clk_set_rate_external); 1750 } 1751 1752 /* set format */ 1753 if (fsi_is_spdif(fsi)) 1754 ret = fsi_set_fmt_spdif(fsi); 1755 else 1756 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1757 1758 return ret; 1759 } 1760 1761 static int fsi_dai_hw_params(struct snd_pcm_substream *substream, 1762 struct snd_pcm_hw_params *params, 1763 struct snd_soc_dai *dai) 1764 { 1765 struct fsi_priv *fsi = fsi_get_priv(substream); 1766 1767 if (fsi_is_clk_master(fsi)) 1768 fsi_clk_valid(fsi, params_rate(params)); 1769 1770 return 0; 1771 } 1772 1773 static const struct snd_soc_dai_ops fsi_dai_ops = { 1774 .startup = fsi_dai_startup, 1775 .shutdown = fsi_dai_shutdown, 1776 .trigger = fsi_dai_trigger, 1777 .set_fmt = fsi_dai_set_fmt, 1778 .hw_params = fsi_dai_hw_params, 1779 }; 1780 1781 /* 1782 * pcm ops 1783 */ 1784 1785 static struct snd_pcm_hardware fsi_pcm_hardware = { 1786 .info = SNDRV_PCM_INFO_INTERLEAVED | 1787 SNDRV_PCM_INFO_MMAP | 1788 SNDRV_PCM_INFO_MMAP_VALID | 1789 SNDRV_PCM_INFO_PAUSE, 1790 .buffer_bytes_max = 64 * 1024, 1791 .period_bytes_min = 32, 1792 .period_bytes_max = 8192, 1793 .periods_min = 1, 1794 .periods_max = 32, 1795 .fifo_size = 256, 1796 }; 1797 1798 static int fsi_pcm_open(struct snd_pcm_substream *substream) 1799 { 1800 struct snd_pcm_runtime *runtime = substream->runtime; 1801 int ret = 0; 1802 1803 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 1804 1805 ret = snd_pcm_hw_constraint_integer(runtime, 1806 SNDRV_PCM_HW_PARAM_PERIODS); 1807 1808 return ret; 1809 } 1810 1811 static int fsi_hw_params(struct snd_pcm_substream *substream, 1812 struct snd_pcm_hw_params *hw_params) 1813 { 1814 return snd_pcm_lib_malloc_pages(substream, 1815 params_buffer_bytes(hw_params)); 1816 } 1817 1818 static int fsi_hw_free(struct snd_pcm_substream *substream) 1819 { 1820 return snd_pcm_lib_free_pages(substream); 1821 } 1822 1823 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) 1824 { 1825 struct fsi_priv *fsi = fsi_get_priv(substream); 1826 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1827 1828 return fsi_sample2frame(fsi, io->buff_sample_pos); 1829 } 1830 1831 static struct snd_pcm_ops fsi_pcm_ops = { 1832 .open = fsi_pcm_open, 1833 .ioctl = snd_pcm_lib_ioctl, 1834 .hw_params = fsi_hw_params, 1835 .hw_free = fsi_hw_free, 1836 .pointer = fsi_pointer, 1837 }; 1838 1839 /* 1840 * snd_soc_platform 1841 */ 1842 1843 #define PREALLOC_BUFFER (32 * 1024) 1844 #define PREALLOC_BUFFER_MAX (32 * 1024) 1845 1846 static void fsi_pcm_free(struct snd_pcm *pcm) 1847 { 1848 snd_pcm_lib_preallocate_free_for_all(pcm); 1849 } 1850 1851 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) 1852 { 1853 struct snd_pcm *pcm = rtd->pcm; 1854 1855 /* 1856 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel 1857 * in MMAP mode (i.e. aplay -M) 1858 */ 1859 return snd_pcm_lib_preallocate_pages_for_all( 1860 pcm, 1861 SNDRV_DMA_TYPE_CONTINUOUS, 1862 snd_dma_continuous_data(GFP_KERNEL), 1863 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1864 } 1865 1866 /* 1867 * alsa struct 1868 */ 1869 1870 static struct snd_soc_dai_driver fsi_soc_dai[] = { 1871 { 1872 .name = "fsia-dai", 1873 .playback = { 1874 .rates = FSI_RATES, 1875 .formats = FSI_FMTS, 1876 .channels_min = 2, 1877 .channels_max = 2, 1878 }, 1879 .capture = { 1880 .rates = FSI_RATES, 1881 .formats = FSI_FMTS, 1882 .channels_min = 2, 1883 .channels_max = 2, 1884 }, 1885 .ops = &fsi_dai_ops, 1886 }, 1887 { 1888 .name = "fsib-dai", 1889 .playback = { 1890 .rates = FSI_RATES, 1891 .formats = FSI_FMTS, 1892 .channels_min = 2, 1893 .channels_max = 2, 1894 }, 1895 .capture = { 1896 .rates = FSI_RATES, 1897 .formats = FSI_FMTS, 1898 .channels_min = 2, 1899 .channels_max = 2, 1900 }, 1901 .ops = &fsi_dai_ops, 1902 }, 1903 }; 1904 1905 static struct snd_soc_platform_driver fsi_soc_platform = { 1906 .ops = &fsi_pcm_ops, 1907 .pcm_new = fsi_pcm_new, 1908 .pcm_free = fsi_pcm_free, 1909 }; 1910 1911 static const struct snd_soc_component_driver fsi_soc_component = { 1912 .name = "fsi", 1913 }; 1914 1915 /* 1916 * platform function 1917 */ 1918 static void fsi_of_parse(char *name, 1919 struct device_node *np, 1920 struct sh_fsi_port_info *info, 1921 struct device *dev) 1922 { 1923 int i; 1924 char prop[128]; 1925 unsigned long flags = 0; 1926 struct { 1927 char *name; 1928 unsigned int val; 1929 } of_parse_property[] = { 1930 { "spdif-connection", SH_FSI_FMT_SPDIF }, 1931 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE }, 1932 { "use-internal-clock", SH_FSI_CLK_CPG }, 1933 }; 1934 1935 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) { 1936 sprintf(prop, "%s,%s", name, of_parse_property[i].name); 1937 if (of_get_property(np, prop, NULL)) 1938 flags |= of_parse_property[i].val; 1939 } 1940 info->flags = flags; 1941 1942 dev_dbg(dev, "%s flags : %lx\n", name, info->flags); 1943 } 1944 1945 static void fsi_port_info_init(struct fsi_priv *fsi, 1946 struct sh_fsi_port_info *info) 1947 { 1948 if (info->flags & SH_FSI_FMT_SPDIF) 1949 fsi->spdif = 1; 1950 1951 if (info->flags & SH_FSI_CLK_CPG) 1952 fsi->clk_cpg = 1; 1953 1954 if (info->flags & SH_FSI_ENABLE_STREAM_MODE) 1955 fsi->enable_stream = 1; 1956 } 1957 1958 static void fsi_handler_init(struct fsi_priv *fsi, 1959 struct sh_fsi_port_info *info) 1960 { 1961 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ 1962 fsi->playback.priv = fsi; 1963 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ 1964 fsi->capture.priv = fsi; 1965 1966 if (info->tx_id) { 1967 fsi->playback.dma_id = info->tx_id; 1968 fsi->playback.handler = &fsi_dma_push_handler; 1969 } 1970 } 1971 1972 static struct of_device_id fsi_of_match[]; 1973 static int fsi_probe(struct platform_device *pdev) 1974 { 1975 struct fsi_master *master; 1976 struct device_node *np = pdev->dev.of_node; 1977 struct sh_fsi_platform_info info; 1978 const struct fsi_core *core; 1979 struct fsi_priv *fsi; 1980 struct resource *res; 1981 unsigned int irq; 1982 int ret; 1983 1984 memset(&info, 0, sizeof(info)); 1985 1986 core = NULL; 1987 if (np) { 1988 const struct of_device_id *of_id; 1989 1990 of_id = of_match_device(fsi_of_match, &pdev->dev); 1991 if (of_id) { 1992 core = of_id->data; 1993 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev); 1994 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev); 1995 } 1996 } else { 1997 const struct platform_device_id *id_entry = pdev->id_entry; 1998 if (id_entry) 1999 core = (struct fsi_core *)id_entry->driver_data; 2000 2001 if (pdev->dev.platform_data) 2002 memcpy(&info, pdev->dev.platform_data, sizeof(info)); 2003 } 2004 2005 if (!core) { 2006 dev_err(&pdev->dev, "unknown fsi device\n"); 2007 return -ENODEV; 2008 } 2009 2010 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2011 irq = platform_get_irq(pdev, 0); 2012 if (!res || (int)irq <= 0) { 2013 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 2014 return -ENODEV; 2015 } 2016 2017 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 2018 if (!master) { 2019 dev_err(&pdev->dev, "Could not allocate master\n"); 2020 return -ENOMEM; 2021 } 2022 2023 master->base = devm_ioremap_nocache(&pdev->dev, 2024 res->start, resource_size(res)); 2025 if (!master->base) { 2026 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 2027 return -ENXIO; 2028 } 2029 2030 /* master setting */ 2031 master->core = core; 2032 spin_lock_init(&master->lock); 2033 2034 /* FSI A setting */ 2035 fsi = &master->fsia; 2036 fsi->base = master->base; 2037 fsi->master = master; 2038 fsi_port_info_init(fsi, &info.port_a); 2039 fsi_handler_init(fsi, &info.port_a); 2040 ret = fsi_stream_probe(fsi, &pdev->dev); 2041 if (ret < 0) { 2042 dev_err(&pdev->dev, "FSIA stream probe failed\n"); 2043 return ret; 2044 } 2045 2046 /* FSI B setting */ 2047 fsi = &master->fsib; 2048 fsi->base = master->base + 0x40; 2049 fsi->master = master; 2050 fsi_port_info_init(fsi, &info.port_b); 2051 fsi_handler_init(fsi, &info.port_b); 2052 ret = fsi_stream_probe(fsi, &pdev->dev); 2053 if (ret < 0) { 2054 dev_err(&pdev->dev, "FSIB stream probe failed\n"); 2055 goto exit_fsia; 2056 } 2057 2058 pm_runtime_enable(&pdev->dev); 2059 dev_set_drvdata(&pdev->dev, master); 2060 2061 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, 2062 dev_name(&pdev->dev), master); 2063 if (ret) { 2064 dev_err(&pdev->dev, "irq request err\n"); 2065 goto exit_fsib; 2066 } 2067 2068 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); 2069 if (ret < 0) { 2070 dev_err(&pdev->dev, "cannot snd soc register\n"); 2071 goto exit_fsib; 2072 } 2073 2074 ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component, 2075 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 2076 if (ret < 0) { 2077 dev_err(&pdev->dev, "cannot snd component register\n"); 2078 goto exit_snd_soc; 2079 } 2080 2081 return ret; 2082 2083 exit_snd_soc: 2084 snd_soc_unregister_platform(&pdev->dev); 2085 exit_fsib: 2086 pm_runtime_disable(&pdev->dev); 2087 fsi_stream_remove(&master->fsib); 2088 exit_fsia: 2089 fsi_stream_remove(&master->fsia); 2090 2091 return ret; 2092 } 2093 2094 static int fsi_remove(struct platform_device *pdev) 2095 { 2096 struct fsi_master *master; 2097 2098 master = dev_get_drvdata(&pdev->dev); 2099 2100 pm_runtime_disable(&pdev->dev); 2101 2102 snd_soc_unregister_component(&pdev->dev); 2103 snd_soc_unregister_platform(&pdev->dev); 2104 2105 fsi_stream_remove(&master->fsia); 2106 fsi_stream_remove(&master->fsib); 2107 2108 return 0; 2109 } 2110 2111 static void __fsi_suspend(struct fsi_priv *fsi, 2112 struct fsi_stream *io, 2113 struct device *dev) 2114 { 2115 if (!fsi_stream_is_working(fsi, io)) 2116 return; 2117 2118 fsi_stream_stop(fsi, io); 2119 fsi_hw_shutdown(fsi, dev); 2120 } 2121 2122 static void __fsi_resume(struct fsi_priv *fsi, 2123 struct fsi_stream *io, 2124 struct device *dev) 2125 { 2126 if (!fsi_stream_is_working(fsi, io)) 2127 return; 2128 2129 fsi_hw_startup(fsi, io, dev); 2130 fsi_stream_start(fsi, io); 2131 } 2132 2133 static int fsi_suspend(struct device *dev) 2134 { 2135 struct fsi_master *master = dev_get_drvdata(dev); 2136 struct fsi_priv *fsia = &master->fsia; 2137 struct fsi_priv *fsib = &master->fsib; 2138 2139 __fsi_suspend(fsia, &fsia->playback, dev); 2140 __fsi_suspend(fsia, &fsia->capture, dev); 2141 2142 __fsi_suspend(fsib, &fsib->playback, dev); 2143 __fsi_suspend(fsib, &fsib->capture, dev); 2144 2145 return 0; 2146 } 2147 2148 static int fsi_resume(struct device *dev) 2149 { 2150 struct fsi_master *master = dev_get_drvdata(dev); 2151 struct fsi_priv *fsia = &master->fsia; 2152 struct fsi_priv *fsib = &master->fsib; 2153 2154 __fsi_resume(fsia, &fsia->playback, dev); 2155 __fsi_resume(fsia, &fsia->capture, dev); 2156 2157 __fsi_resume(fsib, &fsib->playback, dev); 2158 __fsi_resume(fsib, &fsib->capture, dev); 2159 2160 return 0; 2161 } 2162 2163 static struct dev_pm_ops fsi_pm_ops = { 2164 .suspend = fsi_suspend, 2165 .resume = fsi_resume, 2166 }; 2167 2168 static struct fsi_core fsi1_core = { 2169 .ver = 1, 2170 2171 /* Interrupt */ 2172 .int_st = INT_ST, 2173 .iemsk = IEMSK, 2174 .imsk = IMSK, 2175 }; 2176 2177 static struct fsi_core fsi2_core = { 2178 .ver = 2, 2179 2180 /* Interrupt */ 2181 .int_st = CPU_INT_ST, 2182 .iemsk = CPU_IEMSK, 2183 .imsk = CPU_IMSK, 2184 .a_mclk = A_MST_CTLR, 2185 .b_mclk = B_MST_CTLR, 2186 }; 2187 2188 static struct of_device_id fsi_of_match[] = { 2189 { .compatible = "renesas,sh_fsi", .data = &fsi1_core}, 2190 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core}, 2191 {}, 2192 }; 2193 MODULE_DEVICE_TABLE(of, fsi_of_match); 2194 2195 static struct platform_device_id fsi_id_table[] = { 2196 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, 2197 { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, 2198 {}, 2199 }; 2200 MODULE_DEVICE_TABLE(platform, fsi_id_table); 2201 2202 static struct platform_driver fsi_driver = { 2203 .driver = { 2204 .name = "fsi-pcm-audio", 2205 .pm = &fsi_pm_ops, 2206 .of_match_table = fsi_of_match, 2207 }, 2208 .probe = fsi_probe, 2209 .remove = fsi_remove, 2210 .id_table = fsi_id_table, 2211 }; 2212 2213 module_platform_driver(fsi_driver); 2214 2215 MODULE_LICENSE("GPL"); 2216 MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); 2217 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 2218 MODULE_ALIAS("platform:fsi-pcm-audio"); 2219