1 /* 2 * Fifo-attached Serial Interface (FSI) support for SH7724 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on ssi.c 8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/io.h> 19 #include <linux/scatterlist.h> 20 #include <linux/sh_dma.h> 21 #include <linux/slab.h> 22 #include <linux/module.h> 23 #include <linux/workqueue.h> 24 #include <sound/soc.h> 25 #include <sound/pcm_params.h> 26 #include <sound/sh_fsi.h> 27 28 /* PortA/PortB register */ 29 #define REG_DO_FMT 0x0000 30 #define REG_DOFF_CTL 0x0004 31 #define REG_DOFF_ST 0x0008 32 #define REG_DI_FMT 0x000C 33 #define REG_DIFF_CTL 0x0010 34 #define REG_DIFF_ST 0x0014 35 #define REG_CKG1 0x0018 36 #define REG_CKG2 0x001C 37 #define REG_DIDT 0x0020 38 #define REG_DODT 0x0024 39 #define REG_MUTE_ST 0x0028 40 #define REG_OUT_DMAC 0x002C 41 #define REG_OUT_SEL 0x0030 42 #define REG_IN_DMAC 0x0038 43 44 /* master register */ 45 #define MST_CLK_RST 0x0210 46 #define MST_SOFT_RST 0x0214 47 #define MST_FIFO_SZ 0x0218 48 49 /* core register (depend on FSI version) */ 50 #define A_MST_CTLR 0x0180 51 #define B_MST_CTLR 0x01A0 52 #define CPU_INT_ST 0x01F4 53 #define CPU_IEMSK 0x01F8 54 #define CPU_IMSK 0x01FC 55 #define INT_ST 0x0200 56 #define IEMSK 0x0204 57 #define IMSK 0x0208 58 59 /* DO_FMT */ 60 /* DI_FMT */ 61 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */ 62 #define CR_BWS_24 (0x0 << 20) /* FSI2 */ 63 #define CR_BWS_16 (0x1 << 20) /* FSI2 */ 64 #define CR_BWS_20 (0x2 << 20) /* FSI2 */ 65 66 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ 67 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ 68 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ 69 70 #define CR_MONO (0x0 << 4) 71 #define CR_MONO_D (0x1 << 4) 72 #define CR_PCM (0x2 << 4) 73 #define CR_I2S (0x3 << 4) 74 #define CR_TDM (0x4 << 4) 75 #define CR_TDM_D (0x5 << 4) 76 77 /* OUT_DMAC */ 78 /* IN_DMAC */ 79 #define VDMD_MASK (0x3 << 4) 80 #define VDMD_FRONT (0x0 << 4) /* Package in front */ 81 #define VDMD_BACK (0x1 << 4) /* Package in back */ 82 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ 83 84 #define DMA_ON (0x1 << 0) 85 86 /* DOFF_CTL */ 87 /* DIFF_CTL */ 88 #define IRQ_HALF 0x00100000 89 #define FIFO_CLR 0x00000001 90 91 /* DOFF_ST */ 92 #define ERR_OVER 0x00000010 93 #define ERR_UNDER 0x00000001 94 #define ST_ERR (ERR_OVER | ERR_UNDER) 95 96 /* CKG1 */ 97 #define ACKMD_MASK 0x00007000 98 #define BPFMD_MASK 0x00000700 99 #define DIMD (1 << 4) 100 #define DOMD (1 << 0) 101 102 /* A/B MST_CTLR */ 103 #define BP (1 << 4) /* Fix the signal of Biphase output */ 104 #define SE (1 << 0) /* Fix the master clock */ 105 106 /* CLK_RST */ 107 #define CRB (1 << 4) 108 #define CRA (1 << 0) 109 110 /* IO SHIFT / MACRO */ 111 #define BI_SHIFT 12 112 #define BO_SHIFT 8 113 #define AI_SHIFT 4 114 #define AO_SHIFT 0 115 #define AB_IO(param, shift) (param << shift) 116 117 /* SOFT_RST */ 118 #define PBSR (1 << 12) /* Port B Software Reset */ 119 #define PASR (1 << 8) /* Port A Software Reset */ 120 #define IR (1 << 4) /* Interrupt Reset */ 121 #define FSISR (1 << 0) /* Software Reset */ 122 123 /* OUT_SEL (FSI2) */ 124 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ 125 /* 1: Biphase and serial */ 126 127 /* FIFO_SZ */ 128 #define FIFO_SZ_MASK 0x7 129 130 #define FSI_RATES SNDRV_PCM_RATE_8000_96000 131 132 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 133 134 typedef int (*set_rate_func)(struct device *dev, int rate, int enable); 135 136 /* 137 * bus options 138 * 139 * 0x000000BA 140 * 141 * A : sample widtht 16bit setting 142 * B : sample widtht 24bit setting 143 */ 144 145 #define SHIFT_16DATA 0 146 #define SHIFT_24DATA 4 147 148 #define PACKAGE_24BITBUS_BACK 0 149 #define PACKAGE_24BITBUS_FRONT 1 150 #define PACKAGE_16BITBUS_STREAM 2 151 152 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) 153 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) 154 155 /* 156 * FSI driver use below type name for variable 157 * 158 * xxx_num : number of data 159 * xxx_pos : position of data 160 * xxx_capa : capacity of data 161 */ 162 163 /* 164 * period/frame/sample image 165 * 166 * ex) PCM (2ch) 167 * 168 * period pos period pos 169 * [n] [n + 1] 170 * |<-------------------- period--------------------->| 171 * ==|============================================ ... =|== 172 * | | 173 * ||<----- frame ----->|<------ frame ----->| ... | 174 * |+--------------------+--------------------+- ... | 175 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | 176 * |+--------------------+--------------------+- ... | 177 * ==|============================================ ... =|== 178 */ 179 180 /* 181 * FSI FIFO image 182 * 183 * | | 184 * | | 185 * | [ sample ] | 186 * | [ sample ] | 187 * | [ sample ] | 188 * | [ sample ] | 189 * --> go to codecs 190 */ 191 192 /* 193 * FSI clock 194 * 195 * FSIxCLK [CPG] (ick) -------> | 196 * |-> FSI_DIV (div)-> FSI2 197 * FSIxCK [external] (xck) ---> | 198 */ 199 200 /* 201 * struct 202 */ 203 204 struct fsi_stream_handler; 205 struct fsi_stream { 206 207 /* 208 * these are initialized by fsi_stream_init() 209 */ 210 struct snd_pcm_substream *substream; 211 int fifo_sample_capa; /* sample capacity of FSI FIFO */ 212 int buff_sample_capa; /* sample capacity of ALSA buffer */ 213 int buff_sample_pos; /* sample position of ALSA buffer */ 214 int period_samples; /* sample number / 1 period */ 215 int period_pos; /* current period position */ 216 int sample_width; /* sample width */ 217 int uerr_num; 218 int oerr_num; 219 220 /* 221 * bus options 222 */ 223 u32 bus_option; 224 225 /* 226 * thse are initialized by fsi_handler_init() 227 */ 228 struct fsi_stream_handler *handler; 229 struct fsi_priv *priv; 230 231 /* 232 * these are for DMAEngine 233 */ 234 struct dma_chan *chan; 235 struct sh_dmae_slave slave; /* see fsi_handler_init() */ 236 struct work_struct work; 237 dma_addr_t dma; 238 }; 239 240 struct fsi_clk { 241 /* see [FSI clock] */ 242 struct clk *own; 243 struct clk *xck; 244 struct clk *ick; 245 struct clk *div; 246 int (*set_rate)(struct device *dev, 247 struct fsi_priv *fsi, 248 unsigned long rate); 249 250 unsigned long rate; 251 unsigned int count; 252 }; 253 254 struct fsi_priv { 255 void __iomem *base; 256 struct fsi_master *master; 257 struct sh_fsi_port_info *info; 258 259 struct fsi_stream playback; 260 struct fsi_stream capture; 261 262 struct fsi_clk clock; 263 264 u32 fmt; 265 266 int chan_num:16; 267 int clk_master:1; 268 int clk_cpg:1; 269 int spdif:1; 270 int enable_stream:1; 271 int bit_clk_inv:1; 272 int lr_clk_inv:1; 273 274 long rate; 275 }; 276 277 struct fsi_stream_handler { 278 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); 279 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); 280 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); 281 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); 282 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); 283 void (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, 284 int enable); 285 }; 286 #define fsi_stream_handler_call(io, func, args...) \ 287 (!(io) ? -ENODEV : \ 288 !((io)->handler->func) ? 0 : \ 289 (io)->handler->func(args)) 290 291 struct fsi_core { 292 int ver; 293 294 u32 int_st; 295 u32 iemsk; 296 u32 imsk; 297 u32 a_mclk; 298 u32 b_mclk; 299 }; 300 301 struct fsi_master { 302 void __iomem *base; 303 int irq; 304 struct fsi_priv fsia; 305 struct fsi_priv fsib; 306 struct fsi_core *core; 307 spinlock_t lock; 308 }; 309 310 static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io); 311 312 /* 313 * basic read write function 314 */ 315 316 static void __fsi_reg_write(u32 __iomem *reg, u32 data) 317 { 318 /* valid data area is 24bit */ 319 data &= 0x00ffffff; 320 321 __raw_writel(data, reg); 322 } 323 324 static u32 __fsi_reg_read(u32 __iomem *reg) 325 { 326 return __raw_readl(reg); 327 } 328 329 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) 330 { 331 u32 val = __fsi_reg_read(reg); 332 333 val &= ~mask; 334 val |= data & mask; 335 336 __fsi_reg_write(reg, val); 337 } 338 339 #define fsi_reg_write(p, r, d)\ 340 __fsi_reg_write((p->base + REG_##r), d) 341 342 #define fsi_reg_read(p, r)\ 343 __fsi_reg_read((p->base + REG_##r)) 344 345 #define fsi_reg_mask_set(p, r, m, d)\ 346 __fsi_reg_mask_set((p->base + REG_##r), m, d) 347 348 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) 349 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) 350 static u32 _fsi_master_read(struct fsi_master *master, u32 reg) 351 { 352 u32 ret; 353 unsigned long flags; 354 355 spin_lock_irqsave(&master->lock, flags); 356 ret = __fsi_reg_read(master->base + reg); 357 spin_unlock_irqrestore(&master->lock, flags); 358 359 return ret; 360 } 361 362 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) 363 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) 364 static void _fsi_master_mask_set(struct fsi_master *master, 365 u32 reg, u32 mask, u32 data) 366 { 367 unsigned long flags; 368 369 spin_lock_irqsave(&master->lock, flags); 370 __fsi_reg_mask_set(master->base + reg, mask, data); 371 spin_unlock_irqrestore(&master->lock, flags); 372 } 373 374 /* 375 * basic function 376 */ 377 static int fsi_version(struct fsi_master *master) 378 { 379 return master->core->ver; 380 } 381 382 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) 383 { 384 return fsi->master; 385 } 386 387 static int fsi_is_clk_master(struct fsi_priv *fsi) 388 { 389 return fsi->clk_master; 390 } 391 392 static int fsi_is_port_a(struct fsi_priv *fsi) 393 { 394 return fsi->master->base == fsi->base; 395 } 396 397 static int fsi_is_spdif(struct fsi_priv *fsi) 398 { 399 return fsi->spdif; 400 } 401 402 static int fsi_is_enable_stream(struct fsi_priv *fsi) 403 { 404 return fsi->enable_stream; 405 } 406 407 static int fsi_is_play(struct snd_pcm_substream *substream) 408 { 409 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 410 } 411 412 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) 413 { 414 struct snd_soc_pcm_runtime *rtd = substream->private_data; 415 416 return rtd->cpu_dai; 417 } 418 419 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) 420 { 421 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); 422 423 if (dai->id == 0) 424 return &master->fsia; 425 else 426 return &master->fsib; 427 } 428 429 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) 430 { 431 return fsi_get_priv_frm_dai(fsi_get_dai(substream)); 432 } 433 434 static set_rate_func fsi_get_info_set_rate(struct fsi_priv *fsi) 435 { 436 if (!fsi->info) 437 return NULL; 438 439 return fsi->info->set_rate; 440 } 441 442 static u32 fsi_get_info_flags(struct fsi_priv *fsi) 443 { 444 if (!fsi->info) 445 return 0; 446 447 return fsi->info->flags; 448 } 449 450 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) 451 { 452 int is_play = fsi_stream_is_play(fsi, io); 453 int is_porta = fsi_is_port_a(fsi); 454 u32 shift; 455 456 if (is_porta) 457 shift = is_play ? AO_SHIFT : AI_SHIFT; 458 else 459 shift = is_play ? BO_SHIFT : BI_SHIFT; 460 461 return shift; 462 } 463 464 static int fsi_frame2sample(struct fsi_priv *fsi, int frames) 465 { 466 return frames * fsi->chan_num; 467 } 468 469 static int fsi_sample2frame(struct fsi_priv *fsi, int samples) 470 { 471 return samples / fsi->chan_num; 472 } 473 474 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, 475 struct fsi_stream *io) 476 { 477 int is_play = fsi_stream_is_play(fsi, io); 478 u32 status; 479 int frames; 480 481 status = is_play ? 482 fsi_reg_read(fsi, DOFF_ST) : 483 fsi_reg_read(fsi, DIFF_ST); 484 485 frames = 0x1ff & (status >> 8); 486 487 return fsi_frame2sample(fsi, frames); 488 } 489 490 static void fsi_count_fifo_err(struct fsi_priv *fsi) 491 { 492 u32 ostatus = fsi_reg_read(fsi, DOFF_ST); 493 u32 istatus = fsi_reg_read(fsi, DIFF_ST); 494 495 if (ostatus & ERR_OVER) 496 fsi->playback.oerr_num++; 497 498 if (ostatus & ERR_UNDER) 499 fsi->playback.uerr_num++; 500 501 if (istatus & ERR_OVER) 502 fsi->capture.oerr_num++; 503 504 if (istatus & ERR_UNDER) 505 fsi->capture.uerr_num++; 506 507 fsi_reg_write(fsi, DOFF_ST, 0); 508 fsi_reg_write(fsi, DIFF_ST, 0); 509 } 510 511 /* 512 * fsi_stream_xx() function 513 */ 514 static inline int fsi_stream_is_play(struct fsi_priv *fsi, 515 struct fsi_stream *io) 516 { 517 return &fsi->playback == io; 518 } 519 520 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, 521 struct snd_pcm_substream *substream) 522 { 523 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; 524 } 525 526 static int fsi_stream_is_working(struct fsi_priv *fsi, 527 struct fsi_stream *io) 528 { 529 struct fsi_master *master = fsi_get_master(fsi); 530 unsigned long flags; 531 int ret; 532 533 spin_lock_irqsave(&master->lock, flags); 534 ret = !!(io->substream && io->substream->runtime); 535 spin_unlock_irqrestore(&master->lock, flags); 536 537 return ret; 538 } 539 540 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) 541 { 542 return io->priv; 543 } 544 545 static void fsi_stream_init(struct fsi_priv *fsi, 546 struct fsi_stream *io, 547 struct snd_pcm_substream *substream) 548 { 549 struct snd_pcm_runtime *runtime = substream->runtime; 550 struct fsi_master *master = fsi_get_master(fsi); 551 unsigned long flags; 552 553 spin_lock_irqsave(&master->lock, flags); 554 io->substream = substream; 555 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); 556 io->buff_sample_pos = 0; 557 io->period_samples = fsi_frame2sample(fsi, runtime->period_size); 558 io->period_pos = 0; 559 io->sample_width = samples_to_bytes(runtime, 1); 560 io->bus_option = 0; 561 io->oerr_num = -1; /* ignore 1st err */ 562 io->uerr_num = -1; /* ignore 1st err */ 563 fsi_stream_handler_call(io, init, fsi, io); 564 spin_unlock_irqrestore(&master->lock, flags); 565 } 566 567 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) 568 { 569 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 570 struct fsi_master *master = fsi_get_master(fsi); 571 unsigned long flags; 572 573 spin_lock_irqsave(&master->lock, flags); 574 575 if (io->oerr_num > 0) 576 dev_err(dai->dev, "over_run = %d\n", io->oerr_num); 577 578 if (io->uerr_num > 0) 579 dev_err(dai->dev, "under_run = %d\n", io->uerr_num); 580 581 fsi_stream_handler_call(io, quit, fsi, io); 582 io->substream = NULL; 583 io->buff_sample_capa = 0; 584 io->buff_sample_pos = 0; 585 io->period_samples = 0; 586 io->period_pos = 0; 587 io->sample_width = 0; 588 io->bus_option = 0; 589 io->oerr_num = 0; 590 io->uerr_num = 0; 591 spin_unlock_irqrestore(&master->lock, flags); 592 } 593 594 static int fsi_stream_transfer(struct fsi_stream *io) 595 { 596 struct fsi_priv *fsi = fsi_stream_to_priv(io); 597 if (!fsi) 598 return -EIO; 599 600 return fsi_stream_handler_call(io, transfer, fsi, io); 601 } 602 603 #define fsi_stream_start(fsi, io)\ 604 fsi_stream_handler_call(io, start_stop, fsi, io, 1) 605 606 #define fsi_stream_stop(fsi, io)\ 607 fsi_stream_handler_call(io, start_stop, fsi, io, 0) 608 609 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) 610 { 611 struct fsi_stream *io; 612 int ret1, ret2; 613 614 io = &fsi->playback; 615 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); 616 617 io = &fsi->capture; 618 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); 619 620 if (ret1 < 0) 621 return ret1; 622 if (ret2 < 0) 623 return ret2; 624 625 return 0; 626 } 627 628 static int fsi_stream_remove(struct fsi_priv *fsi) 629 { 630 struct fsi_stream *io; 631 int ret1, ret2; 632 633 io = &fsi->playback; 634 ret1 = fsi_stream_handler_call(io, remove, fsi, io); 635 636 io = &fsi->capture; 637 ret2 = fsi_stream_handler_call(io, remove, fsi, io); 638 639 if (ret1 < 0) 640 return ret1; 641 if (ret2 < 0) 642 return ret2; 643 644 return 0; 645 } 646 647 /* 648 * format/bus/dma setting 649 */ 650 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, 651 u32 bus, struct device *dev) 652 { 653 struct fsi_master *master = fsi_get_master(fsi); 654 int is_play = fsi_stream_is_play(fsi, io); 655 u32 fmt = fsi->fmt; 656 657 if (fsi_version(master) >= 2) { 658 u32 dma = 0; 659 660 /* 661 * FSI2 needs DMA/Bus setting 662 */ 663 switch (bus) { 664 case PACKAGE_24BITBUS_FRONT: 665 fmt |= CR_BWS_24; 666 dma |= VDMD_FRONT; 667 dev_dbg(dev, "24bit bus / package in front\n"); 668 break; 669 case PACKAGE_16BITBUS_STREAM: 670 fmt |= CR_BWS_16; 671 dma |= VDMD_STREAM; 672 dev_dbg(dev, "16bit bus / stream mode\n"); 673 break; 674 case PACKAGE_24BITBUS_BACK: 675 default: 676 fmt |= CR_BWS_24; 677 dma |= VDMD_BACK; 678 dev_dbg(dev, "24bit bus / package in back\n"); 679 break; 680 } 681 682 if (is_play) 683 fsi_reg_write(fsi, OUT_DMAC, dma); 684 else 685 fsi_reg_write(fsi, IN_DMAC, dma); 686 } 687 688 if (is_play) 689 fsi_reg_write(fsi, DO_FMT, fmt); 690 else 691 fsi_reg_write(fsi, DI_FMT, fmt); 692 } 693 694 /* 695 * irq function 696 */ 697 698 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) 699 { 700 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 701 struct fsi_master *master = fsi_get_master(fsi); 702 703 fsi_core_mask_set(master, imsk, data, data); 704 fsi_core_mask_set(master, iemsk, data, data); 705 } 706 707 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) 708 { 709 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 710 struct fsi_master *master = fsi_get_master(fsi); 711 712 fsi_core_mask_set(master, imsk, data, 0); 713 fsi_core_mask_set(master, iemsk, data, 0); 714 } 715 716 static u32 fsi_irq_get_status(struct fsi_master *master) 717 { 718 return fsi_core_read(master, int_st); 719 } 720 721 static void fsi_irq_clear_status(struct fsi_priv *fsi) 722 { 723 u32 data = 0; 724 struct fsi_master *master = fsi_get_master(fsi); 725 726 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); 727 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); 728 729 /* clear interrupt factor */ 730 fsi_core_mask_set(master, int_st, data, 0); 731 } 732 733 /* 734 * SPDIF master clock function 735 * 736 * These functions are used later FSI2 737 */ 738 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) 739 { 740 struct fsi_master *master = fsi_get_master(fsi); 741 u32 mask, val; 742 743 mask = BP | SE; 744 val = enable ? mask : 0; 745 746 fsi_is_port_a(fsi) ? 747 fsi_core_mask_set(master, a_mclk, mask, val) : 748 fsi_core_mask_set(master, b_mclk, mask, val); 749 } 750 751 /* 752 * clock function 753 */ 754 static int fsi_clk_init(struct device *dev, 755 struct fsi_priv *fsi, 756 int xck, 757 int ick, 758 int div, 759 int (*set_rate)(struct device *dev, 760 struct fsi_priv *fsi, 761 unsigned long rate)) 762 { 763 struct fsi_clk *clock = &fsi->clock; 764 int is_porta = fsi_is_port_a(fsi); 765 766 clock->xck = NULL; 767 clock->ick = NULL; 768 clock->div = NULL; 769 clock->rate = 0; 770 clock->count = 0; 771 clock->set_rate = set_rate; 772 773 clock->own = devm_clk_get(dev, NULL); 774 if (IS_ERR(clock->own)) 775 return -EINVAL; 776 777 /* external clock */ 778 if (xck) { 779 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); 780 if (IS_ERR(clock->xck)) { 781 dev_err(dev, "can't get xck clock\n"); 782 return -EINVAL; 783 } 784 if (clock->xck == clock->own) { 785 dev_err(dev, "cpu doesn't support xck clock\n"); 786 return -EINVAL; 787 } 788 } 789 790 /* FSIACLK/FSIBCLK */ 791 if (ick) { 792 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); 793 if (IS_ERR(clock->ick)) { 794 dev_err(dev, "can't get ick clock\n"); 795 return -EINVAL; 796 } 797 if (clock->ick == clock->own) { 798 dev_err(dev, "cpu doesn't support ick clock\n"); 799 return -EINVAL; 800 } 801 } 802 803 /* FSI-DIV */ 804 if (div) { 805 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); 806 if (IS_ERR(clock->div)) { 807 dev_err(dev, "can't get div clock\n"); 808 return -EINVAL; 809 } 810 if (clock->div == clock->own) { 811 dev_err(dev, "cpu doens't support div clock\n"); 812 return -EINVAL; 813 } 814 } 815 816 return 0; 817 } 818 819 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) 820 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) 821 { 822 fsi->clock.rate = rate; 823 } 824 825 static int fsi_clk_is_valid(struct fsi_priv *fsi) 826 { 827 return fsi->clock.set_rate && 828 fsi->clock.rate; 829 } 830 831 static int fsi_clk_enable(struct device *dev, 832 struct fsi_priv *fsi, 833 unsigned long rate) 834 { 835 struct fsi_clk *clock = &fsi->clock; 836 int ret = -EINVAL; 837 838 if (!fsi_clk_is_valid(fsi)) 839 return ret; 840 841 if (0 == clock->count) { 842 ret = clock->set_rate(dev, fsi, rate); 843 if (ret < 0) { 844 fsi_clk_invalid(fsi); 845 return ret; 846 } 847 848 if (clock->xck) 849 clk_enable(clock->xck); 850 if (clock->ick) 851 clk_enable(clock->ick); 852 if (clock->div) 853 clk_enable(clock->div); 854 855 clock->count++; 856 } 857 858 return ret; 859 } 860 861 static int fsi_clk_disable(struct device *dev, 862 struct fsi_priv *fsi) 863 { 864 struct fsi_clk *clock = &fsi->clock; 865 866 if (!fsi_clk_is_valid(fsi)) 867 return -EINVAL; 868 869 if (1 == clock->count--) { 870 if (clock->xck) 871 clk_disable(clock->xck); 872 if (clock->ick) 873 clk_disable(clock->ick); 874 if (clock->div) 875 clk_disable(clock->div); 876 } 877 878 return 0; 879 } 880 881 static int fsi_clk_set_ackbpf(struct device *dev, 882 struct fsi_priv *fsi, 883 int ackmd, int bpfmd) 884 { 885 u32 data = 0; 886 887 /* check ackmd/bpfmd relationship */ 888 if (bpfmd > ackmd) { 889 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); 890 return -EINVAL; 891 } 892 893 /* ACKMD */ 894 switch (ackmd) { 895 case 512: 896 data |= (0x0 << 12); 897 break; 898 case 256: 899 data |= (0x1 << 12); 900 break; 901 case 128: 902 data |= (0x2 << 12); 903 break; 904 case 64: 905 data |= (0x3 << 12); 906 break; 907 case 32: 908 data |= (0x4 << 12); 909 break; 910 default: 911 dev_err(dev, "unsupported ackmd (%d)\n", ackmd); 912 return -EINVAL; 913 } 914 915 /* BPFMD */ 916 switch (bpfmd) { 917 case 32: 918 data |= (0x0 << 8); 919 break; 920 case 64: 921 data |= (0x1 << 8); 922 break; 923 case 128: 924 data |= (0x2 << 8); 925 break; 926 case 256: 927 data |= (0x3 << 8); 928 break; 929 case 512: 930 data |= (0x4 << 8); 931 break; 932 case 16: 933 data |= (0x7 << 8); 934 break; 935 default: 936 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); 937 return -EINVAL; 938 } 939 940 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); 941 942 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 943 udelay(10); 944 945 return 0; 946 } 947 948 static int fsi_clk_set_rate_external(struct device *dev, 949 struct fsi_priv *fsi, 950 unsigned long rate) 951 { 952 struct clk *xck = fsi->clock.xck; 953 struct clk *ick = fsi->clock.ick; 954 unsigned long xrate; 955 int ackmd, bpfmd; 956 int ret = 0; 957 958 /* check clock rate */ 959 xrate = clk_get_rate(xck); 960 if (xrate % rate) { 961 dev_err(dev, "unsupported clock rate\n"); 962 return -EINVAL; 963 } 964 965 clk_set_parent(ick, xck); 966 clk_set_rate(ick, xrate); 967 968 bpfmd = fsi->chan_num * 32; 969 ackmd = xrate / rate; 970 971 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); 972 973 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 974 if (ret < 0) 975 dev_err(dev, "%s failed", __func__); 976 977 return ret; 978 } 979 980 static int fsi_clk_set_rate_cpg(struct device *dev, 981 struct fsi_priv *fsi, 982 unsigned long rate) 983 { 984 struct clk *ick = fsi->clock.ick; 985 struct clk *div = fsi->clock.div; 986 unsigned long target = 0; /* 12288000 or 11289600 */ 987 unsigned long actual, cout; 988 unsigned long diff, min; 989 unsigned long best_cout, best_act; 990 int adj; 991 int ackmd, bpfmd; 992 int ret = -EINVAL; 993 994 if (!(12288000 % rate)) 995 target = 12288000; 996 if (!(11289600 % rate)) 997 target = 11289600; 998 if (!target) { 999 dev_err(dev, "unsupported rate\n"); 1000 return ret; 1001 } 1002 1003 bpfmd = fsi->chan_num * 32; 1004 ackmd = target / rate; 1005 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 1006 if (ret < 0) { 1007 dev_err(dev, "%s failed", __func__); 1008 return ret; 1009 } 1010 1011 /* 1012 * The clock flow is 1013 * 1014 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] 1015 * 1016 * But, it needs to find best match of CPG and FSI_DIV 1017 * combination, since it is difficult to generate correct 1018 * frequency of audio clock from ick clock only. 1019 * Because ick is created from its parent clock. 1020 * 1021 * target = rate x [512/256/128/64]fs 1022 * cout = round(target x adjustment) 1023 * actual = cout / adjustment (by FSI-DIV) ~= target 1024 * audio = actual 1025 */ 1026 min = ~0; 1027 best_cout = 0; 1028 best_act = 0; 1029 for (adj = 1; adj < 0xffff; adj++) { 1030 1031 cout = target * adj; 1032 if (cout > 100000000) /* max clock = 100MHz */ 1033 break; 1034 1035 /* cout/actual audio clock */ 1036 cout = clk_round_rate(ick, cout); 1037 actual = cout / adj; 1038 1039 /* find best frequency */ 1040 diff = abs(actual - target); 1041 if (diff < min) { 1042 min = diff; 1043 best_cout = cout; 1044 best_act = actual; 1045 } 1046 } 1047 1048 ret = clk_set_rate(ick, best_cout); 1049 if (ret < 0) { 1050 dev_err(dev, "ick clock failed\n"); 1051 return -EIO; 1052 } 1053 1054 ret = clk_set_rate(div, clk_round_rate(div, best_act)); 1055 if (ret < 0) { 1056 dev_err(dev, "div clock failed\n"); 1057 return -EIO; 1058 } 1059 1060 dev_dbg(dev, "ick/div = %ld/%ld\n", 1061 clk_get_rate(ick), clk_get_rate(div)); 1062 1063 return ret; 1064 } 1065 1066 static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi, 1067 long rate, int enable) 1068 { 1069 set_rate_func set_rate = fsi_get_info_set_rate(fsi); 1070 int ret; 1071 1072 /* 1073 * CAUTION 1074 * 1075 * set_rate will be deleted 1076 */ 1077 if (!set_rate) { 1078 if (enable) 1079 return fsi_clk_enable(dev, fsi, rate); 1080 else 1081 return fsi_clk_disable(dev, fsi); 1082 } 1083 1084 ret = set_rate(dev, rate, enable); 1085 if (ret < 0) /* error */ 1086 return ret; 1087 1088 if (!enable) 1089 return 0; 1090 1091 if (ret > 0) { 1092 u32 data = 0; 1093 1094 switch (ret & SH_FSI_ACKMD_MASK) { 1095 default: 1096 /* FALL THROUGH */ 1097 case SH_FSI_ACKMD_512: 1098 data |= (0x0 << 12); 1099 break; 1100 case SH_FSI_ACKMD_256: 1101 data |= (0x1 << 12); 1102 break; 1103 case SH_FSI_ACKMD_128: 1104 data |= (0x2 << 12); 1105 break; 1106 case SH_FSI_ACKMD_64: 1107 data |= (0x3 << 12); 1108 break; 1109 case SH_FSI_ACKMD_32: 1110 data |= (0x4 << 12); 1111 break; 1112 } 1113 1114 switch (ret & SH_FSI_BPFMD_MASK) { 1115 default: 1116 /* FALL THROUGH */ 1117 case SH_FSI_BPFMD_32: 1118 data |= (0x0 << 8); 1119 break; 1120 case SH_FSI_BPFMD_64: 1121 data |= (0x1 << 8); 1122 break; 1123 case SH_FSI_BPFMD_128: 1124 data |= (0x2 << 8); 1125 break; 1126 case SH_FSI_BPFMD_256: 1127 data |= (0x3 << 8); 1128 break; 1129 case SH_FSI_BPFMD_512: 1130 data |= (0x4 << 8); 1131 break; 1132 case SH_FSI_BPFMD_16: 1133 data |= (0x7 << 8); 1134 break; 1135 } 1136 1137 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 1138 udelay(10); 1139 ret = 0; 1140 } 1141 1142 return ret; 1143 } 1144 1145 /* 1146 * pio data transfer handler 1147 */ 1148 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) 1149 { 1150 int i; 1151 1152 if (fsi_is_enable_stream(fsi)) { 1153 /* 1154 * stream mode 1155 * see 1156 * fsi_pio_push_init() 1157 */ 1158 u32 *buf = (u32 *)_buf; 1159 1160 for (i = 0; i < samples / 2; i++) 1161 fsi_reg_write(fsi, DODT, buf[i]); 1162 } else { 1163 /* normal mode */ 1164 u16 *buf = (u16 *)_buf; 1165 1166 for (i = 0; i < samples; i++) 1167 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); 1168 } 1169 } 1170 1171 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) 1172 { 1173 u16 *buf = (u16 *)_buf; 1174 int i; 1175 1176 for (i = 0; i < samples; i++) 1177 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); 1178 } 1179 1180 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) 1181 { 1182 u32 *buf = (u32 *)_buf; 1183 int i; 1184 1185 for (i = 0; i < samples; i++) 1186 fsi_reg_write(fsi, DODT, *(buf + i)); 1187 } 1188 1189 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) 1190 { 1191 u32 *buf = (u32 *)_buf; 1192 int i; 1193 1194 for (i = 0; i < samples; i++) 1195 *(buf + i) = fsi_reg_read(fsi, DIDT); 1196 } 1197 1198 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) 1199 { 1200 struct snd_pcm_runtime *runtime = io->substream->runtime; 1201 1202 return runtime->dma_area + 1203 samples_to_bytes(runtime, io->buff_sample_pos); 1204 } 1205 1206 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, 1207 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), 1208 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), 1209 int samples) 1210 { 1211 struct snd_pcm_runtime *runtime; 1212 struct snd_pcm_substream *substream; 1213 u8 *buf; 1214 int over_period; 1215 1216 if (!fsi_stream_is_working(fsi, io)) 1217 return -EINVAL; 1218 1219 over_period = 0; 1220 substream = io->substream; 1221 runtime = substream->runtime; 1222 1223 /* FSI FIFO has limit. 1224 * So, this driver can not send periods data at a time 1225 */ 1226 if (io->buff_sample_pos >= 1227 io->period_samples * (io->period_pos + 1)) { 1228 1229 over_period = 1; 1230 io->period_pos = (io->period_pos + 1) % runtime->periods; 1231 1232 if (0 == io->period_pos) 1233 io->buff_sample_pos = 0; 1234 } 1235 1236 buf = fsi_pio_get_area(fsi, io); 1237 1238 switch (io->sample_width) { 1239 case 2: 1240 run16(fsi, buf, samples); 1241 break; 1242 case 4: 1243 run32(fsi, buf, samples); 1244 break; 1245 default: 1246 return -EINVAL; 1247 } 1248 1249 /* update buff_sample_pos */ 1250 io->buff_sample_pos += samples; 1251 1252 if (over_period) 1253 snd_pcm_period_elapsed(substream); 1254 1255 return 0; 1256 } 1257 1258 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) 1259 { 1260 int sample_residues; /* samples in FSI fifo */ 1261 int sample_space; /* ALSA free samples space */ 1262 int samples; 1263 1264 sample_residues = fsi_get_current_fifo_samples(fsi, io); 1265 sample_space = io->buff_sample_capa - io->buff_sample_pos; 1266 1267 samples = min(sample_residues, sample_space); 1268 1269 return fsi_pio_transfer(fsi, io, 1270 fsi_pio_pop16, 1271 fsi_pio_pop32, 1272 samples); 1273 } 1274 1275 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) 1276 { 1277 int sample_residues; /* ALSA residue samples */ 1278 int sample_space; /* FSI fifo free samples space */ 1279 int samples; 1280 1281 sample_residues = io->buff_sample_capa - io->buff_sample_pos; 1282 sample_space = io->fifo_sample_capa - 1283 fsi_get_current_fifo_samples(fsi, io); 1284 1285 samples = min(sample_residues, sample_space); 1286 1287 return fsi_pio_transfer(fsi, io, 1288 fsi_pio_push16, 1289 fsi_pio_push32, 1290 samples); 1291 } 1292 1293 static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1294 int enable) 1295 { 1296 struct fsi_master *master = fsi_get_master(fsi); 1297 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1298 1299 if (enable) 1300 fsi_irq_enable(fsi, io); 1301 else 1302 fsi_irq_disable(fsi, io); 1303 1304 if (fsi_is_clk_master(fsi)) 1305 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1306 } 1307 1308 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) 1309 { 1310 /* 1311 * we can use 16bit stream mode 1312 * when "playback" and "16bit data" 1313 * and platform allows "stream mode" 1314 * see 1315 * fsi_pio_push16() 1316 */ 1317 if (fsi_is_enable_stream(fsi)) 1318 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1319 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1320 else 1321 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1322 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1323 return 0; 1324 } 1325 1326 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) 1327 { 1328 /* 1329 * always 24bit bus, package back when "capture" 1330 */ 1331 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1332 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1333 return 0; 1334 } 1335 1336 static struct fsi_stream_handler fsi_pio_push_handler = { 1337 .init = fsi_pio_push_init, 1338 .transfer = fsi_pio_push, 1339 .start_stop = fsi_pio_start_stop, 1340 }; 1341 1342 static struct fsi_stream_handler fsi_pio_pop_handler = { 1343 .init = fsi_pio_pop_init, 1344 .transfer = fsi_pio_pop, 1345 .start_stop = fsi_pio_start_stop, 1346 }; 1347 1348 static irqreturn_t fsi_interrupt(int irq, void *data) 1349 { 1350 struct fsi_master *master = data; 1351 u32 int_st = fsi_irq_get_status(master); 1352 1353 /* clear irq status */ 1354 fsi_master_mask_set(master, SOFT_RST, IR, 0); 1355 fsi_master_mask_set(master, SOFT_RST, IR, IR); 1356 1357 if (int_st & AB_IO(1, AO_SHIFT)) 1358 fsi_stream_transfer(&master->fsia.playback); 1359 if (int_st & AB_IO(1, BO_SHIFT)) 1360 fsi_stream_transfer(&master->fsib.playback); 1361 if (int_st & AB_IO(1, AI_SHIFT)) 1362 fsi_stream_transfer(&master->fsia.capture); 1363 if (int_st & AB_IO(1, BI_SHIFT)) 1364 fsi_stream_transfer(&master->fsib.capture); 1365 1366 fsi_count_fifo_err(&master->fsia); 1367 fsi_count_fifo_err(&master->fsib); 1368 1369 fsi_irq_clear_status(&master->fsia); 1370 fsi_irq_clear_status(&master->fsib); 1371 1372 return IRQ_HANDLED; 1373 } 1374 1375 /* 1376 * dma data transfer handler 1377 */ 1378 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) 1379 { 1380 struct snd_pcm_runtime *runtime = io->substream->runtime; 1381 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1382 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? 1383 DMA_TO_DEVICE : DMA_FROM_DEVICE; 1384 1385 /* 1386 * 24bit data : 24bit bus / package in back 1387 * 16bit data : 16bit bus / stream mode 1388 */ 1389 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1390 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1391 1392 io->dma = dma_map_single(dai->dev, runtime->dma_area, 1393 snd_pcm_lib_buffer_bytes(io->substream), dir); 1394 return 0; 1395 } 1396 1397 static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io) 1398 { 1399 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1400 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? 1401 DMA_TO_DEVICE : DMA_FROM_DEVICE; 1402 1403 dma_unmap_single(dai->dev, io->dma, 1404 snd_pcm_lib_buffer_bytes(io->substream), dir); 1405 return 0; 1406 } 1407 1408 static dma_addr_t fsi_dma_get_area(struct fsi_stream *io) 1409 { 1410 struct snd_pcm_runtime *runtime = io->substream->runtime; 1411 1412 return io->dma + samples_to_bytes(runtime, io->buff_sample_pos); 1413 } 1414 1415 static void fsi_dma_complete(void *data) 1416 { 1417 struct fsi_stream *io = (struct fsi_stream *)data; 1418 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1419 struct snd_pcm_runtime *runtime = io->substream->runtime; 1420 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1421 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? 1422 DMA_TO_DEVICE : DMA_FROM_DEVICE; 1423 1424 dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io), 1425 samples_to_bytes(runtime, io->period_samples), dir); 1426 1427 io->buff_sample_pos += io->period_samples; 1428 io->period_pos++; 1429 1430 if (io->period_pos >= runtime->periods) { 1431 io->period_pos = 0; 1432 io->buff_sample_pos = 0; 1433 } 1434 1435 fsi_count_fifo_err(fsi); 1436 fsi_stream_transfer(io); 1437 1438 snd_pcm_period_elapsed(io->substream); 1439 } 1440 1441 static void fsi_dma_do_work(struct work_struct *work) 1442 { 1443 struct fsi_stream *io = container_of(work, struct fsi_stream, work); 1444 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1445 struct snd_soc_dai *dai; 1446 struct dma_async_tx_descriptor *desc; 1447 struct snd_pcm_runtime *runtime; 1448 enum dma_data_direction dir; 1449 int is_play = fsi_stream_is_play(fsi, io); 1450 int len; 1451 dma_addr_t buf; 1452 1453 if (!fsi_stream_is_working(fsi, io)) 1454 return; 1455 1456 dai = fsi_get_dai(io->substream); 1457 runtime = io->substream->runtime; 1458 dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 1459 len = samples_to_bytes(runtime, io->period_samples); 1460 buf = fsi_dma_get_area(io); 1461 1462 dma_sync_single_for_device(dai->dev, buf, len, dir); 1463 1464 desc = dmaengine_prep_slave_single(io->chan, buf, len, dir, 1465 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1466 if (!desc) { 1467 dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n"); 1468 return; 1469 } 1470 1471 desc->callback = fsi_dma_complete; 1472 desc->callback_param = io; 1473 1474 if (dmaengine_submit(desc) < 0) { 1475 dev_err(dai->dev, "tx_submit() fail\n"); 1476 return; 1477 } 1478 1479 dma_async_issue_pending(io->chan); 1480 1481 /* 1482 * FIXME 1483 * 1484 * In DMAEngine case, codec and FSI cannot be started simultaneously 1485 * since FSI is using the scheduler work queue. 1486 * Therefore, in capture case, probably FSI FIFO will have got 1487 * overflow error in this point. 1488 * in that case, DMA cannot start transfer until error was cleared. 1489 */ 1490 if (!is_play) { 1491 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { 1492 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1493 fsi_reg_write(fsi, DIFF_ST, 0); 1494 } 1495 } 1496 } 1497 1498 static bool fsi_dma_filter(struct dma_chan *chan, void *param) 1499 { 1500 struct sh_dmae_slave *slave = param; 1501 1502 chan->private = slave; 1503 1504 return true; 1505 } 1506 1507 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) 1508 { 1509 schedule_work(&io->work); 1510 1511 return 0; 1512 } 1513 1514 static void fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1515 int start) 1516 { 1517 struct fsi_master *master = fsi_get_master(fsi); 1518 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1519 u32 enable = start ? DMA_ON : 0; 1520 1521 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); 1522 1523 dmaengine_terminate_all(io->chan); 1524 1525 if (fsi_is_clk_master(fsi)) 1526 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1527 } 1528 1529 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) 1530 { 1531 dma_cap_mask_t mask; 1532 1533 dma_cap_zero(mask); 1534 dma_cap_set(DMA_SLAVE, mask); 1535 1536 io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave); 1537 if (!io->chan) { 1538 1539 /* switch to PIO handler */ 1540 if (fsi_stream_is_play(fsi, io)) 1541 fsi->playback.handler = &fsi_pio_push_handler; 1542 else 1543 fsi->capture.handler = &fsi_pio_pop_handler; 1544 1545 dev_info(dev, "switch handler (dma => pio)\n"); 1546 1547 /* probe again */ 1548 return fsi_stream_probe(fsi, dev); 1549 } 1550 1551 INIT_WORK(&io->work, fsi_dma_do_work); 1552 1553 return 0; 1554 } 1555 1556 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) 1557 { 1558 cancel_work_sync(&io->work); 1559 1560 fsi_stream_stop(fsi, io); 1561 1562 if (io->chan) 1563 dma_release_channel(io->chan); 1564 1565 io->chan = NULL; 1566 return 0; 1567 } 1568 1569 static struct fsi_stream_handler fsi_dma_push_handler = { 1570 .init = fsi_dma_init, 1571 .quit = fsi_dma_quit, 1572 .probe = fsi_dma_probe, 1573 .transfer = fsi_dma_transfer, 1574 .remove = fsi_dma_remove, 1575 .start_stop = fsi_dma_push_start_stop, 1576 }; 1577 1578 /* 1579 * dai ops 1580 */ 1581 static void fsi_fifo_init(struct fsi_priv *fsi, 1582 struct fsi_stream *io, 1583 struct device *dev) 1584 { 1585 struct fsi_master *master = fsi_get_master(fsi); 1586 int is_play = fsi_stream_is_play(fsi, io); 1587 u32 shift, i; 1588 int frame_capa; 1589 1590 /* get on-chip RAM capacity */ 1591 shift = fsi_master_read(master, FIFO_SZ); 1592 shift >>= fsi_get_port_shift(fsi, io); 1593 shift &= FIFO_SZ_MASK; 1594 frame_capa = 256 << shift; 1595 dev_dbg(dev, "fifo = %d words\n", frame_capa); 1596 1597 /* 1598 * The maximum number of sample data varies depending 1599 * on the number of channels selected for the format. 1600 * 1601 * FIFOs are used in 4-channel units in 3-channel mode 1602 * and in 8-channel units in 5- to 7-channel mode 1603 * meaning that more FIFOs than the required size of DPRAM 1604 * are used. 1605 * 1606 * ex) if 256 words of DP-RAM is connected 1607 * 1 channel: 256 (256 x 1 = 256) 1608 * 2 channels: 128 (128 x 2 = 256) 1609 * 3 channels: 64 ( 64 x 3 = 192) 1610 * 4 channels: 64 ( 64 x 4 = 256) 1611 * 5 channels: 32 ( 32 x 5 = 160) 1612 * 6 channels: 32 ( 32 x 6 = 192) 1613 * 7 channels: 32 ( 32 x 7 = 224) 1614 * 8 channels: 32 ( 32 x 8 = 256) 1615 */ 1616 for (i = 1; i < fsi->chan_num; i <<= 1) 1617 frame_capa >>= 1; 1618 dev_dbg(dev, "%d channel %d store\n", 1619 fsi->chan_num, frame_capa); 1620 1621 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); 1622 1623 /* 1624 * set interrupt generation factor 1625 * clear FIFO 1626 */ 1627 if (is_play) { 1628 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); 1629 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); 1630 } else { 1631 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); 1632 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1633 } 1634 } 1635 1636 static int fsi_hw_startup(struct fsi_priv *fsi, 1637 struct fsi_stream *io, 1638 struct device *dev) 1639 { 1640 u32 flags = fsi_get_info_flags(fsi); 1641 u32 data = 0; 1642 1643 /* clock setting */ 1644 if (fsi_is_clk_master(fsi)) 1645 data = DIMD | DOMD; 1646 1647 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); 1648 1649 /* clock inversion (CKG2) */ 1650 data = 0; 1651 if (fsi->bit_clk_inv) 1652 data |= (1 << 0); 1653 if (fsi->lr_clk_inv) 1654 data |= (1 << 4); 1655 if (fsi_is_clk_master(fsi)) 1656 data <<= 8; 1657 /* FIXME 1658 * 1659 * SH_FSI_xxx_INV style will be removed 1660 */ 1661 if (SH_FSI_LRM_INV & flags) 1662 data |= 1 << 12; 1663 if (SH_FSI_BRM_INV & flags) 1664 data |= 1 << 8; 1665 if (SH_FSI_LRS_INV & flags) 1666 data |= 1 << 4; 1667 if (SH_FSI_BRS_INV & flags) 1668 data |= 1 << 0; 1669 1670 fsi_reg_write(fsi, CKG2, data); 1671 1672 /* spdif ? */ 1673 if (fsi_is_spdif(fsi)) { 1674 fsi_spdif_clk_ctrl(fsi, 1); 1675 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); 1676 } 1677 1678 /* 1679 * get bus settings 1680 */ 1681 data = 0; 1682 switch (io->sample_width) { 1683 case 2: 1684 data = BUSOP_GET(16, io->bus_option); 1685 break; 1686 case 4: 1687 data = BUSOP_GET(24, io->bus_option); 1688 break; 1689 } 1690 fsi_format_bus_setup(fsi, io, data, dev); 1691 1692 /* irq clear */ 1693 fsi_irq_disable(fsi, io); 1694 fsi_irq_clear_status(fsi); 1695 1696 /* fifo init */ 1697 fsi_fifo_init(fsi, io, dev); 1698 1699 /* start master clock */ 1700 if (fsi_is_clk_master(fsi)) 1701 return fsi_set_master_clk(dev, fsi, fsi->rate, 1); 1702 1703 return 0; 1704 } 1705 1706 static int fsi_hw_shutdown(struct fsi_priv *fsi, 1707 struct device *dev) 1708 { 1709 /* stop master clock */ 1710 if (fsi_is_clk_master(fsi)) 1711 return fsi_set_master_clk(dev, fsi, fsi->rate, 0); 1712 1713 return 0; 1714 } 1715 1716 static int fsi_dai_startup(struct snd_pcm_substream *substream, 1717 struct snd_soc_dai *dai) 1718 { 1719 struct fsi_priv *fsi = fsi_get_priv(substream); 1720 1721 fsi_clk_invalid(fsi); 1722 fsi->rate = 0; 1723 1724 return 0; 1725 } 1726 1727 static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 1728 struct snd_soc_dai *dai) 1729 { 1730 struct fsi_priv *fsi = fsi_get_priv(substream); 1731 1732 fsi_clk_invalid(fsi); 1733 fsi->rate = 0; 1734 } 1735 1736 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 1737 struct snd_soc_dai *dai) 1738 { 1739 struct fsi_priv *fsi = fsi_get_priv(substream); 1740 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1741 int ret = 0; 1742 1743 switch (cmd) { 1744 case SNDRV_PCM_TRIGGER_START: 1745 fsi_stream_init(fsi, io, substream); 1746 if (!ret) 1747 ret = fsi_hw_startup(fsi, io, dai->dev); 1748 if (!ret) 1749 ret = fsi_stream_transfer(io); 1750 if (!ret) 1751 fsi_stream_start(fsi, io); 1752 break; 1753 case SNDRV_PCM_TRIGGER_STOP: 1754 if (!ret) 1755 ret = fsi_hw_shutdown(fsi, dai->dev); 1756 fsi_stream_stop(fsi, io); 1757 fsi_stream_quit(fsi, io); 1758 break; 1759 } 1760 1761 return ret; 1762 } 1763 1764 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) 1765 { 1766 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1767 case SND_SOC_DAIFMT_I2S: 1768 fsi->fmt = CR_I2S; 1769 fsi->chan_num = 2; 1770 break; 1771 case SND_SOC_DAIFMT_LEFT_J: 1772 fsi->fmt = CR_PCM; 1773 fsi->chan_num = 2; 1774 break; 1775 default: 1776 return -EINVAL; 1777 } 1778 1779 return 0; 1780 } 1781 1782 static int fsi_set_fmt_spdif(struct fsi_priv *fsi) 1783 { 1784 struct fsi_master *master = fsi_get_master(fsi); 1785 1786 if (fsi_version(master) < 2) 1787 return -EINVAL; 1788 1789 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; 1790 fsi->chan_num = 2; 1791 1792 return 0; 1793 } 1794 1795 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1796 { 1797 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); 1798 set_rate_func set_rate = fsi_get_info_set_rate(fsi); 1799 int ret; 1800 1801 /* set master/slave audio interface */ 1802 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1803 case SND_SOC_DAIFMT_CBM_CFM: 1804 fsi->clk_master = 1; 1805 break; 1806 case SND_SOC_DAIFMT_CBS_CFS: 1807 break; 1808 default: 1809 return -EINVAL; 1810 } 1811 1812 /* set clock inversion */ 1813 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1814 case SND_SOC_DAIFMT_NB_IF: 1815 fsi->bit_clk_inv = 0; 1816 fsi->lr_clk_inv = 1; 1817 break; 1818 case SND_SOC_DAIFMT_IB_NF: 1819 fsi->bit_clk_inv = 1; 1820 fsi->lr_clk_inv = 0; 1821 break; 1822 case SND_SOC_DAIFMT_IB_IF: 1823 fsi->bit_clk_inv = 1; 1824 fsi->lr_clk_inv = 1; 1825 break; 1826 case SND_SOC_DAIFMT_NB_NF: 1827 default: 1828 fsi->bit_clk_inv = 0; 1829 fsi->lr_clk_inv = 0; 1830 break; 1831 } 1832 1833 if (fsi_is_clk_master(fsi)) { 1834 /* 1835 * CAUTION 1836 * 1837 * set_rate will be deleted 1838 */ 1839 if (set_rate) 1840 dev_warn(dai->dev, "set_rate will be removed soon\n"); 1841 1842 if (fsi->clk_cpg) 1843 fsi_clk_init(dai->dev, fsi, 0, 1, 1, 1844 fsi_clk_set_rate_cpg); 1845 else 1846 fsi_clk_init(dai->dev, fsi, 1, 1, 0, 1847 fsi_clk_set_rate_external); 1848 } 1849 1850 /* set format */ 1851 if (fsi_is_spdif(fsi)) 1852 ret = fsi_set_fmt_spdif(fsi); 1853 else 1854 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1855 1856 return ret; 1857 } 1858 1859 static int fsi_dai_hw_params(struct snd_pcm_substream *substream, 1860 struct snd_pcm_hw_params *params, 1861 struct snd_soc_dai *dai) 1862 { 1863 struct fsi_priv *fsi = fsi_get_priv(substream); 1864 1865 if (fsi_is_clk_master(fsi)) { 1866 fsi->rate = params_rate(params); 1867 fsi_clk_valid(fsi, fsi->rate); 1868 } 1869 1870 return 0; 1871 } 1872 1873 static const struct snd_soc_dai_ops fsi_dai_ops = { 1874 .startup = fsi_dai_startup, 1875 .shutdown = fsi_dai_shutdown, 1876 .trigger = fsi_dai_trigger, 1877 .set_fmt = fsi_dai_set_fmt, 1878 .hw_params = fsi_dai_hw_params, 1879 }; 1880 1881 /* 1882 * pcm ops 1883 */ 1884 1885 static struct snd_pcm_hardware fsi_pcm_hardware = { 1886 .info = SNDRV_PCM_INFO_INTERLEAVED | 1887 SNDRV_PCM_INFO_MMAP | 1888 SNDRV_PCM_INFO_MMAP_VALID | 1889 SNDRV_PCM_INFO_PAUSE, 1890 .formats = FSI_FMTS, 1891 .rates = FSI_RATES, 1892 .rate_min = 8000, 1893 .rate_max = 192000, 1894 .channels_min = 2, 1895 .channels_max = 2, 1896 .buffer_bytes_max = 64 * 1024, 1897 .period_bytes_min = 32, 1898 .period_bytes_max = 8192, 1899 .periods_min = 1, 1900 .periods_max = 32, 1901 .fifo_size = 256, 1902 }; 1903 1904 static int fsi_pcm_open(struct snd_pcm_substream *substream) 1905 { 1906 struct snd_pcm_runtime *runtime = substream->runtime; 1907 int ret = 0; 1908 1909 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 1910 1911 ret = snd_pcm_hw_constraint_integer(runtime, 1912 SNDRV_PCM_HW_PARAM_PERIODS); 1913 1914 return ret; 1915 } 1916 1917 static int fsi_hw_params(struct snd_pcm_substream *substream, 1918 struct snd_pcm_hw_params *hw_params) 1919 { 1920 return snd_pcm_lib_malloc_pages(substream, 1921 params_buffer_bytes(hw_params)); 1922 } 1923 1924 static int fsi_hw_free(struct snd_pcm_substream *substream) 1925 { 1926 return snd_pcm_lib_free_pages(substream); 1927 } 1928 1929 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) 1930 { 1931 struct fsi_priv *fsi = fsi_get_priv(substream); 1932 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1933 1934 return fsi_sample2frame(fsi, io->buff_sample_pos); 1935 } 1936 1937 static struct snd_pcm_ops fsi_pcm_ops = { 1938 .open = fsi_pcm_open, 1939 .ioctl = snd_pcm_lib_ioctl, 1940 .hw_params = fsi_hw_params, 1941 .hw_free = fsi_hw_free, 1942 .pointer = fsi_pointer, 1943 }; 1944 1945 /* 1946 * snd_soc_platform 1947 */ 1948 1949 #define PREALLOC_BUFFER (32 * 1024) 1950 #define PREALLOC_BUFFER_MAX (32 * 1024) 1951 1952 static void fsi_pcm_free(struct snd_pcm *pcm) 1953 { 1954 snd_pcm_lib_preallocate_free_for_all(pcm); 1955 } 1956 1957 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) 1958 { 1959 struct snd_pcm *pcm = rtd->pcm; 1960 1961 /* 1962 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel 1963 * in MMAP mode (i.e. aplay -M) 1964 */ 1965 return snd_pcm_lib_preallocate_pages_for_all( 1966 pcm, 1967 SNDRV_DMA_TYPE_CONTINUOUS, 1968 snd_dma_continuous_data(GFP_KERNEL), 1969 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1970 } 1971 1972 /* 1973 * alsa struct 1974 */ 1975 1976 static struct snd_soc_dai_driver fsi_soc_dai[] = { 1977 { 1978 .name = "fsia-dai", 1979 .playback = { 1980 .rates = FSI_RATES, 1981 .formats = FSI_FMTS, 1982 .channels_min = 2, 1983 .channels_max = 2, 1984 }, 1985 .capture = { 1986 .rates = FSI_RATES, 1987 .formats = FSI_FMTS, 1988 .channels_min = 2, 1989 .channels_max = 2, 1990 }, 1991 .ops = &fsi_dai_ops, 1992 }, 1993 { 1994 .name = "fsib-dai", 1995 .playback = { 1996 .rates = FSI_RATES, 1997 .formats = FSI_FMTS, 1998 .channels_min = 2, 1999 .channels_max = 2, 2000 }, 2001 .capture = { 2002 .rates = FSI_RATES, 2003 .formats = FSI_FMTS, 2004 .channels_min = 2, 2005 .channels_max = 2, 2006 }, 2007 .ops = &fsi_dai_ops, 2008 }, 2009 }; 2010 2011 static struct snd_soc_platform_driver fsi_soc_platform = { 2012 .ops = &fsi_pcm_ops, 2013 .pcm_new = fsi_pcm_new, 2014 .pcm_free = fsi_pcm_free, 2015 }; 2016 2017 /* 2018 * platform function 2019 */ 2020 static void fsi_port_info_init(struct fsi_priv *fsi, 2021 struct sh_fsi_port_info *info) 2022 { 2023 if (info->flags & SH_FSI_FMT_SPDIF) 2024 fsi->spdif = 1; 2025 2026 if (info->flags & SH_FSI_CLK_CPG) 2027 fsi->clk_cpg = 1; 2028 2029 if (info->flags & SH_FSI_ENABLE_STREAM_MODE) 2030 fsi->enable_stream = 1; 2031 } 2032 2033 static void fsi_handler_init(struct fsi_priv *fsi, 2034 struct sh_fsi_port_info *info) 2035 { 2036 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ 2037 fsi->playback.priv = fsi; 2038 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ 2039 fsi->capture.priv = fsi; 2040 2041 if (info->tx_id) { 2042 fsi->playback.slave.shdma_slave.slave_id = info->tx_id; 2043 fsi->playback.handler = &fsi_dma_push_handler; 2044 } 2045 } 2046 2047 static int fsi_probe(struct platform_device *pdev) 2048 { 2049 struct fsi_master *master; 2050 const struct platform_device_id *id_entry; 2051 struct sh_fsi_platform_info *info = pdev->dev.platform_data; 2052 struct sh_fsi_port_info nul_info, *pinfo; 2053 struct fsi_priv *fsi; 2054 struct resource *res; 2055 unsigned int irq; 2056 int ret; 2057 2058 nul_info.flags = 0; 2059 nul_info.tx_id = 0; 2060 nul_info.rx_id = 0; 2061 2062 id_entry = pdev->id_entry; 2063 if (!id_entry) { 2064 dev_err(&pdev->dev, "unknown fsi device\n"); 2065 return -ENODEV; 2066 } 2067 2068 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2069 irq = platform_get_irq(pdev, 0); 2070 if (!res || (int)irq <= 0) { 2071 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 2072 return -ENODEV; 2073 } 2074 2075 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 2076 if (!master) { 2077 dev_err(&pdev->dev, "Could not allocate master\n"); 2078 return -ENOMEM; 2079 } 2080 2081 master->base = devm_ioremap_nocache(&pdev->dev, 2082 res->start, resource_size(res)); 2083 if (!master->base) { 2084 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 2085 return -ENXIO; 2086 } 2087 2088 /* master setting */ 2089 master->irq = irq; 2090 master->core = (struct fsi_core *)id_entry->driver_data; 2091 spin_lock_init(&master->lock); 2092 2093 /* FSI A setting */ 2094 pinfo = (info) ? &info->port_a : &nul_info; 2095 fsi = &master->fsia; 2096 fsi->base = master->base; 2097 fsi->master = master; 2098 fsi->info = pinfo; 2099 fsi_port_info_init(fsi, pinfo); 2100 fsi_handler_init(fsi, pinfo); 2101 ret = fsi_stream_probe(fsi, &pdev->dev); 2102 if (ret < 0) { 2103 dev_err(&pdev->dev, "FSIA stream probe failed\n"); 2104 return ret; 2105 } 2106 2107 /* FSI B setting */ 2108 pinfo = (info) ? &info->port_b : &nul_info; 2109 fsi = &master->fsib; 2110 fsi->base = master->base + 0x40; 2111 fsi->master = master; 2112 fsi->info = pinfo; 2113 fsi_port_info_init(fsi, pinfo); 2114 fsi_handler_init(fsi, pinfo); 2115 ret = fsi_stream_probe(fsi, &pdev->dev); 2116 if (ret < 0) { 2117 dev_err(&pdev->dev, "FSIB stream probe failed\n"); 2118 goto exit_fsia; 2119 } 2120 2121 pm_runtime_enable(&pdev->dev); 2122 dev_set_drvdata(&pdev->dev, master); 2123 2124 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, 2125 id_entry->name, master); 2126 if (ret) { 2127 dev_err(&pdev->dev, "irq request err\n"); 2128 goto exit_fsib; 2129 } 2130 2131 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); 2132 if (ret < 0) { 2133 dev_err(&pdev->dev, "cannot snd soc register\n"); 2134 goto exit_fsib; 2135 } 2136 2137 ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai, 2138 ARRAY_SIZE(fsi_soc_dai)); 2139 if (ret < 0) { 2140 dev_err(&pdev->dev, "cannot snd dai register\n"); 2141 goto exit_snd_soc; 2142 } 2143 2144 return ret; 2145 2146 exit_snd_soc: 2147 snd_soc_unregister_platform(&pdev->dev); 2148 exit_fsib: 2149 pm_runtime_disable(&pdev->dev); 2150 fsi_stream_remove(&master->fsib); 2151 exit_fsia: 2152 fsi_stream_remove(&master->fsia); 2153 2154 return ret; 2155 } 2156 2157 static int fsi_remove(struct platform_device *pdev) 2158 { 2159 struct fsi_master *master; 2160 2161 master = dev_get_drvdata(&pdev->dev); 2162 2163 pm_runtime_disable(&pdev->dev); 2164 2165 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai)); 2166 snd_soc_unregister_platform(&pdev->dev); 2167 2168 fsi_stream_remove(&master->fsia); 2169 fsi_stream_remove(&master->fsib); 2170 2171 return 0; 2172 } 2173 2174 static void __fsi_suspend(struct fsi_priv *fsi, 2175 struct fsi_stream *io, 2176 struct device *dev) 2177 { 2178 if (!fsi_stream_is_working(fsi, io)) 2179 return; 2180 2181 fsi_stream_stop(fsi, io); 2182 fsi_hw_shutdown(fsi, dev); 2183 } 2184 2185 static void __fsi_resume(struct fsi_priv *fsi, 2186 struct fsi_stream *io, 2187 struct device *dev) 2188 { 2189 if (!fsi_stream_is_working(fsi, io)) 2190 return; 2191 2192 fsi_hw_startup(fsi, io, dev); 2193 fsi_stream_start(fsi, io); 2194 } 2195 2196 static int fsi_suspend(struct device *dev) 2197 { 2198 struct fsi_master *master = dev_get_drvdata(dev); 2199 struct fsi_priv *fsia = &master->fsia; 2200 struct fsi_priv *fsib = &master->fsib; 2201 2202 __fsi_suspend(fsia, &fsia->playback, dev); 2203 __fsi_suspend(fsia, &fsia->capture, dev); 2204 2205 __fsi_suspend(fsib, &fsib->playback, dev); 2206 __fsi_suspend(fsib, &fsib->capture, dev); 2207 2208 return 0; 2209 } 2210 2211 static int fsi_resume(struct device *dev) 2212 { 2213 struct fsi_master *master = dev_get_drvdata(dev); 2214 struct fsi_priv *fsia = &master->fsia; 2215 struct fsi_priv *fsib = &master->fsib; 2216 2217 __fsi_resume(fsia, &fsia->playback, dev); 2218 __fsi_resume(fsia, &fsia->capture, dev); 2219 2220 __fsi_resume(fsib, &fsib->playback, dev); 2221 __fsi_resume(fsib, &fsib->capture, dev); 2222 2223 return 0; 2224 } 2225 2226 static struct dev_pm_ops fsi_pm_ops = { 2227 .suspend = fsi_suspend, 2228 .resume = fsi_resume, 2229 }; 2230 2231 static struct fsi_core fsi1_core = { 2232 .ver = 1, 2233 2234 /* Interrupt */ 2235 .int_st = INT_ST, 2236 .iemsk = IEMSK, 2237 .imsk = IMSK, 2238 }; 2239 2240 static struct fsi_core fsi2_core = { 2241 .ver = 2, 2242 2243 /* Interrupt */ 2244 .int_st = CPU_INT_ST, 2245 .iemsk = CPU_IEMSK, 2246 .imsk = CPU_IMSK, 2247 .a_mclk = A_MST_CTLR, 2248 .b_mclk = B_MST_CTLR, 2249 }; 2250 2251 static struct platform_device_id fsi_id_table[] = { 2252 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, 2253 { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, 2254 {}, 2255 }; 2256 MODULE_DEVICE_TABLE(platform, fsi_id_table); 2257 2258 static struct platform_driver fsi_driver = { 2259 .driver = { 2260 .name = "fsi-pcm-audio", 2261 .pm = &fsi_pm_ops, 2262 }, 2263 .probe = fsi_probe, 2264 .remove = fsi_remove, 2265 .id_table = fsi_id_table, 2266 }; 2267 2268 module_platform_driver(fsi_driver); 2269 2270 MODULE_LICENSE("GPL"); 2271 MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); 2272 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 2273 MODULE_ALIAS("platform:fsi-pcm-audio"); 2274