1 /* 2 * Fifo-attached Serial Interface (FSI) support for SH7724 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on ssi.c 8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/scatterlist.h> 22 #include <linux/sh_dma.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/workqueue.h> 26 #include <sound/soc.h> 27 #include <sound/pcm_params.h> 28 #include <sound/sh_fsi.h> 29 30 /* PortA/PortB register */ 31 #define REG_DO_FMT 0x0000 32 #define REG_DOFF_CTL 0x0004 33 #define REG_DOFF_ST 0x0008 34 #define REG_DI_FMT 0x000C 35 #define REG_DIFF_CTL 0x0010 36 #define REG_DIFF_ST 0x0014 37 #define REG_CKG1 0x0018 38 #define REG_CKG2 0x001C 39 #define REG_DIDT 0x0020 40 #define REG_DODT 0x0024 41 #define REG_MUTE_ST 0x0028 42 #define REG_OUT_DMAC 0x002C 43 #define REG_OUT_SEL 0x0030 44 #define REG_IN_DMAC 0x0038 45 46 /* master register */ 47 #define MST_CLK_RST 0x0210 48 #define MST_SOFT_RST 0x0214 49 #define MST_FIFO_SZ 0x0218 50 51 /* core register (depend on FSI version) */ 52 #define A_MST_CTLR 0x0180 53 #define B_MST_CTLR 0x01A0 54 #define CPU_INT_ST 0x01F4 55 #define CPU_IEMSK 0x01F8 56 #define CPU_IMSK 0x01FC 57 #define INT_ST 0x0200 58 #define IEMSK 0x0204 59 #define IMSK 0x0208 60 61 /* DO_FMT */ 62 /* DI_FMT */ 63 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */ 64 #define CR_BWS_24 (0x0 << 20) /* FSI2 */ 65 #define CR_BWS_16 (0x1 << 20) /* FSI2 */ 66 #define CR_BWS_20 (0x2 << 20) /* FSI2 */ 67 68 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ 69 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ 70 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ 71 72 #define CR_MONO (0x0 << 4) 73 #define CR_MONO_D (0x1 << 4) 74 #define CR_PCM (0x2 << 4) 75 #define CR_I2S (0x3 << 4) 76 #define CR_TDM (0x4 << 4) 77 #define CR_TDM_D (0x5 << 4) 78 79 /* OUT_DMAC */ 80 /* IN_DMAC */ 81 #define VDMD_MASK (0x3 << 4) 82 #define VDMD_FRONT (0x0 << 4) /* Package in front */ 83 #define VDMD_BACK (0x1 << 4) /* Package in back */ 84 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ 85 86 #define DMA_ON (0x1 << 0) 87 88 /* DOFF_CTL */ 89 /* DIFF_CTL */ 90 #define IRQ_HALF 0x00100000 91 #define FIFO_CLR 0x00000001 92 93 /* DOFF_ST */ 94 #define ERR_OVER 0x00000010 95 #define ERR_UNDER 0x00000001 96 #define ST_ERR (ERR_OVER | ERR_UNDER) 97 98 /* CKG1 */ 99 #define ACKMD_MASK 0x00007000 100 #define BPFMD_MASK 0x00000700 101 #define DIMD (1 << 4) 102 #define DOMD (1 << 0) 103 104 /* A/B MST_CTLR */ 105 #define BP (1 << 4) /* Fix the signal of Biphase output */ 106 #define SE (1 << 0) /* Fix the master clock */ 107 108 /* CLK_RST */ 109 #define CRB (1 << 4) 110 #define CRA (1 << 0) 111 112 /* IO SHIFT / MACRO */ 113 #define BI_SHIFT 12 114 #define BO_SHIFT 8 115 #define AI_SHIFT 4 116 #define AO_SHIFT 0 117 #define AB_IO(param, shift) (param << shift) 118 119 /* SOFT_RST */ 120 #define PBSR (1 << 12) /* Port B Software Reset */ 121 #define PASR (1 << 8) /* Port A Software Reset */ 122 #define IR (1 << 4) /* Interrupt Reset */ 123 #define FSISR (1 << 0) /* Software Reset */ 124 125 /* OUT_SEL (FSI2) */ 126 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ 127 /* 1: Biphase and serial */ 128 129 /* FIFO_SZ */ 130 #define FIFO_SZ_MASK 0x7 131 132 #define FSI_RATES SNDRV_PCM_RATE_8000_96000 133 134 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 135 136 /* 137 * bus options 138 * 139 * 0x000000BA 140 * 141 * A : sample widtht 16bit setting 142 * B : sample widtht 24bit setting 143 */ 144 145 #define SHIFT_16DATA 0 146 #define SHIFT_24DATA 4 147 148 #define PACKAGE_24BITBUS_BACK 0 149 #define PACKAGE_24BITBUS_FRONT 1 150 #define PACKAGE_16BITBUS_STREAM 2 151 152 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) 153 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) 154 155 /* 156 * FSI driver use below type name for variable 157 * 158 * xxx_num : number of data 159 * xxx_pos : position of data 160 * xxx_capa : capacity of data 161 */ 162 163 /* 164 * period/frame/sample image 165 * 166 * ex) PCM (2ch) 167 * 168 * period pos period pos 169 * [n] [n + 1] 170 * |<-------------------- period--------------------->| 171 * ==|============================================ ... =|== 172 * | | 173 * ||<----- frame ----->|<------ frame ----->| ... | 174 * |+--------------------+--------------------+- ... | 175 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | 176 * |+--------------------+--------------------+- ... | 177 * ==|============================================ ... =|== 178 */ 179 180 /* 181 * FSI FIFO image 182 * 183 * | | 184 * | | 185 * | [ sample ] | 186 * | [ sample ] | 187 * | [ sample ] | 188 * | [ sample ] | 189 * --> go to codecs 190 */ 191 192 /* 193 * FSI clock 194 * 195 * FSIxCLK [CPG] (ick) -------> | 196 * |-> FSI_DIV (div)-> FSI2 197 * FSIxCK [external] (xck) ---> | 198 */ 199 200 /* 201 * struct 202 */ 203 204 struct fsi_stream_handler; 205 struct fsi_stream { 206 207 /* 208 * these are initialized by fsi_stream_init() 209 */ 210 struct snd_pcm_substream *substream; 211 int fifo_sample_capa; /* sample capacity of FSI FIFO */ 212 int buff_sample_capa; /* sample capacity of ALSA buffer */ 213 int buff_sample_pos; /* sample position of ALSA buffer */ 214 int period_samples; /* sample number / 1 period */ 215 int period_pos; /* current period position */ 216 int sample_width; /* sample width */ 217 int uerr_num; 218 int oerr_num; 219 220 /* 221 * bus options 222 */ 223 u32 bus_option; 224 225 /* 226 * thse are initialized by fsi_handler_init() 227 */ 228 struct fsi_stream_handler *handler; 229 struct fsi_priv *priv; 230 231 /* 232 * these are for DMAEngine 233 */ 234 struct dma_chan *chan; 235 int dma_id; 236 }; 237 238 struct fsi_clk { 239 /* see [FSI clock] */ 240 struct clk *own; 241 struct clk *xck; 242 struct clk *ick; 243 struct clk *div; 244 int (*set_rate)(struct device *dev, 245 struct fsi_priv *fsi); 246 247 unsigned long rate; 248 unsigned int count; 249 }; 250 251 struct fsi_priv { 252 void __iomem *base; 253 phys_addr_t phys; 254 struct fsi_master *master; 255 256 struct fsi_stream playback; 257 struct fsi_stream capture; 258 259 struct fsi_clk clock; 260 261 u32 fmt; 262 263 int chan_num:16; 264 unsigned int clk_master:1; 265 unsigned int clk_cpg:1; 266 unsigned int spdif:1; 267 unsigned int enable_stream:1; 268 unsigned int bit_clk_inv:1; 269 unsigned int lr_clk_inv:1; 270 }; 271 272 struct fsi_stream_handler { 273 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); 274 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); 275 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); 276 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); 277 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); 278 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, 279 int enable); 280 }; 281 #define fsi_stream_handler_call(io, func, args...) \ 282 (!(io) ? -ENODEV : \ 283 !((io)->handler->func) ? 0 : \ 284 (io)->handler->func(args)) 285 286 struct fsi_core { 287 int ver; 288 289 u32 int_st; 290 u32 iemsk; 291 u32 imsk; 292 u32 a_mclk; 293 u32 b_mclk; 294 }; 295 296 struct fsi_master { 297 void __iomem *base; 298 struct fsi_priv fsia; 299 struct fsi_priv fsib; 300 const struct fsi_core *core; 301 spinlock_t lock; 302 }; 303 304 static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io); 305 306 /* 307 * basic read write function 308 */ 309 310 static void __fsi_reg_write(u32 __iomem *reg, u32 data) 311 { 312 /* valid data area is 24bit */ 313 data &= 0x00ffffff; 314 315 __raw_writel(data, reg); 316 } 317 318 static u32 __fsi_reg_read(u32 __iomem *reg) 319 { 320 return __raw_readl(reg); 321 } 322 323 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) 324 { 325 u32 val = __fsi_reg_read(reg); 326 327 val &= ~mask; 328 val |= data & mask; 329 330 __fsi_reg_write(reg, val); 331 } 332 333 #define fsi_reg_write(p, r, d)\ 334 __fsi_reg_write((p->base + REG_##r), d) 335 336 #define fsi_reg_read(p, r)\ 337 __fsi_reg_read((p->base + REG_##r)) 338 339 #define fsi_reg_mask_set(p, r, m, d)\ 340 __fsi_reg_mask_set((p->base + REG_##r), m, d) 341 342 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) 343 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) 344 static u32 _fsi_master_read(struct fsi_master *master, u32 reg) 345 { 346 u32 ret; 347 unsigned long flags; 348 349 spin_lock_irqsave(&master->lock, flags); 350 ret = __fsi_reg_read(master->base + reg); 351 spin_unlock_irqrestore(&master->lock, flags); 352 353 return ret; 354 } 355 356 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) 357 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) 358 static void _fsi_master_mask_set(struct fsi_master *master, 359 u32 reg, u32 mask, u32 data) 360 { 361 unsigned long flags; 362 363 spin_lock_irqsave(&master->lock, flags); 364 __fsi_reg_mask_set(master->base + reg, mask, data); 365 spin_unlock_irqrestore(&master->lock, flags); 366 } 367 368 /* 369 * basic function 370 */ 371 static int fsi_version(struct fsi_master *master) 372 { 373 return master->core->ver; 374 } 375 376 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) 377 { 378 return fsi->master; 379 } 380 381 static int fsi_is_clk_master(struct fsi_priv *fsi) 382 { 383 return fsi->clk_master; 384 } 385 386 static int fsi_is_port_a(struct fsi_priv *fsi) 387 { 388 return fsi->master->base == fsi->base; 389 } 390 391 static int fsi_is_spdif(struct fsi_priv *fsi) 392 { 393 return fsi->spdif; 394 } 395 396 static int fsi_is_enable_stream(struct fsi_priv *fsi) 397 { 398 return fsi->enable_stream; 399 } 400 401 static int fsi_is_play(struct snd_pcm_substream *substream) 402 { 403 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 404 } 405 406 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) 407 { 408 struct snd_soc_pcm_runtime *rtd = substream->private_data; 409 410 return rtd->cpu_dai; 411 } 412 413 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) 414 { 415 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); 416 417 if (dai->id == 0) 418 return &master->fsia; 419 else 420 return &master->fsib; 421 } 422 423 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) 424 { 425 return fsi_get_priv_frm_dai(fsi_get_dai(substream)); 426 } 427 428 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) 429 { 430 int is_play = fsi_stream_is_play(fsi, io); 431 int is_porta = fsi_is_port_a(fsi); 432 u32 shift; 433 434 if (is_porta) 435 shift = is_play ? AO_SHIFT : AI_SHIFT; 436 else 437 shift = is_play ? BO_SHIFT : BI_SHIFT; 438 439 return shift; 440 } 441 442 static int fsi_frame2sample(struct fsi_priv *fsi, int frames) 443 { 444 return frames * fsi->chan_num; 445 } 446 447 static int fsi_sample2frame(struct fsi_priv *fsi, int samples) 448 { 449 return samples / fsi->chan_num; 450 } 451 452 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, 453 struct fsi_stream *io) 454 { 455 int is_play = fsi_stream_is_play(fsi, io); 456 u32 status; 457 int frames; 458 459 status = is_play ? 460 fsi_reg_read(fsi, DOFF_ST) : 461 fsi_reg_read(fsi, DIFF_ST); 462 463 frames = 0x1ff & (status >> 8); 464 465 return fsi_frame2sample(fsi, frames); 466 } 467 468 static void fsi_count_fifo_err(struct fsi_priv *fsi) 469 { 470 u32 ostatus = fsi_reg_read(fsi, DOFF_ST); 471 u32 istatus = fsi_reg_read(fsi, DIFF_ST); 472 473 if (ostatus & ERR_OVER) 474 fsi->playback.oerr_num++; 475 476 if (ostatus & ERR_UNDER) 477 fsi->playback.uerr_num++; 478 479 if (istatus & ERR_OVER) 480 fsi->capture.oerr_num++; 481 482 if (istatus & ERR_UNDER) 483 fsi->capture.uerr_num++; 484 485 fsi_reg_write(fsi, DOFF_ST, 0); 486 fsi_reg_write(fsi, DIFF_ST, 0); 487 } 488 489 /* 490 * fsi_stream_xx() function 491 */ 492 static inline int fsi_stream_is_play(struct fsi_priv *fsi, 493 struct fsi_stream *io) 494 { 495 return &fsi->playback == io; 496 } 497 498 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, 499 struct snd_pcm_substream *substream) 500 { 501 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; 502 } 503 504 static int fsi_stream_is_working(struct fsi_priv *fsi, 505 struct fsi_stream *io) 506 { 507 struct fsi_master *master = fsi_get_master(fsi); 508 unsigned long flags; 509 int ret; 510 511 spin_lock_irqsave(&master->lock, flags); 512 ret = !!(io->substream && io->substream->runtime); 513 spin_unlock_irqrestore(&master->lock, flags); 514 515 return ret; 516 } 517 518 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) 519 { 520 return io->priv; 521 } 522 523 static void fsi_stream_init(struct fsi_priv *fsi, 524 struct fsi_stream *io, 525 struct snd_pcm_substream *substream) 526 { 527 struct snd_pcm_runtime *runtime = substream->runtime; 528 struct fsi_master *master = fsi_get_master(fsi); 529 unsigned long flags; 530 531 spin_lock_irqsave(&master->lock, flags); 532 io->substream = substream; 533 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); 534 io->buff_sample_pos = 0; 535 io->period_samples = fsi_frame2sample(fsi, runtime->period_size); 536 io->period_pos = 0; 537 io->sample_width = samples_to_bytes(runtime, 1); 538 io->bus_option = 0; 539 io->oerr_num = -1; /* ignore 1st err */ 540 io->uerr_num = -1; /* ignore 1st err */ 541 fsi_stream_handler_call(io, init, fsi, io); 542 spin_unlock_irqrestore(&master->lock, flags); 543 } 544 545 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) 546 { 547 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 548 struct fsi_master *master = fsi_get_master(fsi); 549 unsigned long flags; 550 551 spin_lock_irqsave(&master->lock, flags); 552 553 if (io->oerr_num > 0) 554 dev_err(dai->dev, "over_run = %d\n", io->oerr_num); 555 556 if (io->uerr_num > 0) 557 dev_err(dai->dev, "under_run = %d\n", io->uerr_num); 558 559 fsi_stream_handler_call(io, quit, fsi, io); 560 io->substream = NULL; 561 io->buff_sample_capa = 0; 562 io->buff_sample_pos = 0; 563 io->period_samples = 0; 564 io->period_pos = 0; 565 io->sample_width = 0; 566 io->bus_option = 0; 567 io->oerr_num = 0; 568 io->uerr_num = 0; 569 spin_unlock_irqrestore(&master->lock, flags); 570 } 571 572 static int fsi_stream_transfer(struct fsi_stream *io) 573 { 574 struct fsi_priv *fsi = fsi_stream_to_priv(io); 575 if (!fsi) 576 return -EIO; 577 578 return fsi_stream_handler_call(io, transfer, fsi, io); 579 } 580 581 #define fsi_stream_start(fsi, io)\ 582 fsi_stream_handler_call(io, start_stop, fsi, io, 1) 583 584 #define fsi_stream_stop(fsi, io)\ 585 fsi_stream_handler_call(io, start_stop, fsi, io, 0) 586 587 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) 588 { 589 struct fsi_stream *io; 590 int ret1, ret2; 591 592 io = &fsi->playback; 593 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); 594 595 io = &fsi->capture; 596 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); 597 598 if (ret1 < 0) 599 return ret1; 600 if (ret2 < 0) 601 return ret2; 602 603 return 0; 604 } 605 606 static int fsi_stream_remove(struct fsi_priv *fsi) 607 { 608 struct fsi_stream *io; 609 int ret1, ret2; 610 611 io = &fsi->playback; 612 ret1 = fsi_stream_handler_call(io, remove, fsi, io); 613 614 io = &fsi->capture; 615 ret2 = fsi_stream_handler_call(io, remove, fsi, io); 616 617 if (ret1 < 0) 618 return ret1; 619 if (ret2 < 0) 620 return ret2; 621 622 return 0; 623 } 624 625 /* 626 * format/bus/dma setting 627 */ 628 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, 629 u32 bus, struct device *dev) 630 { 631 struct fsi_master *master = fsi_get_master(fsi); 632 int is_play = fsi_stream_is_play(fsi, io); 633 u32 fmt = fsi->fmt; 634 635 if (fsi_version(master) >= 2) { 636 u32 dma = 0; 637 638 /* 639 * FSI2 needs DMA/Bus setting 640 */ 641 switch (bus) { 642 case PACKAGE_24BITBUS_FRONT: 643 fmt |= CR_BWS_24; 644 dma |= VDMD_FRONT; 645 dev_dbg(dev, "24bit bus / package in front\n"); 646 break; 647 case PACKAGE_16BITBUS_STREAM: 648 fmt |= CR_BWS_16; 649 dma |= VDMD_STREAM; 650 dev_dbg(dev, "16bit bus / stream mode\n"); 651 break; 652 case PACKAGE_24BITBUS_BACK: 653 default: 654 fmt |= CR_BWS_24; 655 dma |= VDMD_BACK; 656 dev_dbg(dev, "24bit bus / package in back\n"); 657 break; 658 } 659 660 if (is_play) 661 fsi_reg_write(fsi, OUT_DMAC, dma); 662 else 663 fsi_reg_write(fsi, IN_DMAC, dma); 664 } 665 666 if (is_play) 667 fsi_reg_write(fsi, DO_FMT, fmt); 668 else 669 fsi_reg_write(fsi, DI_FMT, fmt); 670 } 671 672 /* 673 * irq function 674 */ 675 676 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) 677 { 678 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 679 struct fsi_master *master = fsi_get_master(fsi); 680 681 fsi_core_mask_set(master, imsk, data, data); 682 fsi_core_mask_set(master, iemsk, data, data); 683 } 684 685 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) 686 { 687 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 688 struct fsi_master *master = fsi_get_master(fsi); 689 690 fsi_core_mask_set(master, imsk, data, 0); 691 fsi_core_mask_set(master, iemsk, data, 0); 692 } 693 694 static u32 fsi_irq_get_status(struct fsi_master *master) 695 { 696 return fsi_core_read(master, int_st); 697 } 698 699 static void fsi_irq_clear_status(struct fsi_priv *fsi) 700 { 701 u32 data = 0; 702 struct fsi_master *master = fsi_get_master(fsi); 703 704 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); 705 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); 706 707 /* clear interrupt factor */ 708 fsi_core_mask_set(master, int_st, data, 0); 709 } 710 711 /* 712 * SPDIF master clock function 713 * 714 * These functions are used later FSI2 715 */ 716 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) 717 { 718 struct fsi_master *master = fsi_get_master(fsi); 719 u32 mask, val; 720 721 mask = BP | SE; 722 val = enable ? mask : 0; 723 724 fsi_is_port_a(fsi) ? 725 fsi_core_mask_set(master, a_mclk, mask, val) : 726 fsi_core_mask_set(master, b_mclk, mask, val); 727 } 728 729 /* 730 * clock function 731 */ 732 static int fsi_clk_init(struct device *dev, 733 struct fsi_priv *fsi, 734 int xck, 735 int ick, 736 int div, 737 int (*set_rate)(struct device *dev, 738 struct fsi_priv *fsi)) 739 { 740 struct fsi_clk *clock = &fsi->clock; 741 int is_porta = fsi_is_port_a(fsi); 742 743 clock->xck = NULL; 744 clock->ick = NULL; 745 clock->div = NULL; 746 clock->rate = 0; 747 clock->count = 0; 748 clock->set_rate = set_rate; 749 750 clock->own = devm_clk_get(dev, NULL); 751 if (IS_ERR(clock->own)) 752 return -EINVAL; 753 754 /* external clock */ 755 if (xck) { 756 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); 757 if (IS_ERR(clock->xck)) { 758 dev_err(dev, "can't get xck clock\n"); 759 return -EINVAL; 760 } 761 if (clock->xck == clock->own) { 762 dev_err(dev, "cpu doesn't support xck clock\n"); 763 return -EINVAL; 764 } 765 } 766 767 /* FSIACLK/FSIBCLK */ 768 if (ick) { 769 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); 770 if (IS_ERR(clock->ick)) { 771 dev_err(dev, "can't get ick clock\n"); 772 return -EINVAL; 773 } 774 if (clock->ick == clock->own) { 775 dev_err(dev, "cpu doesn't support ick clock\n"); 776 return -EINVAL; 777 } 778 } 779 780 /* FSI-DIV */ 781 if (div) { 782 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); 783 if (IS_ERR(clock->div)) { 784 dev_err(dev, "can't get div clock\n"); 785 return -EINVAL; 786 } 787 if (clock->div == clock->own) { 788 dev_err(dev, "cpu doens't support div clock\n"); 789 return -EINVAL; 790 } 791 } 792 793 return 0; 794 } 795 796 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) 797 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) 798 { 799 fsi->clock.rate = rate; 800 } 801 802 static int fsi_clk_is_valid(struct fsi_priv *fsi) 803 { 804 return fsi->clock.set_rate && 805 fsi->clock.rate; 806 } 807 808 static int fsi_clk_enable(struct device *dev, 809 struct fsi_priv *fsi) 810 { 811 struct fsi_clk *clock = &fsi->clock; 812 int ret = -EINVAL; 813 814 if (!fsi_clk_is_valid(fsi)) 815 return ret; 816 817 if (0 == clock->count) { 818 ret = clock->set_rate(dev, fsi); 819 if (ret < 0) { 820 fsi_clk_invalid(fsi); 821 return ret; 822 } 823 824 clk_enable(clock->xck); 825 clk_enable(clock->ick); 826 clk_enable(clock->div); 827 828 clock->count++; 829 } 830 831 return ret; 832 } 833 834 static int fsi_clk_disable(struct device *dev, 835 struct fsi_priv *fsi) 836 { 837 struct fsi_clk *clock = &fsi->clock; 838 839 if (!fsi_clk_is_valid(fsi)) 840 return -EINVAL; 841 842 if (1 == clock->count--) { 843 clk_disable(clock->xck); 844 clk_disable(clock->ick); 845 clk_disable(clock->div); 846 } 847 848 return 0; 849 } 850 851 static int fsi_clk_set_ackbpf(struct device *dev, 852 struct fsi_priv *fsi, 853 int ackmd, int bpfmd) 854 { 855 u32 data = 0; 856 857 /* check ackmd/bpfmd relationship */ 858 if (bpfmd > ackmd) { 859 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); 860 return -EINVAL; 861 } 862 863 /* ACKMD */ 864 switch (ackmd) { 865 case 512: 866 data |= (0x0 << 12); 867 break; 868 case 256: 869 data |= (0x1 << 12); 870 break; 871 case 128: 872 data |= (0x2 << 12); 873 break; 874 case 64: 875 data |= (0x3 << 12); 876 break; 877 case 32: 878 data |= (0x4 << 12); 879 break; 880 default: 881 dev_err(dev, "unsupported ackmd (%d)\n", ackmd); 882 return -EINVAL; 883 } 884 885 /* BPFMD */ 886 switch (bpfmd) { 887 case 32: 888 data |= (0x0 << 8); 889 break; 890 case 64: 891 data |= (0x1 << 8); 892 break; 893 case 128: 894 data |= (0x2 << 8); 895 break; 896 case 256: 897 data |= (0x3 << 8); 898 break; 899 case 512: 900 data |= (0x4 << 8); 901 break; 902 case 16: 903 data |= (0x7 << 8); 904 break; 905 default: 906 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); 907 return -EINVAL; 908 } 909 910 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); 911 912 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 913 udelay(10); 914 915 return 0; 916 } 917 918 static int fsi_clk_set_rate_external(struct device *dev, 919 struct fsi_priv *fsi) 920 { 921 struct clk *xck = fsi->clock.xck; 922 struct clk *ick = fsi->clock.ick; 923 unsigned long rate = fsi->clock.rate; 924 unsigned long xrate; 925 int ackmd, bpfmd; 926 int ret = 0; 927 928 /* check clock rate */ 929 xrate = clk_get_rate(xck); 930 if (xrate % rate) { 931 dev_err(dev, "unsupported clock rate\n"); 932 return -EINVAL; 933 } 934 935 clk_set_parent(ick, xck); 936 clk_set_rate(ick, xrate); 937 938 bpfmd = fsi->chan_num * 32; 939 ackmd = xrate / rate; 940 941 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); 942 943 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 944 if (ret < 0) 945 dev_err(dev, "%s failed", __func__); 946 947 return ret; 948 } 949 950 static int fsi_clk_set_rate_cpg(struct device *dev, 951 struct fsi_priv *fsi) 952 { 953 struct clk *ick = fsi->clock.ick; 954 struct clk *div = fsi->clock.div; 955 unsigned long rate = fsi->clock.rate; 956 unsigned long target = 0; /* 12288000 or 11289600 */ 957 unsigned long actual, cout; 958 unsigned long diff, min; 959 unsigned long best_cout, best_act; 960 int adj; 961 int ackmd, bpfmd; 962 int ret = -EINVAL; 963 964 if (!(12288000 % rate)) 965 target = 12288000; 966 if (!(11289600 % rate)) 967 target = 11289600; 968 if (!target) { 969 dev_err(dev, "unsupported rate\n"); 970 return ret; 971 } 972 973 bpfmd = fsi->chan_num * 32; 974 ackmd = target / rate; 975 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 976 if (ret < 0) { 977 dev_err(dev, "%s failed", __func__); 978 return ret; 979 } 980 981 /* 982 * The clock flow is 983 * 984 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] 985 * 986 * But, it needs to find best match of CPG and FSI_DIV 987 * combination, since it is difficult to generate correct 988 * frequency of audio clock from ick clock only. 989 * Because ick is created from its parent clock. 990 * 991 * target = rate x [512/256/128/64]fs 992 * cout = round(target x adjustment) 993 * actual = cout / adjustment (by FSI-DIV) ~= target 994 * audio = actual 995 */ 996 min = ~0; 997 best_cout = 0; 998 best_act = 0; 999 for (adj = 1; adj < 0xffff; adj++) { 1000 1001 cout = target * adj; 1002 if (cout > 100000000) /* max clock = 100MHz */ 1003 break; 1004 1005 /* cout/actual audio clock */ 1006 cout = clk_round_rate(ick, cout); 1007 actual = cout / adj; 1008 1009 /* find best frequency */ 1010 diff = abs(actual - target); 1011 if (diff < min) { 1012 min = diff; 1013 best_cout = cout; 1014 best_act = actual; 1015 } 1016 } 1017 1018 ret = clk_set_rate(ick, best_cout); 1019 if (ret < 0) { 1020 dev_err(dev, "ick clock failed\n"); 1021 return -EIO; 1022 } 1023 1024 ret = clk_set_rate(div, clk_round_rate(div, best_act)); 1025 if (ret < 0) { 1026 dev_err(dev, "div clock failed\n"); 1027 return -EIO; 1028 } 1029 1030 dev_dbg(dev, "ick/div = %ld/%ld\n", 1031 clk_get_rate(ick), clk_get_rate(div)); 1032 1033 return ret; 1034 } 1035 1036 static void fsi_pointer_update(struct fsi_stream *io, int size) 1037 { 1038 io->buff_sample_pos += size; 1039 1040 if (io->buff_sample_pos >= 1041 io->period_samples * (io->period_pos + 1)) { 1042 struct snd_pcm_substream *substream = io->substream; 1043 struct snd_pcm_runtime *runtime = substream->runtime; 1044 1045 io->period_pos++; 1046 1047 if (io->period_pos >= runtime->periods) { 1048 io->buff_sample_pos = 0; 1049 io->period_pos = 0; 1050 } 1051 1052 snd_pcm_period_elapsed(substream); 1053 } 1054 } 1055 1056 /* 1057 * pio data transfer handler 1058 */ 1059 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) 1060 { 1061 int i; 1062 1063 if (fsi_is_enable_stream(fsi)) { 1064 /* 1065 * stream mode 1066 * see 1067 * fsi_pio_push_init() 1068 */ 1069 u32 *buf = (u32 *)_buf; 1070 1071 for (i = 0; i < samples / 2; i++) 1072 fsi_reg_write(fsi, DODT, buf[i]); 1073 } else { 1074 /* normal mode */ 1075 u16 *buf = (u16 *)_buf; 1076 1077 for (i = 0; i < samples; i++) 1078 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); 1079 } 1080 } 1081 1082 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) 1083 { 1084 u16 *buf = (u16 *)_buf; 1085 int i; 1086 1087 for (i = 0; i < samples; i++) 1088 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); 1089 } 1090 1091 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) 1092 { 1093 u32 *buf = (u32 *)_buf; 1094 int i; 1095 1096 for (i = 0; i < samples; i++) 1097 fsi_reg_write(fsi, DODT, *(buf + i)); 1098 } 1099 1100 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) 1101 { 1102 u32 *buf = (u32 *)_buf; 1103 int i; 1104 1105 for (i = 0; i < samples; i++) 1106 *(buf + i) = fsi_reg_read(fsi, DIDT); 1107 } 1108 1109 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) 1110 { 1111 struct snd_pcm_runtime *runtime = io->substream->runtime; 1112 1113 return runtime->dma_area + 1114 samples_to_bytes(runtime, io->buff_sample_pos); 1115 } 1116 1117 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, 1118 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), 1119 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), 1120 int samples) 1121 { 1122 u8 *buf; 1123 1124 if (!fsi_stream_is_working(fsi, io)) 1125 return -EINVAL; 1126 1127 buf = fsi_pio_get_area(fsi, io); 1128 1129 switch (io->sample_width) { 1130 case 2: 1131 run16(fsi, buf, samples); 1132 break; 1133 case 4: 1134 run32(fsi, buf, samples); 1135 break; 1136 default: 1137 return -EINVAL; 1138 } 1139 1140 fsi_pointer_update(io, samples); 1141 1142 return 0; 1143 } 1144 1145 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) 1146 { 1147 int sample_residues; /* samples in FSI fifo */ 1148 int sample_space; /* ALSA free samples space */ 1149 int samples; 1150 1151 sample_residues = fsi_get_current_fifo_samples(fsi, io); 1152 sample_space = io->buff_sample_capa - io->buff_sample_pos; 1153 1154 samples = min(sample_residues, sample_space); 1155 1156 return fsi_pio_transfer(fsi, io, 1157 fsi_pio_pop16, 1158 fsi_pio_pop32, 1159 samples); 1160 } 1161 1162 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) 1163 { 1164 int sample_residues; /* ALSA residue samples */ 1165 int sample_space; /* FSI fifo free samples space */ 1166 int samples; 1167 1168 sample_residues = io->buff_sample_capa - io->buff_sample_pos; 1169 sample_space = io->fifo_sample_capa - 1170 fsi_get_current_fifo_samples(fsi, io); 1171 1172 samples = min(sample_residues, sample_space); 1173 1174 return fsi_pio_transfer(fsi, io, 1175 fsi_pio_push16, 1176 fsi_pio_push32, 1177 samples); 1178 } 1179 1180 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1181 int enable) 1182 { 1183 struct fsi_master *master = fsi_get_master(fsi); 1184 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1185 1186 if (enable) 1187 fsi_irq_enable(fsi, io); 1188 else 1189 fsi_irq_disable(fsi, io); 1190 1191 if (fsi_is_clk_master(fsi)) 1192 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1193 1194 return 0; 1195 } 1196 1197 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) 1198 { 1199 /* 1200 * we can use 16bit stream mode 1201 * when "playback" and "16bit data" 1202 * and platform allows "stream mode" 1203 * see 1204 * fsi_pio_push16() 1205 */ 1206 if (fsi_is_enable_stream(fsi)) 1207 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1208 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1209 else 1210 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1211 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1212 return 0; 1213 } 1214 1215 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) 1216 { 1217 /* 1218 * always 24bit bus, package back when "capture" 1219 */ 1220 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1221 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1222 return 0; 1223 } 1224 1225 static struct fsi_stream_handler fsi_pio_push_handler = { 1226 .init = fsi_pio_push_init, 1227 .transfer = fsi_pio_push, 1228 .start_stop = fsi_pio_start_stop, 1229 }; 1230 1231 static struct fsi_stream_handler fsi_pio_pop_handler = { 1232 .init = fsi_pio_pop_init, 1233 .transfer = fsi_pio_pop, 1234 .start_stop = fsi_pio_start_stop, 1235 }; 1236 1237 static irqreturn_t fsi_interrupt(int irq, void *data) 1238 { 1239 struct fsi_master *master = data; 1240 u32 int_st = fsi_irq_get_status(master); 1241 1242 /* clear irq status */ 1243 fsi_master_mask_set(master, SOFT_RST, IR, 0); 1244 fsi_master_mask_set(master, SOFT_RST, IR, IR); 1245 1246 if (int_st & AB_IO(1, AO_SHIFT)) 1247 fsi_stream_transfer(&master->fsia.playback); 1248 if (int_st & AB_IO(1, BO_SHIFT)) 1249 fsi_stream_transfer(&master->fsib.playback); 1250 if (int_st & AB_IO(1, AI_SHIFT)) 1251 fsi_stream_transfer(&master->fsia.capture); 1252 if (int_st & AB_IO(1, BI_SHIFT)) 1253 fsi_stream_transfer(&master->fsib.capture); 1254 1255 fsi_count_fifo_err(&master->fsia); 1256 fsi_count_fifo_err(&master->fsib); 1257 1258 fsi_irq_clear_status(&master->fsia); 1259 fsi_irq_clear_status(&master->fsib); 1260 1261 return IRQ_HANDLED; 1262 } 1263 1264 /* 1265 * dma data transfer handler 1266 */ 1267 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) 1268 { 1269 /* 1270 * 24bit data : 24bit bus / package in back 1271 * 16bit data : 16bit bus / stream mode 1272 */ 1273 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1274 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1275 1276 return 0; 1277 } 1278 1279 static void fsi_dma_complete(void *data) 1280 { 1281 struct fsi_stream *io = (struct fsi_stream *)data; 1282 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1283 1284 fsi_pointer_update(io, io->period_samples); 1285 1286 fsi_count_fifo_err(fsi); 1287 } 1288 1289 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) 1290 { 1291 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1292 struct snd_pcm_substream *substream = io->substream; 1293 struct dma_async_tx_descriptor *desc; 1294 int is_play = fsi_stream_is_play(fsi, io); 1295 enum dma_transfer_direction dir; 1296 int ret = -EIO; 1297 1298 if (is_play) 1299 dir = DMA_MEM_TO_DEV; 1300 else 1301 dir = DMA_DEV_TO_MEM; 1302 1303 desc = dmaengine_prep_dma_cyclic(io->chan, 1304 substream->runtime->dma_addr, 1305 snd_pcm_lib_buffer_bytes(substream), 1306 snd_pcm_lib_period_bytes(substream), 1307 dir, 1308 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1309 if (!desc) { 1310 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n"); 1311 goto fsi_dma_transfer_err; 1312 } 1313 1314 desc->callback = fsi_dma_complete; 1315 desc->callback_param = io; 1316 1317 if (dmaengine_submit(desc) < 0) { 1318 dev_err(dai->dev, "tx_submit() fail\n"); 1319 goto fsi_dma_transfer_err; 1320 } 1321 1322 dma_async_issue_pending(io->chan); 1323 1324 /* 1325 * FIXME 1326 * 1327 * In DMAEngine case, codec and FSI cannot be started simultaneously 1328 * since FSI is using the scheduler work queue. 1329 * Therefore, in capture case, probably FSI FIFO will have got 1330 * overflow error in this point. 1331 * in that case, DMA cannot start transfer until error was cleared. 1332 */ 1333 if (!is_play) { 1334 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { 1335 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1336 fsi_reg_write(fsi, DIFF_ST, 0); 1337 } 1338 } 1339 1340 ret = 0; 1341 1342 fsi_dma_transfer_err: 1343 return ret; 1344 } 1345 1346 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1347 int start) 1348 { 1349 struct fsi_master *master = fsi_get_master(fsi); 1350 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1351 u32 enable = start ? DMA_ON : 0; 1352 1353 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); 1354 1355 dmaengine_terminate_all(io->chan); 1356 1357 if (fsi_is_clk_master(fsi)) 1358 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1359 1360 return 0; 1361 } 1362 1363 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) 1364 { 1365 int is_play = fsi_stream_is_play(fsi, io); 1366 1367 #ifdef CONFIG_SUPERH 1368 dma_cap_mask_t mask; 1369 dma_cap_zero(mask); 1370 dma_cap_set(DMA_SLAVE, mask); 1371 1372 io->chan = dma_request_channel(mask, shdma_chan_filter, 1373 (void *)io->dma_id); 1374 #else 1375 io->chan = dma_request_slave_channel(dev, is_play ? "tx" : "rx"); 1376 #endif 1377 if (io->chan) { 1378 struct dma_slave_config cfg = {}; 1379 int ret; 1380 1381 if (is_play) { 1382 cfg.dst_addr = fsi->phys + REG_DODT; 1383 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1384 cfg.direction = DMA_MEM_TO_DEV; 1385 } else { 1386 cfg.src_addr = fsi->phys + REG_DIDT; 1387 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1388 cfg.direction = DMA_DEV_TO_MEM; 1389 } 1390 1391 ret = dmaengine_slave_config(io->chan, &cfg); 1392 if (ret < 0) { 1393 dma_release_channel(io->chan); 1394 io->chan = NULL; 1395 } 1396 } 1397 1398 if (!io->chan) { 1399 1400 /* switch to PIO handler */ 1401 if (is_play) 1402 fsi->playback.handler = &fsi_pio_push_handler; 1403 else 1404 fsi->capture.handler = &fsi_pio_pop_handler; 1405 1406 dev_info(dev, "switch handler (dma => pio)\n"); 1407 1408 /* probe again */ 1409 return fsi_stream_probe(fsi, dev); 1410 } 1411 1412 return 0; 1413 } 1414 1415 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) 1416 { 1417 fsi_stream_stop(fsi, io); 1418 1419 if (io->chan) 1420 dma_release_channel(io->chan); 1421 1422 io->chan = NULL; 1423 return 0; 1424 } 1425 1426 static struct fsi_stream_handler fsi_dma_push_handler = { 1427 .init = fsi_dma_init, 1428 .probe = fsi_dma_probe, 1429 .transfer = fsi_dma_transfer, 1430 .remove = fsi_dma_remove, 1431 .start_stop = fsi_dma_push_start_stop, 1432 }; 1433 1434 /* 1435 * dai ops 1436 */ 1437 static void fsi_fifo_init(struct fsi_priv *fsi, 1438 struct fsi_stream *io, 1439 struct device *dev) 1440 { 1441 struct fsi_master *master = fsi_get_master(fsi); 1442 int is_play = fsi_stream_is_play(fsi, io); 1443 u32 shift, i; 1444 int frame_capa; 1445 1446 /* get on-chip RAM capacity */ 1447 shift = fsi_master_read(master, FIFO_SZ); 1448 shift >>= fsi_get_port_shift(fsi, io); 1449 shift &= FIFO_SZ_MASK; 1450 frame_capa = 256 << shift; 1451 dev_dbg(dev, "fifo = %d words\n", frame_capa); 1452 1453 /* 1454 * The maximum number of sample data varies depending 1455 * on the number of channels selected for the format. 1456 * 1457 * FIFOs are used in 4-channel units in 3-channel mode 1458 * and in 8-channel units in 5- to 7-channel mode 1459 * meaning that more FIFOs than the required size of DPRAM 1460 * are used. 1461 * 1462 * ex) if 256 words of DP-RAM is connected 1463 * 1 channel: 256 (256 x 1 = 256) 1464 * 2 channels: 128 (128 x 2 = 256) 1465 * 3 channels: 64 ( 64 x 3 = 192) 1466 * 4 channels: 64 ( 64 x 4 = 256) 1467 * 5 channels: 32 ( 32 x 5 = 160) 1468 * 6 channels: 32 ( 32 x 6 = 192) 1469 * 7 channels: 32 ( 32 x 7 = 224) 1470 * 8 channels: 32 ( 32 x 8 = 256) 1471 */ 1472 for (i = 1; i < fsi->chan_num; i <<= 1) 1473 frame_capa >>= 1; 1474 dev_dbg(dev, "%d channel %d store\n", 1475 fsi->chan_num, frame_capa); 1476 1477 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); 1478 1479 /* 1480 * set interrupt generation factor 1481 * clear FIFO 1482 */ 1483 if (is_play) { 1484 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); 1485 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); 1486 } else { 1487 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); 1488 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1489 } 1490 } 1491 1492 static int fsi_hw_startup(struct fsi_priv *fsi, 1493 struct fsi_stream *io, 1494 struct device *dev) 1495 { 1496 u32 data = 0; 1497 1498 /* clock setting */ 1499 if (fsi_is_clk_master(fsi)) 1500 data = DIMD | DOMD; 1501 1502 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); 1503 1504 /* clock inversion (CKG2) */ 1505 data = 0; 1506 if (fsi->bit_clk_inv) 1507 data |= (1 << 0); 1508 if (fsi->lr_clk_inv) 1509 data |= (1 << 4); 1510 if (fsi_is_clk_master(fsi)) 1511 data <<= 8; 1512 fsi_reg_write(fsi, CKG2, data); 1513 1514 /* spdif ? */ 1515 if (fsi_is_spdif(fsi)) { 1516 fsi_spdif_clk_ctrl(fsi, 1); 1517 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); 1518 } 1519 1520 /* 1521 * get bus settings 1522 */ 1523 data = 0; 1524 switch (io->sample_width) { 1525 case 2: 1526 data = BUSOP_GET(16, io->bus_option); 1527 break; 1528 case 4: 1529 data = BUSOP_GET(24, io->bus_option); 1530 break; 1531 } 1532 fsi_format_bus_setup(fsi, io, data, dev); 1533 1534 /* irq clear */ 1535 fsi_irq_disable(fsi, io); 1536 fsi_irq_clear_status(fsi); 1537 1538 /* fifo init */ 1539 fsi_fifo_init(fsi, io, dev); 1540 1541 /* start master clock */ 1542 if (fsi_is_clk_master(fsi)) 1543 return fsi_clk_enable(dev, fsi); 1544 1545 return 0; 1546 } 1547 1548 static int fsi_hw_shutdown(struct fsi_priv *fsi, 1549 struct device *dev) 1550 { 1551 /* stop master clock */ 1552 if (fsi_is_clk_master(fsi)) 1553 return fsi_clk_disable(dev, fsi); 1554 1555 return 0; 1556 } 1557 1558 static int fsi_dai_startup(struct snd_pcm_substream *substream, 1559 struct snd_soc_dai *dai) 1560 { 1561 struct fsi_priv *fsi = fsi_get_priv(substream); 1562 1563 fsi_clk_invalid(fsi); 1564 1565 return 0; 1566 } 1567 1568 static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 1569 struct snd_soc_dai *dai) 1570 { 1571 struct fsi_priv *fsi = fsi_get_priv(substream); 1572 1573 fsi_clk_invalid(fsi); 1574 } 1575 1576 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 1577 struct snd_soc_dai *dai) 1578 { 1579 struct fsi_priv *fsi = fsi_get_priv(substream); 1580 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1581 int ret = 0; 1582 1583 switch (cmd) { 1584 case SNDRV_PCM_TRIGGER_START: 1585 fsi_stream_init(fsi, io, substream); 1586 if (!ret) 1587 ret = fsi_hw_startup(fsi, io, dai->dev); 1588 if (!ret) 1589 ret = fsi_stream_start(fsi, io); 1590 if (!ret) 1591 ret = fsi_stream_transfer(io); 1592 break; 1593 case SNDRV_PCM_TRIGGER_STOP: 1594 if (!ret) 1595 ret = fsi_hw_shutdown(fsi, dai->dev); 1596 fsi_stream_stop(fsi, io); 1597 fsi_stream_quit(fsi, io); 1598 break; 1599 } 1600 1601 return ret; 1602 } 1603 1604 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) 1605 { 1606 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1607 case SND_SOC_DAIFMT_I2S: 1608 fsi->fmt = CR_I2S; 1609 fsi->chan_num = 2; 1610 break; 1611 case SND_SOC_DAIFMT_LEFT_J: 1612 fsi->fmt = CR_PCM; 1613 fsi->chan_num = 2; 1614 break; 1615 default: 1616 return -EINVAL; 1617 } 1618 1619 return 0; 1620 } 1621 1622 static int fsi_set_fmt_spdif(struct fsi_priv *fsi) 1623 { 1624 struct fsi_master *master = fsi_get_master(fsi); 1625 1626 if (fsi_version(master) < 2) 1627 return -EINVAL; 1628 1629 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; 1630 fsi->chan_num = 2; 1631 1632 return 0; 1633 } 1634 1635 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1636 { 1637 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); 1638 int ret; 1639 1640 /* set master/slave audio interface */ 1641 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1642 case SND_SOC_DAIFMT_CBM_CFM: 1643 break; 1644 case SND_SOC_DAIFMT_CBS_CFS: 1645 fsi->clk_master = 1; /* codec is slave, cpu is master */ 1646 break; 1647 default: 1648 return -EINVAL; 1649 } 1650 1651 /* set clock inversion */ 1652 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1653 case SND_SOC_DAIFMT_NB_IF: 1654 fsi->bit_clk_inv = 0; 1655 fsi->lr_clk_inv = 1; 1656 break; 1657 case SND_SOC_DAIFMT_IB_NF: 1658 fsi->bit_clk_inv = 1; 1659 fsi->lr_clk_inv = 0; 1660 break; 1661 case SND_SOC_DAIFMT_IB_IF: 1662 fsi->bit_clk_inv = 1; 1663 fsi->lr_clk_inv = 1; 1664 break; 1665 case SND_SOC_DAIFMT_NB_NF: 1666 default: 1667 fsi->bit_clk_inv = 0; 1668 fsi->lr_clk_inv = 0; 1669 break; 1670 } 1671 1672 if (fsi_is_clk_master(fsi)) { 1673 if (fsi->clk_cpg) 1674 fsi_clk_init(dai->dev, fsi, 0, 1, 1, 1675 fsi_clk_set_rate_cpg); 1676 else 1677 fsi_clk_init(dai->dev, fsi, 1, 1, 0, 1678 fsi_clk_set_rate_external); 1679 } 1680 1681 /* set format */ 1682 if (fsi_is_spdif(fsi)) 1683 ret = fsi_set_fmt_spdif(fsi); 1684 else 1685 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1686 1687 return ret; 1688 } 1689 1690 static int fsi_dai_hw_params(struct snd_pcm_substream *substream, 1691 struct snd_pcm_hw_params *params, 1692 struct snd_soc_dai *dai) 1693 { 1694 struct fsi_priv *fsi = fsi_get_priv(substream); 1695 1696 if (fsi_is_clk_master(fsi)) 1697 fsi_clk_valid(fsi, params_rate(params)); 1698 1699 return 0; 1700 } 1701 1702 static const struct snd_soc_dai_ops fsi_dai_ops = { 1703 .startup = fsi_dai_startup, 1704 .shutdown = fsi_dai_shutdown, 1705 .trigger = fsi_dai_trigger, 1706 .set_fmt = fsi_dai_set_fmt, 1707 .hw_params = fsi_dai_hw_params, 1708 }; 1709 1710 /* 1711 * pcm ops 1712 */ 1713 1714 static struct snd_pcm_hardware fsi_pcm_hardware = { 1715 .info = SNDRV_PCM_INFO_INTERLEAVED | 1716 SNDRV_PCM_INFO_MMAP | 1717 SNDRV_PCM_INFO_MMAP_VALID, 1718 .buffer_bytes_max = 64 * 1024, 1719 .period_bytes_min = 32, 1720 .period_bytes_max = 8192, 1721 .periods_min = 1, 1722 .periods_max = 32, 1723 .fifo_size = 256, 1724 }; 1725 1726 static int fsi_pcm_open(struct snd_pcm_substream *substream) 1727 { 1728 struct snd_pcm_runtime *runtime = substream->runtime; 1729 int ret = 0; 1730 1731 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 1732 1733 ret = snd_pcm_hw_constraint_integer(runtime, 1734 SNDRV_PCM_HW_PARAM_PERIODS); 1735 1736 return ret; 1737 } 1738 1739 static int fsi_hw_params(struct snd_pcm_substream *substream, 1740 struct snd_pcm_hw_params *hw_params) 1741 { 1742 return snd_pcm_lib_malloc_pages(substream, 1743 params_buffer_bytes(hw_params)); 1744 } 1745 1746 static int fsi_hw_free(struct snd_pcm_substream *substream) 1747 { 1748 return snd_pcm_lib_free_pages(substream); 1749 } 1750 1751 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) 1752 { 1753 struct fsi_priv *fsi = fsi_get_priv(substream); 1754 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1755 1756 return fsi_sample2frame(fsi, io->buff_sample_pos); 1757 } 1758 1759 static struct snd_pcm_ops fsi_pcm_ops = { 1760 .open = fsi_pcm_open, 1761 .ioctl = snd_pcm_lib_ioctl, 1762 .hw_params = fsi_hw_params, 1763 .hw_free = fsi_hw_free, 1764 .pointer = fsi_pointer, 1765 }; 1766 1767 /* 1768 * snd_soc_platform 1769 */ 1770 1771 #define PREALLOC_BUFFER (32 * 1024) 1772 #define PREALLOC_BUFFER_MAX (32 * 1024) 1773 1774 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) 1775 { 1776 return snd_pcm_lib_preallocate_pages_for_all( 1777 rtd->pcm, 1778 SNDRV_DMA_TYPE_DEV, 1779 rtd->card->snd_card->dev, 1780 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1781 } 1782 1783 /* 1784 * alsa struct 1785 */ 1786 1787 static struct snd_soc_dai_driver fsi_soc_dai[] = { 1788 { 1789 .name = "fsia-dai", 1790 .playback = { 1791 .rates = FSI_RATES, 1792 .formats = FSI_FMTS, 1793 .channels_min = 2, 1794 .channels_max = 2, 1795 }, 1796 .capture = { 1797 .rates = FSI_RATES, 1798 .formats = FSI_FMTS, 1799 .channels_min = 2, 1800 .channels_max = 2, 1801 }, 1802 .ops = &fsi_dai_ops, 1803 }, 1804 { 1805 .name = "fsib-dai", 1806 .playback = { 1807 .rates = FSI_RATES, 1808 .formats = FSI_FMTS, 1809 .channels_min = 2, 1810 .channels_max = 2, 1811 }, 1812 .capture = { 1813 .rates = FSI_RATES, 1814 .formats = FSI_FMTS, 1815 .channels_min = 2, 1816 .channels_max = 2, 1817 }, 1818 .ops = &fsi_dai_ops, 1819 }, 1820 }; 1821 1822 static struct snd_soc_platform_driver fsi_soc_platform = { 1823 .ops = &fsi_pcm_ops, 1824 .pcm_new = fsi_pcm_new, 1825 }; 1826 1827 static const struct snd_soc_component_driver fsi_soc_component = { 1828 .name = "fsi", 1829 }; 1830 1831 /* 1832 * platform function 1833 */ 1834 static void fsi_of_parse(char *name, 1835 struct device_node *np, 1836 struct sh_fsi_port_info *info, 1837 struct device *dev) 1838 { 1839 int i; 1840 char prop[128]; 1841 unsigned long flags = 0; 1842 struct { 1843 char *name; 1844 unsigned int val; 1845 } of_parse_property[] = { 1846 { "spdif-connection", SH_FSI_FMT_SPDIF }, 1847 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE }, 1848 { "use-internal-clock", SH_FSI_CLK_CPG }, 1849 }; 1850 1851 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) { 1852 sprintf(prop, "%s,%s", name, of_parse_property[i].name); 1853 if (of_get_property(np, prop, NULL)) 1854 flags |= of_parse_property[i].val; 1855 } 1856 info->flags = flags; 1857 1858 dev_dbg(dev, "%s flags : %lx\n", name, info->flags); 1859 } 1860 1861 static void fsi_port_info_init(struct fsi_priv *fsi, 1862 struct sh_fsi_port_info *info) 1863 { 1864 if (info->flags & SH_FSI_FMT_SPDIF) 1865 fsi->spdif = 1; 1866 1867 if (info->flags & SH_FSI_CLK_CPG) 1868 fsi->clk_cpg = 1; 1869 1870 if (info->flags & SH_FSI_ENABLE_STREAM_MODE) 1871 fsi->enable_stream = 1; 1872 } 1873 1874 static void fsi_handler_init(struct fsi_priv *fsi, 1875 struct sh_fsi_port_info *info) 1876 { 1877 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ 1878 fsi->playback.priv = fsi; 1879 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ 1880 fsi->capture.priv = fsi; 1881 1882 if (info->tx_id) { 1883 fsi->playback.dma_id = info->tx_id; 1884 fsi->playback.handler = &fsi_dma_push_handler; 1885 } 1886 } 1887 1888 static const struct fsi_core fsi1_core = { 1889 .ver = 1, 1890 1891 /* Interrupt */ 1892 .int_st = INT_ST, 1893 .iemsk = IEMSK, 1894 .imsk = IMSK, 1895 }; 1896 1897 static const struct fsi_core fsi2_core = { 1898 .ver = 2, 1899 1900 /* Interrupt */ 1901 .int_st = CPU_INT_ST, 1902 .iemsk = CPU_IEMSK, 1903 .imsk = CPU_IMSK, 1904 .a_mclk = A_MST_CTLR, 1905 .b_mclk = B_MST_CTLR, 1906 }; 1907 1908 static const struct of_device_id fsi_of_match[] = { 1909 { .compatible = "renesas,sh_fsi", .data = &fsi1_core}, 1910 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core}, 1911 {}, 1912 }; 1913 MODULE_DEVICE_TABLE(of, fsi_of_match); 1914 1915 static const struct platform_device_id fsi_id_table[] = { 1916 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, 1917 {}, 1918 }; 1919 MODULE_DEVICE_TABLE(platform, fsi_id_table); 1920 1921 static int fsi_probe(struct platform_device *pdev) 1922 { 1923 struct fsi_master *master; 1924 struct device_node *np = pdev->dev.of_node; 1925 struct sh_fsi_platform_info info; 1926 const struct fsi_core *core; 1927 struct fsi_priv *fsi; 1928 struct resource *res; 1929 unsigned int irq; 1930 int ret; 1931 1932 memset(&info, 0, sizeof(info)); 1933 1934 core = NULL; 1935 if (np) { 1936 const struct of_device_id *of_id; 1937 1938 of_id = of_match_device(fsi_of_match, &pdev->dev); 1939 if (of_id) { 1940 core = of_id->data; 1941 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev); 1942 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev); 1943 } 1944 } else { 1945 const struct platform_device_id *id_entry = pdev->id_entry; 1946 if (id_entry) 1947 core = (struct fsi_core *)id_entry->driver_data; 1948 1949 if (pdev->dev.platform_data) 1950 memcpy(&info, pdev->dev.platform_data, sizeof(info)); 1951 } 1952 1953 if (!core) { 1954 dev_err(&pdev->dev, "unknown fsi device\n"); 1955 return -ENODEV; 1956 } 1957 1958 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1959 irq = platform_get_irq(pdev, 0); 1960 if (!res || (int)irq <= 0) { 1961 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 1962 return -ENODEV; 1963 } 1964 1965 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1966 if (!master) { 1967 dev_err(&pdev->dev, "Could not allocate master\n"); 1968 return -ENOMEM; 1969 } 1970 1971 master->base = devm_ioremap_nocache(&pdev->dev, 1972 res->start, resource_size(res)); 1973 if (!master->base) { 1974 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 1975 return -ENXIO; 1976 } 1977 1978 /* master setting */ 1979 master->core = core; 1980 spin_lock_init(&master->lock); 1981 1982 /* FSI A setting */ 1983 fsi = &master->fsia; 1984 fsi->base = master->base; 1985 fsi->phys = res->start; 1986 fsi->master = master; 1987 fsi_port_info_init(fsi, &info.port_a); 1988 fsi_handler_init(fsi, &info.port_a); 1989 ret = fsi_stream_probe(fsi, &pdev->dev); 1990 if (ret < 0) { 1991 dev_err(&pdev->dev, "FSIA stream probe failed\n"); 1992 return ret; 1993 } 1994 1995 /* FSI B setting */ 1996 fsi = &master->fsib; 1997 fsi->base = master->base + 0x40; 1998 fsi->phys = res->start + 0x40; 1999 fsi->master = master; 2000 fsi_port_info_init(fsi, &info.port_b); 2001 fsi_handler_init(fsi, &info.port_b); 2002 ret = fsi_stream_probe(fsi, &pdev->dev); 2003 if (ret < 0) { 2004 dev_err(&pdev->dev, "FSIB stream probe failed\n"); 2005 goto exit_fsia; 2006 } 2007 2008 pm_runtime_enable(&pdev->dev); 2009 dev_set_drvdata(&pdev->dev, master); 2010 2011 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, 2012 dev_name(&pdev->dev), master); 2013 if (ret) { 2014 dev_err(&pdev->dev, "irq request err\n"); 2015 goto exit_fsib; 2016 } 2017 2018 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); 2019 if (ret < 0) { 2020 dev_err(&pdev->dev, "cannot snd soc register\n"); 2021 goto exit_fsib; 2022 } 2023 2024 ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component, 2025 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 2026 if (ret < 0) { 2027 dev_err(&pdev->dev, "cannot snd component register\n"); 2028 goto exit_snd_soc; 2029 } 2030 2031 return ret; 2032 2033 exit_snd_soc: 2034 snd_soc_unregister_platform(&pdev->dev); 2035 exit_fsib: 2036 pm_runtime_disable(&pdev->dev); 2037 fsi_stream_remove(&master->fsib); 2038 exit_fsia: 2039 fsi_stream_remove(&master->fsia); 2040 2041 return ret; 2042 } 2043 2044 static int fsi_remove(struct platform_device *pdev) 2045 { 2046 struct fsi_master *master; 2047 2048 master = dev_get_drvdata(&pdev->dev); 2049 2050 pm_runtime_disable(&pdev->dev); 2051 2052 snd_soc_unregister_component(&pdev->dev); 2053 snd_soc_unregister_platform(&pdev->dev); 2054 2055 fsi_stream_remove(&master->fsia); 2056 fsi_stream_remove(&master->fsib); 2057 2058 return 0; 2059 } 2060 2061 static void __fsi_suspend(struct fsi_priv *fsi, 2062 struct fsi_stream *io, 2063 struct device *dev) 2064 { 2065 if (!fsi_stream_is_working(fsi, io)) 2066 return; 2067 2068 fsi_stream_stop(fsi, io); 2069 fsi_hw_shutdown(fsi, dev); 2070 } 2071 2072 static void __fsi_resume(struct fsi_priv *fsi, 2073 struct fsi_stream *io, 2074 struct device *dev) 2075 { 2076 if (!fsi_stream_is_working(fsi, io)) 2077 return; 2078 2079 fsi_hw_startup(fsi, io, dev); 2080 fsi_stream_start(fsi, io); 2081 } 2082 2083 static int fsi_suspend(struct device *dev) 2084 { 2085 struct fsi_master *master = dev_get_drvdata(dev); 2086 struct fsi_priv *fsia = &master->fsia; 2087 struct fsi_priv *fsib = &master->fsib; 2088 2089 __fsi_suspend(fsia, &fsia->playback, dev); 2090 __fsi_suspend(fsia, &fsia->capture, dev); 2091 2092 __fsi_suspend(fsib, &fsib->playback, dev); 2093 __fsi_suspend(fsib, &fsib->capture, dev); 2094 2095 return 0; 2096 } 2097 2098 static int fsi_resume(struct device *dev) 2099 { 2100 struct fsi_master *master = dev_get_drvdata(dev); 2101 struct fsi_priv *fsia = &master->fsia; 2102 struct fsi_priv *fsib = &master->fsib; 2103 2104 __fsi_resume(fsia, &fsia->playback, dev); 2105 __fsi_resume(fsia, &fsia->capture, dev); 2106 2107 __fsi_resume(fsib, &fsib->playback, dev); 2108 __fsi_resume(fsib, &fsib->capture, dev); 2109 2110 return 0; 2111 } 2112 2113 static struct dev_pm_ops fsi_pm_ops = { 2114 .suspend = fsi_suspend, 2115 .resume = fsi_resume, 2116 }; 2117 2118 static struct platform_driver fsi_driver = { 2119 .driver = { 2120 .name = "fsi-pcm-audio", 2121 .pm = &fsi_pm_ops, 2122 .of_match_table = fsi_of_match, 2123 }, 2124 .probe = fsi_probe, 2125 .remove = fsi_remove, 2126 .id_table = fsi_id_table, 2127 }; 2128 2129 module_platform_driver(fsi_driver); 2130 2131 MODULE_LICENSE("GPL v2"); 2132 MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); 2133 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 2134 MODULE_ALIAS("platform:fsi-pcm-audio"); 2135