1 /* sound/soc/samsung/i2s.c 2 * 3 * ALSA SoC Audio Layer - Samsung I2S Controller driver 4 * 5 * Copyright (c) 2010 Samsung Electronics Co. Ltd. 6 * Jaswinder Singh <jassisinghbrar@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <dt-bindings/sound/samsung-i2s.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_gpio.h> 23 #include <linux/pm_runtime.h> 24 25 #include <sound/soc.h> 26 #include <sound/pcm_params.h> 27 28 #include <linux/platform_data/asoc-s3c.h> 29 30 #include "dma.h" 31 #include "idma.h" 32 #include "i2s.h" 33 #include "i2s-regs.h" 34 35 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 36 37 struct samsung_i2s_variant_regs { 38 unsigned int bfs_off; 39 unsigned int rfs_off; 40 unsigned int sdf_off; 41 unsigned int txr_off; 42 unsigned int rclksrc_off; 43 unsigned int mss_off; 44 unsigned int cdclkcon_off; 45 unsigned int lrp_off; 46 unsigned int bfs_mask; 47 unsigned int rfs_mask; 48 unsigned int ftx0cnt_off; 49 }; 50 51 struct samsung_i2s_dai_data { 52 u32 quirks; 53 unsigned int pcm_rates; 54 const struct samsung_i2s_variant_regs *i2s_variant_regs; 55 }; 56 57 struct i2s_dai { 58 /* Platform device for this DAI */ 59 struct platform_device *pdev; 60 /* Memory mapped SFR region */ 61 void __iomem *addr; 62 /* Rate of RCLK source clock */ 63 unsigned long rclk_srcrate; 64 /* Frame Clock */ 65 unsigned frmclk; 66 /* 67 * Specifically requested RCLK,BCLK by MACHINE Driver. 68 * 0 indicates CPU driver is free to choose any value. 69 */ 70 unsigned rfs, bfs; 71 /* I2S Controller's core clock */ 72 struct clk *clk; 73 /* Clock for generating I2S signals */ 74 struct clk *op_clk; 75 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */ 76 struct i2s_dai *pri_dai; 77 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */ 78 struct i2s_dai *sec_dai; 79 #define DAI_OPENED (1 << 0) /* Dai is opened */ 80 #define DAI_MANAGER (1 << 1) /* Dai is the manager */ 81 unsigned mode; 82 /* Driver for this DAI */ 83 struct snd_soc_dai_driver i2s_dai_drv; 84 /* DMA parameters */ 85 struct snd_dmaengine_dai_dma_data dma_playback; 86 struct snd_dmaengine_dai_dma_data dma_capture; 87 struct snd_dmaengine_dai_dma_data idma_playback; 88 dma_filter_fn filter; 89 u32 quirks; 90 u32 suspend_i2smod; 91 u32 suspend_i2scon; 92 u32 suspend_i2spsr; 93 const struct samsung_i2s_variant_regs *variant_regs; 94 95 /* Spinlock protecting access to the device's registers */ 96 spinlock_t spinlock; 97 spinlock_t *lock; 98 99 /* Below fields are only valid if this is the primary FIFO */ 100 struct clk *clk_table[3]; 101 struct clk_onecell_data clk_data; 102 }; 103 104 /* Lock for cross i/f checks */ 105 static DEFINE_SPINLOCK(lock); 106 107 /* If this is the 'overlay' stereo DAI */ 108 static inline bool is_secondary(struct i2s_dai *i2s) 109 { 110 return i2s->pri_dai ? true : false; 111 } 112 113 /* If operating in SoC-Slave mode */ 114 static inline bool is_slave(struct i2s_dai *i2s) 115 { 116 u32 mod = readl(i2s->addr + I2SMOD); 117 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false; 118 } 119 120 /* If this interface of the controller is transmitting data */ 121 static inline bool tx_active(struct i2s_dai *i2s) 122 { 123 u32 active; 124 125 if (!i2s) 126 return false; 127 128 active = readl(i2s->addr + I2SCON); 129 130 if (is_secondary(i2s)) 131 active &= CON_TXSDMA_ACTIVE; 132 else 133 active &= CON_TXDMA_ACTIVE; 134 135 return active ? true : false; 136 } 137 138 /* Return pointer to the other DAI */ 139 static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s) 140 { 141 return i2s->pri_dai ? : i2s->sec_dai; 142 } 143 144 /* If the other interface of the controller is transmitting data */ 145 static inline bool other_tx_active(struct i2s_dai *i2s) 146 { 147 struct i2s_dai *other = get_other_dai(i2s); 148 149 return tx_active(other); 150 } 151 152 /* If any interface of the controller is transmitting data */ 153 static inline bool any_tx_active(struct i2s_dai *i2s) 154 { 155 return tx_active(i2s) || other_tx_active(i2s); 156 } 157 158 /* If this interface of the controller is receiving data */ 159 static inline bool rx_active(struct i2s_dai *i2s) 160 { 161 u32 active; 162 163 if (!i2s) 164 return false; 165 166 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE; 167 168 return active ? true : false; 169 } 170 171 /* If the other interface of the controller is receiving data */ 172 static inline bool other_rx_active(struct i2s_dai *i2s) 173 { 174 struct i2s_dai *other = get_other_dai(i2s); 175 176 return rx_active(other); 177 } 178 179 /* If any interface of the controller is receiving data */ 180 static inline bool any_rx_active(struct i2s_dai *i2s) 181 { 182 return rx_active(i2s) || other_rx_active(i2s); 183 } 184 185 /* If the other DAI is transmitting or receiving data */ 186 static inline bool other_active(struct i2s_dai *i2s) 187 { 188 return other_rx_active(i2s) || other_tx_active(i2s); 189 } 190 191 /* If this DAI is transmitting or receiving data */ 192 static inline bool this_active(struct i2s_dai *i2s) 193 { 194 return tx_active(i2s) || rx_active(i2s); 195 } 196 197 /* If the controller is active anyway */ 198 static inline bool any_active(struct i2s_dai *i2s) 199 { 200 return this_active(i2s) || other_active(i2s); 201 } 202 203 static inline struct i2s_dai *to_info(struct snd_soc_dai *dai) 204 { 205 return snd_soc_dai_get_drvdata(dai); 206 } 207 208 static inline bool is_opened(struct i2s_dai *i2s) 209 { 210 if (i2s && (i2s->mode & DAI_OPENED)) 211 return true; 212 else 213 return false; 214 } 215 216 static inline bool is_manager(struct i2s_dai *i2s) 217 { 218 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER)) 219 return true; 220 else 221 return false; 222 } 223 224 /* Read RCLK of I2S (in multiples of LRCLK) */ 225 static inline unsigned get_rfs(struct i2s_dai *i2s) 226 { 227 u32 rfs; 228 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off; 229 rfs &= i2s->variant_regs->rfs_mask; 230 231 switch (rfs) { 232 case 7: return 192; 233 case 6: return 96; 234 case 5: return 128; 235 case 4: return 64; 236 case 3: return 768; 237 case 2: return 384; 238 case 1: return 512; 239 default: return 256; 240 } 241 } 242 243 /* Write RCLK of I2S (in multiples of LRCLK) */ 244 static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs) 245 { 246 u32 mod = readl(i2s->addr + I2SMOD); 247 int rfs_shift = i2s->variant_regs->rfs_off; 248 249 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift); 250 251 switch (rfs) { 252 case 192: 253 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift); 254 break; 255 case 96: 256 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift); 257 break; 258 case 128: 259 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift); 260 break; 261 case 64: 262 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift); 263 break; 264 case 768: 265 mod |= (MOD_RCLK_768FS << rfs_shift); 266 break; 267 case 512: 268 mod |= (MOD_RCLK_512FS << rfs_shift); 269 break; 270 case 384: 271 mod |= (MOD_RCLK_384FS << rfs_shift); 272 break; 273 default: 274 mod |= (MOD_RCLK_256FS << rfs_shift); 275 break; 276 } 277 278 writel(mod, i2s->addr + I2SMOD); 279 } 280 281 /* Read Bit-Clock of I2S (in multiples of LRCLK) */ 282 static inline unsigned get_bfs(struct i2s_dai *i2s) 283 { 284 u32 bfs; 285 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off; 286 bfs &= i2s->variant_regs->bfs_mask; 287 288 switch (bfs) { 289 case 8: return 256; 290 case 7: return 192; 291 case 6: return 128; 292 case 5: return 96; 293 case 4: return 64; 294 case 3: return 24; 295 case 2: return 16; 296 case 1: return 48; 297 default: return 32; 298 } 299 } 300 301 /* Write Bit-Clock of I2S (in multiples of LRCLK) */ 302 static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs) 303 { 304 u32 mod = readl(i2s->addr + I2SMOD); 305 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM; 306 int bfs_shift = i2s->variant_regs->bfs_off; 307 308 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */ 309 if (!tdm && bfs > 48) { 310 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n"); 311 return; 312 } 313 314 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift); 315 316 switch (bfs) { 317 case 48: 318 mod |= (MOD_BCLK_48FS << bfs_shift); 319 break; 320 case 32: 321 mod |= (MOD_BCLK_32FS << bfs_shift); 322 break; 323 case 24: 324 mod |= (MOD_BCLK_24FS << bfs_shift); 325 break; 326 case 16: 327 mod |= (MOD_BCLK_16FS << bfs_shift); 328 break; 329 case 64: 330 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift); 331 break; 332 case 96: 333 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift); 334 break; 335 case 128: 336 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift); 337 break; 338 case 192: 339 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift); 340 break; 341 case 256: 342 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift); 343 break; 344 default: 345 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n"); 346 return; 347 } 348 349 writel(mod, i2s->addr + I2SMOD); 350 } 351 352 /* Sample-Size */ 353 static inline int get_blc(struct i2s_dai *i2s) 354 { 355 int blc = readl(i2s->addr + I2SMOD); 356 357 blc = (blc >> 13) & 0x3; 358 359 switch (blc) { 360 case 2: return 24; 361 case 1: return 8; 362 default: return 16; 363 } 364 } 365 366 /* TX Channel Control */ 367 static void i2s_txctrl(struct i2s_dai *i2s, int on) 368 { 369 void __iomem *addr = i2s->addr; 370 int txr_off = i2s->variant_regs->txr_off; 371 u32 con = readl(addr + I2SCON); 372 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off); 373 374 if (on) { 375 con |= CON_ACTIVE; 376 con &= ~CON_TXCH_PAUSE; 377 378 if (is_secondary(i2s)) { 379 con |= CON_TXSDMA_ACTIVE; 380 con &= ~CON_TXSDMA_PAUSE; 381 } else { 382 con |= CON_TXDMA_ACTIVE; 383 con &= ~CON_TXDMA_PAUSE; 384 } 385 386 if (any_rx_active(i2s)) 387 mod |= 2 << txr_off; 388 else 389 mod |= 0 << txr_off; 390 } else { 391 if (is_secondary(i2s)) { 392 con |= CON_TXSDMA_PAUSE; 393 con &= ~CON_TXSDMA_ACTIVE; 394 } else { 395 con |= CON_TXDMA_PAUSE; 396 con &= ~CON_TXDMA_ACTIVE; 397 } 398 399 if (other_tx_active(i2s)) { 400 writel(con, addr + I2SCON); 401 return; 402 } 403 404 con |= CON_TXCH_PAUSE; 405 406 if (any_rx_active(i2s)) 407 mod |= 1 << txr_off; 408 else 409 con &= ~CON_ACTIVE; 410 } 411 412 writel(mod, addr + I2SMOD); 413 writel(con, addr + I2SCON); 414 } 415 416 /* RX Channel Control */ 417 static void i2s_rxctrl(struct i2s_dai *i2s, int on) 418 { 419 void __iomem *addr = i2s->addr; 420 int txr_off = i2s->variant_regs->txr_off; 421 u32 con = readl(addr + I2SCON); 422 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off); 423 424 if (on) { 425 con |= CON_RXDMA_ACTIVE | CON_ACTIVE; 426 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE); 427 428 if (any_tx_active(i2s)) 429 mod |= 2 << txr_off; 430 else 431 mod |= 1 << txr_off; 432 } else { 433 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE; 434 con &= ~CON_RXDMA_ACTIVE; 435 436 if (any_tx_active(i2s)) 437 mod |= 0 << txr_off; 438 else 439 con &= ~CON_ACTIVE; 440 } 441 442 writel(mod, addr + I2SMOD); 443 writel(con, addr + I2SCON); 444 } 445 446 /* Flush FIFO of an interface */ 447 static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush) 448 { 449 void __iomem *fic; 450 u32 val; 451 452 if (!i2s) 453 return; 454 455 if (is_secondary(i2s)) 456 fic = i2s->addr + I2SFICS; 457 else 458 fic = i2s->addr + I2SFIC; 459 460 /* Flush the FIFO */ 461 writel(readl(fic) | flush, fic); 462 463 /* Be patient */ 464 val = msecs_to_loops(1) / 1000; /* 1 usec */ 465 while (--val) 466 cpu_relax(); 467 468 writel(readl(fic) & ~flush, fic); 469 } 470 471 static int i2s_set_sysclk(struct snd_soc_dai *dai, 472 int clk_id, unsigned int rfs, int dir) 473 { 474 struct i2s_dai *i2s = to_info(dai); 475 struct i2s_dai *other = get_other_dai(i2s); 476 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs; 477 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off; 478 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off; 479 u32 mod, mask, val = 0; 480 unsigned long flags; 481 int ret = 0; 482 483 pm_runtime_get_sync(dai->dev); 484 485 spin_lock_irqsave(i2s->lock, flags); 486 mod = readl(i2s->addr + I2SMOD); 487 spin_unlock_irqrestore(i2s->lock, flags); 488 489 switch (clk_id) { 490 case SAMSUNG_I2S_OPCLK: 491 mask = MOD_OPCLK_MASK; 492 val = (dir << MOD_OPCLK_SHIFT) & MOD_OPCLK_MASK; 493 break; 494 case SAMSUNG_I2S_CDCLK: 495 mask = 1 << i2s_regs->cdclkcon_off; 496 /* Shouldn't matter in GATING(CLOCK_IN) mode */ 497 if (dir == SND_SOC_CLOCK_IN) 498 rfs = 0; 499 500 if ((rfs && other && other->rfs && (other->rfs != rfs)) || 501 (any_active(i2s) && 502 (((dir == SND_SOC_CLOCK_IN) 503 && !(mod & cdcon_mask)) || 504 ((dir == SND_SOC_CLOCK_OUT) 505 && (mod & cdcon_mask))))) { 506 dev_err(&i2s->pdev->dev, 507 "%s:%d Other DAI busy\n", __func__, __LINE__); 508 ret = -EAGAIN; 509 goto err; 510 } 511 512 if (dir == SND_SOC_CLOCK_IN) 513 val = 1 << i2s_regs->cdclkcon_off; 514 515 i2s->rfs = rfs; 516 break; 517 518 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */ 519 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */ 520 mask = 1 << i2s_regs->rclksrc_off; 521 522 if ((i2s->quirks & QUIRK_NO_MUXPSR) 523 || (clk_id == SAMSUNG_I2S_RCLKSRC_0)) 524 clk_id = 0; 525 else 526 clk_id = 1; 527 528 if (!any_active(i2s)) { 529 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) { 530 if ((clk_id && !(mod & rsrc_mask)) || 531 (!clk_id && (mod & rsrc_mask))) { 532 clk_disable_unprepare(i2s->op_clk); 533 clk_put(i2s->op_clk); 534 } else { 535 i2s->rclk_srcrate = 536 clk_get_rate(i2s->op_clk); 537 goto done; 538 } 539 } 540 541 if (clk_id) 542 i2s->op_clk = clk_get(&i2s->pdev->dev, 543 "i2s_opclk1"); 544 else 545 i2s->op_clk = clk_get(&i2s->pdev->dev, 546 "i2s_opclk0"); 547 548 if (WARN_ON(IS_ERR(i2s->op_clk))) { 549 ret = PTR_ERR(i2s->op_clk); 550 i2s->op_clk = NULL; 551 goto err; 552 } 553 554 ret = clk_prepare_enable(i2s->op_clk); 555 if (ret) { 556 clk_put(i2s->op_clk); 557 i2s->op_clk = NULL; 558 goto err; 559 } 560 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk); 561 562 /* Over-ride the other's */ 563 if (other) { 564 other->op_clk = i2s->op_clk; 565 other->rclk_srcrate = i2s->rclk_srcrate; 566 } 567 } else if ((!clk_id && (mod & rsrc_mask)) 568 || (clk_id && !(mod & rsrc_mask))) { 569 dev_err(&i2s->pdev->dev, 570 "%s:%d Other DAI busy\n", __func__, __LINE__); 571 ret = -EAGAIN; 572 goto err; 573 } else { 574 /* Call can't be on the active DAI */ 575 i2s->op_clk = other->op_clk; 576 i2s->rclk_srcrate = other->rclk_srcrate; 577 goto done; 578 } 579 580 if (clk_id == 1) 581 val = 1 << i2s_regs->rclksrc_off; 582 break; 583 default: 584 dev_err(&i2s->pdev->dev, "We don't serve that!\n"); 585 ret = -EINVAL; 586 goto err; 587 } 588 589 spin_lock_irqsave(i2s->lock, flags); 590 mod = readl(i2s->addr + I2SMOD); 591 mod = (mod & ~mask) | val; 592 writel(mod, i2s->addr + I2SMOD); 593 spin_unlock_irqrestore(i2s->lock, flags); 594 done: 595 pm_runtime_put(dai->dev); 596 597 return 0; 598 err: 599 pm_runtime_put(dai->dev); 600 return ret; 601 } 602 603 static int i2s_set_fmt(struct snd_soc_dai *dai, 604 unsigned int fmt) 605 { 606 struct i2s_dai *i2s = to_info(dai); 607 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave; 608 u32 mod, tmp = 0; 609 unsigned long flags; 610 611 lrp_shift = i2s->variant_regs->lrp_off; 612 sdf_shift = i2s->variant_regs->sdf_off; 613 mod_slave = 1 << i2s->variant_regs->mss_off; 614 615 sdf_mask = MOD_SDF_MASK << sdf_shift; 616 lrp_rlow = MOD_LR_RLOW << lrp_shift; 617 618 /* Format is priority */ 619 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 620 case SND_SOC_DAIFMT_RIGHT_J: 621 tmp |= lrp_rlow; 622 tmp |= (MOD_SDF_MSB << sdf_shift); 623 break; 624 case SND_SOC_DAIFMT_LEFT_J: 625 tmp |= lrp_rlow; 626 tmp |= (MOD_SDF_LSB << sdf_shift); 627 break; 628 case SND_SOC_DAIFMT_I2S: 629 tmp |= (MOD_SDF_IIS << sdf_shift); 630 break; 631 default: 632 dev_err(&i2s->pdev->dev, "Format not supported\n"); 633 return -EINVAL; 634 } 635 636 /* 637 * INV flag is relative to the FORMAT flag - if set it simply 638 * flips the polarity specified by the Standard 639 */ 640 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 641 case SND_SOC_DAIFMT_NB_NF: 642 break; 643 case SND_SOC_DAIFMT_NB_IF: 644 if (tmp & lrp_rlow) 645 tmp &= ~lrp_rlow; 646 else 647 tmp |= lrp_rlow; 648 break; 649 default: 650 dev_err(&i2s->pdev->dev, "Polarity not supported\n"); 651 return -EINVAL; 652 } 653 654 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 655 case SND_SOC_DAIFMT_CBM_CFM: 656 tmp |= mod_slave; 657 break; 658 case SND_SOC_DAIFMT_CBS_CFS: 659 /* 660 * Set default source clock in Master mode, only when the 661 * CLK_I2S_RCLK_SRC clock is not exposed so we ensure any 662 * clock configuration assigned in DT is not overwritten. 663 */ 664 if (i2s->rclk_srcrate == 0 && i2s->clk_data.clks == NULL) 665 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0, 666 0, SND_SOC_CLOCK_IN); 667 break; 668 default: 669 dev_err(&i2s->pdev->dev, "master/slave format not supported\n"); 670 return -EINVAL; 671 } 672 673 pm_runtime_get_sync(dai->dev); 674 spin_lock_irqsave(i2s->lock, flags); 675 mod = readl(i2s->addr + I2SMOD); 676 /* 677 * Don't change the I2S mode if any controller is active on this 678 * channel. 679 */ 680 if (any_active(i2s) && 681 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) { 682 spin_unlock_irqrestore(i2s->lock, flags); 683 pm_runtime_put(dai->dev); 684 dev_err(&i2s->pdev->dev, 685 "%s:%d Other DAI busy\n", __func__, __LINE__); 686 return -EAGAIN; 687 } 688 689 mod &= ~(sdf_mask | lrp_rlow | mod_slave); 690 mod |= tmp; 691 writel(mod, i2s->addr + I2SMOD); 692 spin_unlock_irqrestore(i2s->lock, flags); 693 pm_runtime_put(dai->dev); 694 695 return 0; 696 } 697 698 static int i2s_hw_params(struct snd_pcm_substream *substream, 699 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 700 { 701 struct i2s_dai *i2s = to_info(dai); 702 u32 mod, mask = 0, val = 0; 703 unsigned long flags; 704 705 WARN_ON(!pm_runtime_active(dai->dev)); 706 707 if (!is_secondary(i2s)) 708 mask |= (MOD_DC2_EN | MOD_DC1_EN); 709 710 switch (params_channels(params)) { 711 case 6: 712 val |= MOD_DC2_EN; 713 /* fall through */ 714 case 4: 715 val |= MOD_DC1_EN; 716 break; 717 case 2: 718 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 719 i2s->dma_playback.addr_width = 4; 720 else 721 i2s->dma_capture.addr_width = 4; 722 break; 723 case 1: 724 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 725 i2s->dma_playback.addr_width = 2; 726 else 727 i2s->dma_capture.addr_width = 2; 728 729 break; 730 default: 731 dev_err(&i2s->pdev->dev, "%d channels not supported\n", 732 params_channels(params)); 733 return -EINVAL; 734 } 735 736 if (is_secondary(i2s)) 737 mask |= MOD_BLCS_MASK; 738 else 739 mask |= MOD_BLCP_MASK; 740 741 if (is_manager(i2s)) 742 mask |= MOD_BLC_MASK; 743 744 switch (params_width(params)) { 745 case 8: 746 if (is_secondary(i2s)) 747 val |= MOD_BLCS_8BIT; 748 else 749 val |= MOD_BLCP_8BIT; 750 if (is_manager(i2s)) 751 val |= MOD_BLC_8BIT; 752 break; 753 case 16: 754 if (is_secondary(i2s)) 755 val |= MOD_BLCS_16BIT; 756 else 757 val |= MOD_BLCP_16BIT; 758 if (is_manager(i2s)) 759 val |= MOD_BLC_16BIT; 760 break; 761 case 24: 762 if (is_secondary(i2s)) 763 val |= MOD_BLCS_24BIT; 764 else 765 val |= MOD_BLCP_24BIT; 766 if (is_manager(i2s)) 767 val |= MOD_BLC_24BIT; 768 break; 769 default: 770 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n", 771 params_format(params)); 772 return -EINVAL; 773 } 774 775 spin_lock_irqsave(i2s->lock, flags); 776 mod = readl(i2s->addr + I2SMOD); 777 mod = (mod & ~mask) | val; 778 writel(mod, i2s->addr + I2SMOD); 779 spin_unlock_irqrestore(i2s->lock, flags); 780 781 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture); 782 783 i2s->frmclk = params_rate(params); 784 785 return 0; 786 } 787 788 /* We set constraints on the substream acc to the version of I2S */ 789 static int i2s_startup(struct snd_pcm_substream *substream, 790 struct snd_soc_dai *dai) 791 { 792 struct i2s_dai *i2s = to_info(dai); 793 struct i2s_dai *other = get_other_dai(i2s); 794 unsigned long flags; 795 796 pm_runtime_get_sync(dai->dev); 797 798 spin_lock_irqsave(&lock, flags); 799 800 i2s->mode |= DAI_OPENED; 801 802 if (is_manager(other)) 803 i2s->mode &= ~DAI_MANAGER; 804 else 805 i2s->mode |= DAI_MANAGER; 806 807 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR)) 808 writel(CON_RSTCLR, i2s->addr + I2SCON); 809 810 spin_unlock_irqrestore(&lock, flags); 811 812 return 0; 813 } 814 815 static void i2s_shutdown(struct snd_pcm_substream *substream, 816 struct snd_soc_dai *dai) 817 { 818 struct i2s_dai *i2s = to_info(dai); 819 struct i2s_dai *other = get_other_dai(i2s); 820 unsigned long flags; 821 822 spin_lock_irqsave(&lock, flags); 823 824 i2s->mode &= ~DAI_OPENED; 825 i2s->mode &= ~DAI_MANAGER; 826 827 if (is_opened(other)) 828 other->mode |= DAI_MANAGER; 829 830 /* Reset any constraint on RFS and BFS */ 831 i2s->rfs = 0; 832 i2s->bfs = 0; 833 834 spin_unlock_irqrestore(&lock, flags); 835 836 pm_runtime_put(dai->dev); 837 } 838 839 static int config_setup(struct i2s_dai *i2s) 840 { 841 struct i2s_dai *other = get_other_dai(i2s); 842 unsigned rfs, bfs, blc; 843 u32 psr; 844 845 blc = get_blc(i2s); 846 847 bfs = i2s->bfs; 848 849 if (!bfs && other) 850 bfs = other->bfs; 851 852 /* Select least possible multiple(2) if no constraint set */ 853 if (!bfs) 854 bfs = blc * 2; 855 856 rfs = i2s->rfs; 857 858 if (!rfs && other) 859 rfs = other->rfs; 860 861 if ((rfs == 256 || rfs == 512) && (blc == 24)) { 862 dev_err(&i2s->pdev->dev, 863 "%d-RFS not supported for 24-blc\n", rfs); 864 return -EINVAL; 865 } 866 867 if (!rfs) { 868 if (bfs == 16 || bfs == 32) 869 rfs = 256; 870 else 871 rfs = 384; 872 } 873 874 /* If already setup and running */ 875 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) { 876 dev_err(&i2s->pdev->dev, 877 "%s:%d Other DAI busy\n", __func__, __LINE__); 878 return -EAGAIN; 879 } 880 881 set_bfs(i2s, bfs); 882 set_rfs(i2s, rfs); 883 884 /* Don't bother with PSR in Slave mode */ 885 if (is_slave(i2s)) 886 return 0; 887 888 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) { 889 struct clk *rclksrc = i2s->clk_table[CLK_I2S_RCLK_SRC]; 890 891 if (rclksrc && !IS_ERR(rclksrc)) 892 i2s->rclk_srcrate = clk_get_rate(rclksrc); 893 894 psr = i2s->rclk_srcrate / i2s->frmclk / rfs; 895 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR); 896 dev_dbg(&i2s->pdev->dev, 897 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n", 898 i2s->rclk_srcrate, psr, rfs, bfs); 899 } 900 901 return 0; 902 } 903 904 static int i2s_trigger(struct snd_pcm_substream *substream, 905 int cmd, struct snd_soc_dai *dai) 906 { 907 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); 908 struct snd_soc_pcm_runtime *rtd = substream->private_data; 909 struct i2s_dai *i2s = to_info(rtd->cpu_dai); 910 unsigned long flags; 911 912 switch (cmd) { 913 case SNDRV_PCM_TRIGGER_START: 914 case SNDRV_PCM_TRIGGER_RESUME: 915 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 916 pm_runtime_get_sync(dai->dev); 917 spin_lock_irqsave(i2s->lock, flags); 918 919 if (config_setup(i2s)) { 920 spin_unlock_irqrestore(i2s->lock, flags); 921 return -EINVAL; 922 } 923 924 if (capture) 925 i2s_rxctrl(i2s, 1); 926 else 927 i2s_txctrl(i2s, 1); 928 929 spin_unlock_irqrestore(i2s->lock, flags); 930 break; 931 case SNDRV_PCM_TRIGGER_STOP: 932 case SNDRV_PCM_TRIGGER_SUSPEND: 933 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 934 spin_lock_irqsave(i2s->lock, flags); 935 936 if (capture) { 937 i2s_rxctrl(i2s, 0); 938 i2s_fifo(i2s, FIC_RXFLUSH); 939 } else { 940 i2s_txctrl(i2s, 0); 941 i2s_fifo(i2s, FIC_TXFLUSH); 942 } 943 944 spin_unlock_irqrestore(i2s->lock, flags); 945 pm_runtime_put(dai->dev); 946 break; 947 } 948 949 return 0; 950 } 951 952 static int i2s_set_clkdiv(struct snd_soc_dai *dai, 953 int div_id, int div) 954 { 955 struct i2s_dai *i2s = to_info(dai); 956 struct i2s_dai *other = get_other_dai(i2s); 957 958 switch (div_id) { 959 case SAMSUNG_I2S_DIV_BCLK: 960 pm_runtime_get_sync(dai->dev); 961 if ((any_active(i2s) && div && (get_bfs(i2s) != div)) 962 || (other && other->bfs && (other->bfs != div))) { 963 pm_runtime_put(dai->dev); 964 dev_err(&i2s->pdev->dev, 965 "%s:%d Other DAI busy\n", __func__, __LINE__); 966 return -EAGAIN; 967 } 968 i2s->bfs = div; 969 pm_runtime_put(dai->dev); 970 break; 971 default: 972 dev_err(&i2s->pdev->dev, 973 "Invalid clock divider(%d)\n", div_id); 974 return -EINVAL; 975 } 976 977 return 0; 978 } 979 980 static snd_pcm_sframes_t 981 i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 982 { 983 struct i2s_dai *i2s = to_info(dai); 984 u32 reg = readl(i2s->addr + I2SFIC); 985 snd_pcm_sframes_t delay; 986 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs; 987 988 WARN_ON(!pm_runtime_active(dai->dev)); 989 990 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 991 delay = FIC_RXCOUNT(reg); 992 else if (is_secondary(i2s)) 993 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS)); 994 else 995 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f; 996 997 return delay; 998 } 999 1000 #ifdef CONFIG_PM 1001 static int i2s_suspend(struct snd_soc_dai *dai) 1002 { 1003 return pm_runtime_force_suspend(dai->dev); 1004 } 1005 1006 static int i2s_resume(struct snd_soc_dai *dai) 1007 { 1008 return pm_runtime_force_resume(dai->dev); 1009 } 1010 #else 1011 #define i2s_suspend NULL 1012 #define i2s_resume NULL 1013 #endif 1014 1015 static int samsung_i2s_dai_probe(struct snd_soc_dai *dai) 1016 { 1017 struct i2s_dai *i2s = to_info(dai); 1018 struct i2s_dai *other = get_other_dai(i2s); 1019 unsigned long flags; 1020 1021 pm_runtime_get_sync(dai->dev); 1022 1023 if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */ 1024 snd_soc_dai_init_dma_data(dai, &other->sec_dai->dma_playback, 1025 NULL); 1026 } else { 1027 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, 1028 &i2s->dma_capture); 1029 1030 if (i2s->quirks & QUIRK_NEED_RSTCLR) 1031 writel(CON_RSTCLR, i2s->addr + I2SCON); 1032 1033 if (i2s->quirks & QUIRK_SUPPORTS_IDMA) 1034 idma_reg_addr_init(i2s->addr, 1035 i2s->sec_dai->idma_playback.addr); 1036 } 1037 1038 /* Reset any constraint on RFS and BFS */ 1039 i2s->rfs = 0; 1040 i2s->bfs = 0; 1041 i2s->rclk_srcrate = 0; 1042 1043 spin_lock_irqsave(i2s->lock, flags); 1044 i2s_txctrl(i2s, 0); 1045 i2s_rxctrl(i2s, 0); 1046 i2s_fifo(i2s, FIC_TXFLUSH); 1047 i2s_fifo(other, FIC_TXFLUSH); 1048 i2s_fifo(i2s, FIC_RXFLUSH); 1049 spin_unlock_irqrestore(i2s->lock, flags); 1050 1051 /* Gate CDCLK by default */ 1052 if (!is_opened(other)) 1053 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK, 1054 0, SND_SOC_CLOCK_IN); 1055 pm_runtime_put(dai->dev); 1056 1057 return 0; 1058 } 1059 1060 static int samsung_i2s_dai_remove(struct snd_soc_dai *dai) 1061 { 1062 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai); 1063 unsigned long flags; 1064 1065 pm_runtime_get_sync(dai->dev); 1066 1067 if (!is_secondary(i2s)) { 1068 if (i2s->quirks & QUIRK_NEED_RSTCLR) { 1069 spin_lock_irqsave(i2s->lock, flags); 1070 writel(0, i2s->addr + I2SCON); 1071 spin_unlock_irqrestore(i2s->lock, flags); 1072 } 1073 } 1074 1075 pm_runtime_put(dai->dev); 1076 1077 return 0; 1078 } 1079 1080 static const struct snd_soc_dai_ops samsung_i2s_dai_ops = { 1081 .trigger = i2s_trigger, 1082 .hw_params = i2s_hw_params, 1083 .set_fmt = i2s_set_fmt, 1084 .set_clkdiv = i2s_set_clkdiv, 1085 .set_sysclk = i2s_set_sysclk, 1086 .startup = i2s_startup, 1087 .shutdown = i2s_shutdown, 1088 .delay = i2s_delay, 1089 }; 1090 1091 static const struct snd_soc_component_driver samsung_i2s_component = { 1092 .name = "samsung-i2s", 1093 }; 1094 1095 #define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1096 SNDRV_PCM_FMTBIT_S16_LE | \ 1097 SNDRV_PCM_FMTBIT_S24_LE) 1098 1099 static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev, 1100 const struct samsung_i2s_dai_data *i2s_dai_data, 1101 bool sec) 1102 { 1103 struct i2s_dai *i2s; 1104 1105 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL); 1106 if (i2s == NULL) 1107 return NULL; 1108 1109 i2s->pdev = pdev; 1110 i2s->pri_dai = NULL; 1111 i2s->sec_dai = NULL; 1112 i2s->i2s_dai_drv.id = 1; 1113 i2s->i2s_dai_drv.symmetric_rates = 1; 1114 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe; 1115 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove; 1116 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops; 1117 i2s->i2s_dai_drv.suspend = i2s_suspend; 1118 i2s->i2s_dai_drv.resume = i2s_resume; 1119 i2s->i2s_dai_drv.playback.channels_min = 1; 1120 i2s->i2s_dai_drv.playback.channels_max = 2; 1121 i2s->i2s_dai_drv.playback.rates = i2s_dai_data->pcm_rates; 1122 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS; 1123 1124 if (!sec) { 1125 i2s->i2s_dai_drv.name = SAMSUNG_I2S_DAI; 1126 i2s->i2s_dai_drv.capture.channels_min = 1; 1127 i2s->i2s_dai_drv.capture.channels_max = 2; 1128 i2s->i2s_dai_drv.capture.rates = i2s_dai_data->pcm_rates; 1129 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS; 1130 } else { 1131 i2s->i2s_dai_drv.name = SAMSUNG_I2S_DAI_SEC; 1132 } 1133 return i2s; 1134 } 1135 1136 #ifdef CONFIG_PM 1137 static int i2s_runtime_suspend(struct device *dev) 1138 { 1139 struct i2s_dai *i2s = dev_get_drvdata(dev); 1140 1141 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD); 1142 i2s->suspend_i2scon = readl(i2s->addr + I2SCON); 1143 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR); 1144 1145 if (i2s->op_clk) 1146 clk_disable_unprepare(i2s->op_clk); 1147 clk_disable_unprepare(i2s->clk); 1148 1149 return 0; 1150 } 1151 1152 static int i2s_runtime_resume(struct device *dev) 1153 { 1154 struct i2s_dai *i2s = dev_get_drvdata(dev); 1155 int ret; 1156 1157 ret = clk_prepare_enable(i2s->clk); 1158 if (ret) 1159 return ret; 1160 1161 if (i2s->op_clk) { 1162 ret = clk_prepare_enable(i2s->op_clk); 1163 if (ret) { 1164 clk_disable_unprepare(i2s->clk); 1165 return ret; 1166 } 1167 } 1168 1169 writel(i2s->suspend_i2scon, i2s->addr + I2SCON); 1170 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD); 1171 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR); 1172 1173 return 0; 1174 } 1175 #endif /* CONFIG_PM */ 1176 1177 static void i2s_unregister_clocks(struct i2s_dai *i2s) 1178 { 1179 int i; 1180 1181 for (i = 0; i < i2s->clk_data.clk_num; i++) { 1182 if (!IS_ERR(i2s->clk_table[i])) 1183 clk_unregister(i2s->clk_table[i]); 1184 } 1185 } 1186 1187 static void i2s_unregister_clock_provider(struct platform_device *pdev) 1188 { 1189 struct i2s_dai *i2s = dev_get_drvdata(&pdev->dev); 1190 1191 of_clk_del_provider(pdev->dev.of_node); 1192 i2s_unregister_clocks(i2s); 1193 } 1194 1195 static int i2s_register_clock_provider(struct platform_device *pdev) 1196 { 1197 const char * const i2s_clk_desc[] = { "cdclk", "rclk_src", "prescaler" }; 1198 const char *clk_name[2] = { "i2s_opclk0", "i2s_opclk1" }; 1199 const char *p_names[2] = { NULL }; 1200 struct device *dev = &pdev->dev; 1201 struct i2s_dai *i2s = dev_get_drvdata(dev); 1202 const struct samsung_i2s_variant_regs *reg_info = i2s->variant_regs; 1203 const char *i2s_clk_name[ARRAY_SIZE(i2s_clk_desc)]; 1204 struct clk *rclksrc; 1205 int ret, i; 1206 1207 /* Register the clock provider only if it's expected in the DTB */ 1208 if (!of_find_property(dev->of_node, "#clock-cells", NULL)) 1209 return 0; 1210 1211 /* Get the RCLKSRC mux clock parent clock names */ 1212 for (i = 0; i < ARRAY_SIZE(p_names); i++) { 1213 rclksrc = clk_get(dev, clk_name[i]); 1214 if (IS_ERR(rclksrc)) 1215 continue; 1216 p_names[i] = __clk_get_name(rclksrc); 1217 clk_put(rclksrc); 1218 } 1219 1220 for (i = 0; i < ARRAY_SIZE(i2s_clk_desc); i++) { 1221 i2s_clk_name[i] = devm_kasprintf(dev, GFP_KERNEL, "%s_%s", 1222 dev_name(dev), i2s_clk_desc[i]); 1223 if (!i2s_clk_name[i]) 1224 return -ENOMEM; 1225 } 1226 1227 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) { 1228 /* Activate the prescaler */ 1229 u32 val = readl(i2s->addr + I2SPSR); 1230 writel(val | PSR_PSREN, i2s->addr + I2SPSR); 1231 1232 i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev, 1233 i2s_clk_name[CLK_I2S_RCLK_SRC], p_names, 1234 ARRAY_SIZE(p_names), 1235 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, 1236 i2s->addr + I2SMOD, reg_info->rclksrc_off, 1237 1, 0, i2s->lock); 1238 1239 i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev, 1240 i2s_clk_name[CLK_I2S_RCLK_PSR], 1241 i2s_clk_name[CLK_I2S_RCLK_SRC], 1242 CLK_SET_RATE_PARENT, 1243 i2s->addr + I2SPSR, 8, 6, 0, i2s->lock); 1244 1245 p_names[0] = i2s_clk_name[CLK_I2S_RCLK_PSR]; 1246 i2s->clk_data.clk_num = 2; 1247 } 1248 1249 i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev, 1250 i2s_clk_name[CLK_I2S_CDCLK], p_names[0], 1251 CLK_SET_RATE_PARENT, 1252 i2s->addr + I2SMOD, reg_info->cdclkcon_off, 1253 CLK_GATE_SET_TO_DISABLE, i2s->lock); 1254 1255 i2s->clk_data.clk_num += 1; 1256 i2s->clk_data.clks = i2s->clk_table; 1257 1258 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, 1259 &i2s->clk_data); 1260 if (ret < 0) { 1261 dev_err(dev, "failed to add clock provider: %d\n", ret); 1262 i2s_unregister_clocks(i2s); 1263 } 1264 1265 return ret; 1266 } 1267 1268 static int samsung_i2s_probe(struct platform_device *pdev) 1269 { 1270 struct i2s_dai *pri_dai, *sec_dai = NULL; 1271 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data; 1272 struct resource *res; 1273 u32 regs_base, quirks = 0, idma_addr = 0; 1274 struct device_node *np = pdev->dev.of_node; 1275 const struct samsung_i2s_dai_data *i2s_dai_data; 1276 int ret; 1277 1278 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) 1279 i2s_dai_data = of_device_get_match_data(&pdev->dev); 1280 else 1281 i2s_dai_data = (struct samsung_i2s_dai_data *) 1282 platform_get_device_id(pdev)->driver_data; 1283 1284 pri_dai = i2s_alloc_dai(pdev, i2s_dai_data, false); 1285 if (!pri_dai) { 1286 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n"); 1287 return -ENOMEM; 1288 } 1289 1290 spin_lock_init(&pri_dai->spinlock); 1291 pri_dai->lock = &pri_dai->spinlock; 1292 1293 if (!np) { 1294 if (i2s_pdata == NULL) { 1295 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n"); 1296 return -EINVAL; 1297 } 1298 1299 pri_dai->dma_playback.filter_data = i2s_pdata->dma_playback; 1300 pri_dai->dma_capture.filter_data = i2s_pdata->dma_capture; 1301 pri_dai->filter = i2s_pdata->dma_filter; 1302 1303 quirks = i2s_pdata->type.quirks; 1304 idma_addr = i2s_pdata->type.idma_addr; 1305 } else { 1306 quirks = i2s_dai_data->quirks; 1307 if (of_property_read_u32(np, "samsung,idma-addr", 1308 &idma_addr)) { 1309 if (quirks & QUIRK_SUPPORTS_IDMA) { 1310 dev_info(&pdev->dev, "idma address is not"\ 1311 "specified"); 1312 } 1313 } 1314 } 1315 quirks &= ~(QUIRK_SEC_DAI | QUIRK_SUPPORTS_IDMA); 1316 1317 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1318 pri_dai->addr = devm_ioremap_resource(&pdev->dev, res); 1319 if (IS_ERR(pri_dai->addr)) 1320 return PTR_ERR(pri_dai->addr); 1321 1322 regs_base = res->start; 1323 1324 pri_dai->clk = devm_clk_get(&pdev->dev, "iis"); 1325 if (IS_ERR(pri_dai->clk)) { 1326 dev_err(&pdev->dev, "Failed to get iis clock\n"); 1327 return PTR_ERR(pri_dai->clk); 1328 } 1329 1330 ret = clk_prepare_enable(pri_dai->clk); 1331 if (ret != 0) { 1332 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret); 1333 return ret; 1334 } 1335 pri_dai->dma_playback.addr = regs_base + I2STXD; 1336 pri_dai->dma_capture.addr = regs_base + I2SRXD; 1337 pri_dai->dma_playback.chan_name = "tx"; 1338 pri_dai->dma_capture.chan_name = "rx"; 1339 pri_dai->dma_playback.addr_width = 4; 1340 pri_dai->dma_capture.addr_width = 4; 1341 pri_dai->quirks = quirks; 1342 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs; 1343 1344 if (quirks & QUIRK_PRI_6CHAN) 1345 pri_dai->i2s_dai_drv.playback.channels_max = 6; 1346 1347 ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter, 1348 NULL, NULL); 1349 if (ret < 0) 1350 goto err_disable_clk; 1351 1352 ret = devm_snd_soc_register_component(&pdev->dev, 1353 &samsung_i2s_component, 1354 &pri_dai->i2s_dai_drv, 1); 1355 if (ret < 0) 1356 goto err_disable_clk; 1357 1358 if (quirks & QUIRK_SEC_DAI) { 1359 sec_dai = i2s_alloc_dai(pdev, i2s_dai_data, true); 1360 if (!sec_dai) { 1361 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n"); 1362 ret = -ENOMEM; 1363 goto err_disable_clk; 1364 } 1365 1366 sec_dai->lock = &pri_dai->spinlock; 1367 sec_dai->variant_regs = pri_dai->variant_regs; 1368 sec_dai->dma_playback.addr = regs_base + I2STXDS; 1369 sec_dai->dma_playback.chan_name = "tx-sec"; 1370 1371 if (!np) { 1372 sec_dai->dma_playback.filter_data = i2s_pdata->dma_play_sec; 1373 sec_dai->filter = i2s_pdata->dma_filter; 1374 } 1375 1376 sec_dai->dma_playback.addr_width = 4; 1377 sec_dai->addr = pri_dai->addr; 1378 sec_dai->clk = pri_dai->clk; 1379 sec_dai->quirks = quirks; 1380 sec_dai->idma_playback.addr = idma_addr; 1381 sec_dai->pri_dai = pri_dai; 1382 pri_dai->sec_dai = sec_dai; 1383 1384 ret = samsung_asoc_dma_platform_register(&pdev->dev, 1385 sec_dai->filter, "tx-sec", NULL); 1386 if (ret < 0) 1387 goto err_disable_clk; 1388 1389 ret = devm_snd_soc_register_component(&pdev->dev, 1390 &samsung_i2s_component, 1391 &sec_dai->i2s_dai_drv, 1); 1392 if (ret < 0) 1393 goto err_disable_clk; 1394 } 1395 1396 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) { 1397 dev_err(&pdev->dev, "Unable to configure gpio\n"); 1398 ret = -EINVAL; 1399 goto err_disable_clk; 1400 } 1401 1402 dev_set_drvdata(&pdev->dev, pri_dai); 1403 1404 pm_runtime_set_active(&pdev->dev); 1405 pm_runtime_enable(&pdev->dev); 1406 1407 ret = i2s_register_clock_provider(pdev); 1408 if (ret < 0) 1409 goto err_disable_pm; 1410 1411 pri_dai->op_clk = clk_get_parent(pri_dai->clk_table[CLK_I2S_RCLK_SRC]); 1412 1413 return 0; 1414 1415 err_disable_pm: 1416 pm_runtime_disable(&pdev->dev); 1417 err_disable_clk: 1418 clk_disable_unprepare(pri_dai->clk); 1419 return ret; 1420 } 1421 1422 static int samsung_i2s_remove(struct platform_device *pdev) 1423 { 1424 struct i2s_dai *pri_dai; 1425 1426 pri_dai = dev_get_drvdata(&pdev->dev); 1427 1428 pm_runtime_get_sync(&pdev->dev); 1429 pm_runtime_disable(&pdev->dev); 1430 1431 i2s_unregister_clock_provider(pdev); 1432 clk_disable_unprepare(pri_dai->clk); 1433 pm_runtime_put_noidle(&pdev->dev); 1434 1435 return 0; 1436 } 1437 1438 static const struct samsung_i2s_variant_regs i2sv3_regs = { 1439 .bfs_off = 1, 1440 .rfs_off = 3, 1441 .sdf_off = 5, 1442 .txr_off = 8, 1443 .rclksrc_off = 10, 1444 .mss_off = 11, 1445 .cdclkcon_off = 12, 1446 .lrp_off = 7, 1447 .bfs_mask = 0x3, 1448 .rfs_mask = 0x3, 1449 .ftx0cnt_off = 8, 1450 }; 1451 1452 static const struct samsung_i2s_variant_regs i2sv6_regs = { 1453 .bfs_off = 0, 1454 .rfs_off = 4, 1455 .sdf_off = 6, 1456 .txr_off = 8, 1457 .rclksrc_off = 10, 1458 .mss_off = 11, 1459 .cdclkcon_off = 12, 1460 .lrp_off = 15, 1461 .bfs_mask = 0xf, 1462 .rfs_mask = 0x3, 1463 .ftx0cnt_off = 8, 1464 }; 1465 1466 static const struct samsung_i2s_variant_regs i2sv7_regs = { 1467 .bfs_off = 0, 1468 .rfs_off = 4, 1469 .sdf_off = 7, 1470 .txr_off = 9, 1471 .rclksrc_off = 11, 1472 .mss_off = 12, 1473 .cdclkcon_off = 22, 1474 .lrp_off = 15, 1475 .bfs_mask = 0xf, 1476 .rfs_mask = 0x7, 1477 .ftx0cnt_off = 0, 1478 }; 1479 1480 static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = { 1481 .bfs_off = 0, 1482 .rfs_off = 3, 1483 .sdf_off = 6, 1484 .txr_off = 8, 1485 .rclksrc_off = 10, 1486 .mss_off = 11, 1487 .cdclkcon_off = 12, 1488 .lrp_off = 15, 1489 .bfs_mask = 0x7, 1490 .rfs_mask = 0x7, 1491 .ftx0cnt_off = 8, 1492 }; 1493 1494 static const struct samsung_i2s_dai_data i2sv3_dai_type = { 1495 .quirks = QUIRK_NO_MUXPSR, 1496 .pcm_rates = SNDRV_PCM_RATE_8000_96000, 1497 .i2s_variant_regs = &i2sv3_regs, 1498 }; 1499 1500 static const struct samsung_i2s_dai_data i2sv5_dai_type = { 1501 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR | 1502 QUIRK_SUPPORTS_IDMA, 1503 .pcm_rates = SNDRV_PCM_RATE_8000_96000, 1504 .i2s_variant_regs = &i2sv3_regs, 1505 }; 1506 1507 static const struct samsung_i2s_dai_data i2sv6_dai_type = { 1508 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR | 1509 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA, 1510 .pcm_rates = SNDRV_PCM_RATE_8000_96000, 1511 .i2s_variant_regs = &i2sv6_regs, 1512 }; 1513 1514 static const struct samsung_i2s_dai_data i2sv7_dai_type = { 1515 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR | 1516 QUIRK_SUPPORTS_TDM, 1517 .pcm_rates = SNDRV_PCM_RATE_8000_192000, 1518 .i2s_variant_regs = &i2sv7_regs, 1519 }; 1520 1521 static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = { 1522 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR, 1523 .pcm_rates = SNDRV_PCM_RATE_8000_96000, 1524 .i2s_variant_regs = &i2sv5_i2s1_regs, 1525 }; 1526 1527 static const struct platform_device_id samsung_i2s_driver_ids[] = { 1528 { 1529 .name = "samsung-i2s", 1530 .driver_data = (kernel_ulong_t)&i2sv3_dai_type, 1531 }, 1532 {}, 1533 }; 1534 MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids); 1535 1536 #ifdef CONFIG_OF 1537 static const struct of_device_id exynos_i2s_match[] = { 1538 { 1539 .compatible = "samsung,s3c6410-i2s", 1540 .data = &i2sv3_dai_type, 1541 }, { 1542 .compatible = "samsung,s5pv210-i2s", 1543 .data = &i2sv5_dai_type, 1544 }, { 1545 .compatible = "samsung,exynos5420-i2s", 1546 .data = &i2sv6_dai_type, 1547 }, { 1548 .compatible = "samsung,exynos7-i2s", 1549 .data = &i2sv7_dai_type, 1550 }, { 1551 .compatible = "samsung,exynos7-i2s1", 1552 .data = &i2sv5_dai_type_i2s1, 1553 }, 1554 {}, 1555 }; 1556 MODULE_DEVICE_TABLE(of, exynos_i2s_match); 1557 #endif 1558 1559 static const struct dev_pm_ops samsung_i2s_pm = { 1560 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, 1561 i2s_runtime_resume, NULL) 1562 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1563 pm_runtime_force_resume) 1564 }; 1565 1566 static struct platform_driver samsung_i2s_driver = { 1567 .probe = samsung_i2s_probe, 1568 .remove = samsung_i2s_remove, 1569 .id_table = samsung_i2s_driver_ids, 1570 .driver = { 1571 .name = "samsung-i2s", 1572 .of_match_table = of_match_ptr(exynos_i2s_match), 1573 .pm = &samsung_i2s_pm, 1574 }, 1575 }; 1576 1577 module_platform_driver(samsung_i2s_driver); 1578 1579 /* Module information */ 1580 MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>"); 1581 MODULE_DESCRIPTION("Samsung I2S Interface"); 1582 MODULE_ALIAS("platform:samsung-i2s"); 1583 MODULE_LICENSE("GPL"); 1584