1 /* sound/soc/samsung/i2s.c 2 * 3 * ALSA SoC Audio Layer - Samsung I2S Controller driver 4 * 5 * Copyright (c) 2010 Samsung Electronics Co. Ltd. 6 * Jaswinder Singh <jassisinghbrar@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <dt-bindings/sound/samsung-i2s.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_gpio.h> 22 #include <linux/pm_runtime.h> 23 24 #include <sound/soc.h> 25 #include <sound/pcm_params.h> 26 27 #include <linux/platform_data/asoc-s3c.h> 28 29 #include "dma.h" 30 #include "idma.h" 31 #include "i2s.h" 32 #include "i2s-regs.h" 33 34 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 35 36 enum samsung_dai_type { 37 TYPE_PRI, 38 TYPE_SEC, 39 }; 40 41 struct samsung_i2s_variant_regs { 42 unsigned int bfs_off; 43 unsigned int rfs_off; 44 unsigned int sdf_off; 45 unsigned int txr_off; 46 unsigned int rclksrc_off; 47 unsigned int mss_off; 48 unsigned int cdclkcon_off; 49 unsigned int lrp_off; 50 unsigned int bfs_mask; 51 unsigned int rfs_mask; 52 unsigned int ftx0cnt_off; 53 }; 54 55 struct samsung_i2s_dai_data { 56 int dai_type; 57 u32 quirks; 58 const struct samsung_i2s_variant_regs *i2s_variant_regs; 59 }; 60 61 struct i2s_dai { 62 /* Platform device for this DAI */ 63 struct platform_device *pdev; 64 /* Memory mapped SFR region */ 65 void __iomem *addr; 66 /* Rate of RCLK source clock */ 67 unsigned long rclk_srcrate; 68 /* Frame Clock */ 69 unsigned frmclk; 70 /* 71 * Specifically requested RCLK,BCLK by MACHINE Driver. 72 * 0 indicates CPU driver is free to choose any value. 73 */ 74 unsigned rfs, bfs; 75 /* I2S Controller's core clock */ 76 struct clk *clk; 77 /* Clock for generating I2S signals */ 78 struct clk *op_clk; 79 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */ 80 struct i2s_dai *pri_dai; 81 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */ 82 struct i2s_dai *sec_dai; 83 #define DAI_OPENED (1 << 0) /* Dai is opened */ 84 #define DAI_MANAGER (1 << 1) /* Dai is the manager */ 85 unsigned mode; 86 /* Driver for this DAI */ 87 struct snd_soc_dai_driver i2s_dai_drv; 88 /* DMA parameters */ 89 struct s3c_dma_params dma_playback; 90 struct s3c_dma_params dma_capture; 91 struct s3c_dma_params idma_playback; 92 dma_filter_fn filter; 93 u32 quirks; 94 u32 suspend_i2smod; 95 u32 suspend_i2scon; 96 u32 suspend_i2spsr; 97 const struct samsung_i2s_variant_regs *variant_regs; 98 99 /* Spinlock protecting access to the device's registers */ 100 spinlock_t spinlock; 101 spinlock_t *lock; 102 103 /* Below fields are only valid if this is the primary FIFO */ 104 struct clk *clk_table[3]; 105 struct clk_onecell_data clk_data; 106 }; 107 108 /* Lock for cross i/f checks */ 109 static DEFINE_SPINLOCK(lock); 110 111 /* If this is the 'overlay' stereo DAI */ 112 static inline bool is_secondary(struct i2s_dai *i2s) 113 { 114 return i2s->pri_dai ? true : false; 115 } 116 117 /* If operating in SoC-Slave mode */ 118 static inline bool is_slave(struct i2s_dai *i2s) 119 { 120 u32 mod = readl(i2s->addr + I2SMOD); 121 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false; 122 } 123 124 /* If this interface of the controller is transmitting data */ 125 static inline bool tx_active(struct i2s_dai *i2s) 126 { 127 u32 active; 128 129 if (!i2s) 130 return false; 131 132 active = readl(i2s->addr + I2SCON); 133 134 if (is_secondary(i2s)) 135 active &= CON_TXSDMA_ACTIVE; 136 else 137 active &= CON_TXDMA_ACTIVE; 138 139 return active ? true : false; 140 } 141 142 /* Return pointer to the other DAI */ 143 static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s) 144 { 145 return i2s->pri_dai ? : i2s->sec_dai; 146 } 147 148 /* If the other interface of the controller is transmitting data */ 149 static inline bool other_tx_active(struct i2s_dai *i2s) 150 { 151 struct i2s_dai *other = get_other_dai(i2s); 152 153 return tx_active(other); 154 } 155 156 /* If any interface of the controller is transmitting data */ 157 static inline bool any_tx_active(struct i2s_dai *i2s) 158 { 159 return tx_active(i2s) || other_tx_active(i2s); 160 } 161 162 /* If this interface of the controller is receiving data */ 163 static inline bool rx_active(struct i2s_dai *i2s) 164 { 165 u32 active; 166 167 if (!i2s) 168 return false; 169 170 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE; 171 172 return active ? true : false; 173 } 174 175 /* If the other interface of the controller is receiving data */ 176 static inline bool other_rx_active(struct i2s_dai *i2s) 177 { 178 struct i2s_dai *other = get_other_dai(i2s); 179 180 return rx_active(other); 181 } 182 183 /* If any interface of the controller is receiving data */ 184 static inline bool any_rx_active(struct i2s_dai *i2s) 185 { 186 return rx_active(i2s) || other_rx_active(i2s); 187 } 188 189 /* If the other DAI is transmitting or receiving data */ 190 static inline bool other_active(struct i2s_dai *i2s) 191 { 192 return other_rx_active(i2s) || other_tx_active(i2s); 193 } 194 195 /* If this DAI is transmitting or receiving data */ 196 static inline bool this_active(struct i2s_dai *i2s) 197 { 198 return tx_active(i2s) || rx_active(i2s); 199 } 200 201 /* If the controller is active anyway */ 202 static inline bool any_active(struct i2s_dai *i2s) 203 { 204 return this_active(i2s) || other_active(i2s); 205 } 206 207 static inline struct i2s_dai *to_info(struct snd_soc_dai *dai) 208 { 209 return snd_soc_dai_get_drvdata(dai); 210 } 211 212 static inline bool is_opened(struct i2s_dai *i2s) 213 { 214 if (i2s && (i2s->mode & DAI_OPENED)) 215 return true; 216 else 217 return false; 218 } 219 220 static inline bool is_manager(struct i2s_dai *i2s) 221 { 222 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER)) 223 return true; 224 else 225 return false; 226 } 227 228 /* Read RCLK of I2S (in multiples of LRCLK) */ 229 static inline unsigned get_rfs(struct i2s_dai *i2s) 230 { 231 u32 rfs; 232 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off; 233 rfs &= i2s->variant_regs->rfs_mask; 234 235 switch (rfs) { 236 case 7: return 192; 237 case 6: return 96; 238 case 5: return 128; 239 case 4: return 64; 240 case 3: return 768; 241 case 2: return 384; 242 case 1: return 512; 243 default: return 256; 244 } 245 } 246 247 /* Write RCLK of I2S (in multiples of LRCLK) */ 248 static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs) 249 { 250 u32 mod = readl(i2s->addr + I2SMOD); 251 int rfs_shift = i2s->variant_regs->rfs_off; 252 253 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift); 254 255 switch (rfs) { 256 case 192: 257 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift); 258 break; 259 case 96: 260 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift); 261 break; 262 case 128: 263 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift); 264 break; 265 case 64: 266 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift); 267 break; 268 case 768: 269 mod |= (MOD_RCLK_768FS << rfs_shift); 270 break; 271 case 512: 272 mod |= (MOD_RCLK_512FS << rfs_shift); 273 break; 274 case 384: 275 mod |= (MOD_RCLK_384FS << rfs_shift); 276 break; 277 default: 278 mod |= (MOD_RCLK_256FS << rfs_shift); 279 break; 280 } 281 282 writel(mod, i2s->addr + I2SMOD); 283 } 284 285 /* Read Bit-Clock of I2S (in multiples of LRCLK) */ 286 static inline unsigned get_bfs(struct i2s_dai *i2s) 287 { 288 u32 bfs; 289 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off; 290 bfs &= i2s->variant_regs->bfs_mask; 291 292 switch (bfs) { 293 case 8: return 256; 294 case 7: return 192; 295 case 6: return 128; 296 case 5: return 96; 297 case 4: return 64; 298 case 3: return 24; 299 case 2: return 16; 300 case 1: return 48; 301 default: return 32; 302 } 303 } 304 305 /* Write Bit-Clock of I2S (in multiples of LRCLK) */ 306 static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs) 307 { 308 u32 mod = readl(i2s->addr + I2SMOD); 309 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM; 310 int bfs_shift = i2s->variant_regs->bfs_off; 311 312 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */ 313 if (!tdm && bfs > 48) { 314 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n"); 315 return; 316 } 317 318 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift); 319 320 switch (bfs) { 321 case 48: 322 mod |= (MOD_BCLK_48FS << bfs_shift); 323 break; 324 case 32: 325 mod |= (MOD_BCLK_32FS << bfs_shift); 326 break; 327 case 24: 328 mod |= (MOD_BCLK_24FS << bfs_shift); 329 break; 330 case 16: 331 mod |= (MOD_BCLK_16FS << bfs_shift); 332 break; 333 case 64: 334 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift); 335 break; 336 case 96: 337 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift); 338 break; 339 case 128: 340 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift); 341 break; 342 case 192: 343 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift); 344 break; 345 case 256: 346 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift); 347 break; 348 default: 349 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n"); 350 return; 351 } 352 353 writel(mod, i2s->addr + I2SMOD); 354 } 355 356 /* Sample-Size */ 357 static inline int get_blc(struct i2s_dai *i2s) 358 { 359 int blc = readl(i2s->addr + I2SMOD); 360 361 blc = (blc >> 13) & 0x3; 362 363 switch (blc) { 364 case 2: return 24; 365 case 1: return 8; 366 default: return 16; 367 } 368 } 369 370 /* TX Channel Control */ 371 static void i2s_txctrl(struct i2s_dai *i2s, int on) 372 { 373 void __iomem *addr = i2s->addr; 374 int txr_off = i2s->variant_regs->txr_off; 375 u32 con = readl(addr + I2SCON); 376 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off); 377 378 if (on) { 379 con |= CON_ACTIVE; 380 con &= ~CON_TXCH_PAUSE; 381 382 if (is_secondary(i2s)) { 383 con |= CON_TXSDMA_ACTIVE; 384 con &= ~CON_TXSDMA_PAUSE; 385 } else { 386 con |= CON_TXDMA_ACTIVE; 387 con &= ~CON_TXDMA_PAUSE; 388 } 389 390 if (any_rx_active(i2s)) 391 mod |= 2 << txr_off; 392 else 393 mod |= 0 << txr_off; 394 } else { 395 if (is_secondary(i2s)) { 396 con |= CON_TXSDMA_PAUSE; 397 con &= ~CON_TXSDMA_ACTIVE; 398 } else { 399 con |= CON_TXDMA_PAUSE; 400 con &= ~CON_TXDMA_ACTIVE; 401 } 402 403 if (other_tx_active(i2s)) { 404 writel(con, addr + I2SCON); 405 return; 406 } 407 408 con |= CON_TXCH_PAUSE; 409 410 if (any_rx_active(i2s)) 411 mod |= 1 << txr_off; 412 else 413 con &= ~CON_ACTIVE; 414 } 415 416 writel(mod, addr + I2SMOD); 417 writel(con, addr + I2SCON); 418 } 419 420 /* RX Channel Control */ 421 static void i2s_rxctrl(struct i2s_dai *i2s, int on) 422 { 423 void __iomem *addr = i2s->addr; 424 int txr_off = i2s->variant_regs->txr_off; 425 u32 con = readl(addr + I2SCON); 426 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off); 427 428 if (on) { 429 con |= CON_RXDMA_ACTIVE | CON_ACTIVE; 430 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE); 431 432 if (any_tx_active(i2s)) 433 mod |= 2 << txr_off; 434 else 435 mod |= 1 << txr_off; 436 } else { 437 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE; 438 con &= ~CON_RXDMA_ACTIVE; 439 440 if (any_tx_active(i2s)) 441 mod |= 0 << txr_off; 442 else 443 con &= ~CON_ACTIVE; 444 } 445 446 writel(mod, addr + I2SMOD); 447 writel(con, addr + I2SCON); 448 } 449 450 /* Flush FIFO of an interface */ 451 static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush) 452 { 453 void __iomem *fic; 454 u32 val; 455 456 if (!i2s) 457 return; 458 459 if (is_secondary(i2s)) 460 fic = i2s->addr + I2SFICS; 461 else 462 fic = i2s->addr + I2SFIC; 463 464 /* Flush the FIFO */ 465 writel(readl(fic) | flush, fic); 466 467 /* Be patient */ 468 val = msecs_to_loops(1) / 1000; /* 1 usec */ 469 while (--val) 470 cpu_relax(); 471 472 writel(readl(fic) & ~flush, fic); 473 } 474 475 static int i2s_set_sysclk(struct snd_soc_dai *dai, 476 int clk_id, unsigned int rfs, int dir) 477 { 478 struct i2s_dai *i2s = to_info(dai); 479 struct i2s_dai *other = get_other_dai(i2s); 480 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs; 481 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off; 482 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off; 483 u32 mod, mask, val = 0; 484 485 spin_lock(i2s->lock); 486 mod = readl(i2s->addr + I2SMOD); 487 spin_unlock(i2s->lock); 488 489 switch (clk_id) { 490 case SAMSUNG_I2S_OPCLK: 491 mask = MOD_OPCLK_MASK; 492 val = dir; 493 break; 494 case SAMSUNG_I2S_CDCLK: 495 mask = 1 << i2s_regs->cdclkcon_off; 496 /* Shouldn't matter in GATING(CLOCK_IN) mode */ 497 if (dir == SND_SOC_CLOCK_IN) 498 rfs = 0; 499 500 if ((rfs && other && other->rfs && (other->rfs != rfs)) || 501 (any_active(i2s) && 502 (((dir == SND_SOC_CLOCK_IN) 503 && !(mod & cdcon_mask)) || 504 ((dir == SND_SOC_CLOCK_OUT) 505 && (mod & cdcon_mask))))) { 506 dev_err(&i2s->pdev->dev, 507 "%s:%d Other DAI busy\n", __func__, __LINE__); 508 return -EAGAIN; 509 } 510 511 if (dir == SND_SOC_CLOCK_IN) 512 val = 1 << i2s_regs->cdclkcon_off; 513 514 i2s->rfs = rfs; 515 break; 516 517 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */ 518 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */ 519 mask = 1 << i2s_regs->rclksrc_off; 520 521 if ((i2s->quirks & QUIRK_NO_MUXPSR) 522 || (clk_id == SAMSUNG_I2S_RCLKSRC_0)) 523 clk_id = 0; 524 else 525 clk_id = 1; 526 527 if (!any_active(i2s)) { 528 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) { 529 if ((clk_id && !(mod & rsrc_mask)) || 530 (!clk_id && (mod & rsrc_mask))) { 531 clk_disable_unprepare(i2s->op_clk); 532 clk_put(i2s->op_clk); 533 } else { 534 i2s->rclk_srcrate = 535 clk_get_rate(i2s->op_clk); 536 return 0; 537 } 538 } 539 540 if (clk_id) 541 i2s->op_clk = clk_get(&i2s->pdev->dev, 542 "i2s_opclk1"); 543 else 544 i2s->op_clk = clk_get(&i2s->pdev->dev, 545 "i2s_opclk0"); 546 547 if (WARN_ON(IS_ERR(i2s->op_clk))) 548 return PTR_ERR(i2s->op_clk); 549 550 clk_prepare_enable(i2s->op_clk); 551 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk); 552 553 /* Over-ride the other's */ 554 if (other) { 555 other->op_clk = i2s->op_clk; 556 other->rclk_srcrate = i2s->rclk_srcrate; 557 } 558 } else if ((!clk_id && (mod & rsrc_mask)) 559 || (clk_id && !(mod & rsrc_mask))) { 560 dev_err(&i2s->pdev->dev, 561 "%s:%d Other DAI busy\n", __func__, __LINE__); 562 return -EAGAIN; 563 } else { 564 /* Call can't be on the active DAI */ 565 i2s->op_clk = other->op_clk; 566 i2s->rclk_srcrate = other->rclk_srcrate; 567 return 0; 568 } 569 570 if (clk_id == 1) 571 val = 1 << i2s_regs->rclksrc_off; 572 break; 573 default: 574 dev_err(&i2s->pdev->dev, "We don't serve that!\n"); 575 return -EINVAL; 576 } 577 578 spin_lock(i2s->lock); 579 mod = readl(i2s->addr + I2SMOD); 580 mod = (mod & ~mask) | val; 581 writel(mod, i2s->addr + I2SMOD); 582 spin_unlock(i2s->lock); 583 584 return 0; 585 } 586 587 static int i2s_set_fmt(struct snd_soc_dai *dai, 588 unsigned int fmt) 589 { 590 struct i2s_dai *i2s = to_info(dai); 591 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave; 592 u32 mod, tmp = 0; 593 594 lrp_shift = i2s->variant_regs->lrp_off; 595 sdf_shift = i2s->variant_regs->sdf_off; 596 mod_slave = 1 << i2s->variant_regs->mss_off; 597 598 sdf_mask = MOD_SDF_MASK << sdf_shift; 599 lrp_rlow = MOD_LR_RLOW << lrp_shift; 600 601 /* Format is priority */ 602 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 603 case SND_SOC_DAIFMT_RIGHT_J: 604 tmp |= lrp_rlow; 605 tmp |= (MOD_SDF_MSB << sdf_shift); 606 break; 607 case SND_SOC_DAIFMT_LEFT_J: 608 tmp |= lrp_rlow; 609 tmp |= (MOD_SDF_LSB << sdf_shift); 610 break; 611 case SND_SOC_DAIFMT_I2S: 612 tmp |= (MOD_SDF_IIS << sdf_shift); 613 break; 614 default: 615 dev_err(&i2s->pdev->dev, "Format not supported\n"); 616 return -EINVAL; 617 } 618 619 /* 620 * INV flag is relative to the FORMAT flag - if set it simply 621 * flips the polarity specified by the Standard 622 */ 623 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 624 case SND_SOC_DAIFMT_NB_NF: 625 break; 626 case SND_SOC_DAIFMT_NB_IF: 627 if (tmp & lrp_rlow) 628 tmp &= ~lrp_rlow; 629 else 630 tmp |= lrp_rlow; 631 break; 632 default: 633 dev_err(&i2s->pdev->dev, "Polarity not supported\n"); 634 return -EINVAL; 635 } 636 637 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 638 case SND_SOC_DAIFMT_CBM_CFM: 639 tmp |= mod_slave; 640 break; 641 case SND_SOC_DAIFMT_CBS_CFS: 642 /* Set default source clock in Master mode */ 643 if (i2s->rclk_srcrate == 0) 644 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0, 645 0, SND_SOC_CLOCK_IN); 646 break; 647 default: 648 dev_err(&i2s->pdev->dev, "master/slave format not supported\n"); 649 return -EINVAL; 650 } 651 652 spin_lock(i2s->lock); 653 mod = readl(i2s->addr + I2SMOD); 654 /* 655 * Don't change the I2S mode if any controller is active on this 656 * channel. 657 */ 658 if (any_active(i2s) && 659 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) { 660 spin_unlock(i2s->lock); 661 dev_err(&i2s->pdev->dev, 662 "%s:%d Other DAI busy\n", __func__, __LINE__); 663 return -EAGAIN; 664 } 665 666 mod &= ~(sdf_mask | lrp_rlow | mod_slave); 667 mod |= tmp; 668 writel(mod, i2s->addr + I2SMOD); 669 spin_unlock(i2s->lock); 670 671 return 0; 672 } 673 674 static int i2s_hw_params(struct snd_pcm_substream *substream, 675 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 676 { 677 struct i2s_dai *i2s = to_info(dai); 678 u32 mod, mask = 0, val = 0; 679 680 if (!is_secondary(i2s)) 681 mask |= (MOD_DC2_EN | MOD_DC1_EN); 682 683 switch (params_channels(params)) { 684 case 6: 685 val |= MOD_DC2_EN; 686 case 4: 687 val |= MOD_DC1_EN; 688 break; 689 case 2: 690 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 691 i2s->dma_playback.dma_size = 4; 692 else 693 i2s->dma_capture.dma_size = 4; 694 break; 695 case 1: 696 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 697 i2s->dma_playback.dma_size = 2; 698 else 699 i2s->dma_capture.dma_size = 2; 700 701 break; 702 default: 703 dev_err(&i2s->pdev->dev, "%d channels not supported\n", 704 params_channels(params)); 705 return -EINVAL; 706 } 707 708 if (is_secondary(i2s)) 709 mask |= MOD_BLCS_MASK; 710 else 711 mask |= MOD_BLCP_MASK; 712 713 if (is_manager(i2s)) 714 mask |= MOD_BLC_MASK; 715 716 switch (params_width(params)) { 717 case 8: 718 if (is_secondary(i2s)) 719 val |= MOD_BLCS_8BIT; 720 else 721 val |= MOD_BLCP_8BIT; 722 if (is_manager(i2s)) 723 val |= MOD_BLC_8BIT; 724 break; 725 case 16: 726 if (is_secondary(i2s)) 727 val |= MOD_BLCS_16BIT; 728 else 729 val |= MOD_BLCP_16BIT; 730 if (is_manager(i2s)) 731 val |= MOD_BLC_16BIT; 732 break; 733 case 24: 734 if (is_secondary(i2s)) 735 val |= MOD_BLCS_24BIT; 736 else 737 val |= MOD_BLCP_24BIT; 738 if (is_manager(i2s)) 739 val |= MOD_BLC_24BIT; 740 break; 741 default: 742 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n", 743 params_format(params)); 744 return -EINVAL; 745 } 746 747 spin_lock(i2s->lock); 748 mod = readl(i2s->addr + I2SMOD); 749 mod = (mod & ~mask) | val; 750 writel(mod, i2s->addr + I2SMOD); 751 spin_unlock(i2s->lock); 752 753 samsung_asoc_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture); 754 755 i2s->frmclk = params_rate(params); 756 757 return 0; 758 } 759 760 /* We set constraints on the substream acc to the version of I2S */ 761 static int i2s_startup(struct snd_pcm_substream *substream, 762 struct snd_soc_dai *dai) 763 { 764 struct i2s_dai *i2s = to_info(dai); 765 struct i2s_dai *other = get_other_dai(i2s); 766 unsigned long flags; 767 768 spin_lock_irqsave(&lock, flags); 769 770 i2s->mode |= DAI_OPENED; 771 772 if (is_manager(other)) 773 i2s->mode &= ~DAI_MANAGER; 774 else 775 i2s->mode |= DAI_MANAGER; 776 777 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR)) 778 writel(CON_RSTCLR, i2s->addr + I2SCON); 779 780 spin_unlock_irqrestore(&lock, flags); 781 782 return 0; 783 } 784 785 static void i2s_shutdown(struct snd_pcm_substream *substream, 786 struct snd_soc_dai *dai) 787 { 788 struct i2s_dai *i2s = to_info(dai); 789 struct i2s_dai *other = get_other_dai(i2s); 790 unsigned long flags; 791 792 spin_lock_irqsave(&lock, flags); 793 794 i2s->mode &= ~DAI_OPENED; 795 i2s->mode &= ~DAI_MANAGER; 796 797 if (is_opened(other)) 798 other->mode |= DAI_MANAGER; 799 800 /* Reset any constraint on RFS and BFS */ 801 i2s->rfs = 0; 802 i2s->bfs = 0; 803 804 spin_unlock_irqrestore(&lock, flags); 805 } 806 807 static int config_setup(struct i2s_dai *i2s) 808 { 809 struct i2s_dai *other = get_other_dai(i2s); 810 unsigned rfs, bfs, blc; 811 u32 psr; 812 813 blc = get_blc(i2s); 814 815 bfs = i2s->bfs; 816 817 if (!bfs && other) 818 bfs = other->bfs; 819 820 /* Select least possible multiple(2) if no constraint set */ 821 if (!bfs) 822 bfs = blc * 2; 823 824 rfs = i2s->rfs; 825 826 if (!rfs && other) 827 rfs = other->rfs; 828 829 if ((rfs == 256 || rfs == 512) && (blc == 24)) { 830 dev_err(&i2s->pdev->dev, 831 "%d-RFS not supported for 24-blc\n", rfs); 832 return -EINVAL; 833 } 834 835 if (!rfs) { 836 if (bfs == 16 || bfs == 32) 837 rfs = 256; 838 else 839 rfs = 384; 840 } 841 842 /* If already setup and running */ 843 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) { 844 dev_err(&i2s->pdev->dev, 845 "%s:%d Other DAI busy\n", __func__, __LINE__); 846 return -EAGAIN; 847 } 848 849 set_bfs(i2s, bfs); 850 set_rfs(i2s, rfs); 851 852 /* Don't bother with PSR in Slave mode */ 853 if (is_slave(i2s)) 854 return 0; 855 856 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) { 857 psr = i2s->rclk_srcrate / i2s->frmclk / rfs; 858 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR); 859 dev_dbg(&i2s->pdev->dev, 860 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n", 861 i2s->rclk_srcrate, psr, rfs, bfs); 862 } 863 864 return 0; 865 } 866 867 static int i2s_trigger(struct snd_pcm_substream *substream, 868 int cmd, struct snd_soc_dai *dai) 869 { 870 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); 871 struct snd_soc_pcm_runtime *rtd = substream->private_data; 872 struct i2s_dai *i2s = to_info(rtd->cpu_dai); 873 unsigned long flags; 874 875 switch (cmd) { 876 case SNDRV_PCM_TRIGGER_START: 877 case SNDRV_PCM_TRIGGER_RESUME: 878 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 879 spin_lock_irqsave(i2s->lock, flags); 880 881 if (config_setup(i2s)) { 882 spin_unlock_irqrestore(i2s->lock, flags); 883 return -EINVAL; 884 } 885 886 if (capture) 887 i2s_rxctrl(i2s, 1); 888 else 889 i2s_txctrl(i2s, 1); 890 891 spin_unlock_irqrestore(i2s->lock, flags); 892 break; 893 case SNDRV_PCM_TRIGGER_STOP: 894 case SNDRV_PCM_TRIGGER_SUSPEND: 895 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 896 spin_lock_irqsave(i2s->lock, flags); 897 898 if (capture) { 899 i2s_rxctrl(i2s, 0); 900 i2s_fifo(i2s, FIC_RXFLUSH); 901 } else { 902 i2s_txctrl(i2s, 0); 903 i2s_fifo(i2s, FIC_TXFLUSH); 904 } 905 906 spin_unlock_irqrestore(i2s->lock, flags); 907 break; 908 } 909 910 return 0; 911 } 912 913 static int i2s_set_clkdiv(struct snd_soc_dai *dai, 914 int div_id, int div) 915 { 916 struct i2s_dai *i2s = to_info(dai); 917 struct i2s_dai *other = get_other_dai(i2s); 918 919 switch (div_id) { 920 case SAMSUNG_I2S_DIV_BCLK: 921 if ((any_active(i2s) && div && (get_bfs(i2s) != div)) 922 || (other && other->bfs && (other->bfs != div))) { 923 dev_err(&i2s->pdev->dev, 924 "%s:%d Other DAI busy\n", __func__, __LINE__); 925 return -EAGAIN; 926 } 927 i2s->bfs = div; 928 break; 929 default: 930 dev_err(&i2s->pdev->dev, 931 "Invalid clock divider(%d)\n", div_id); 932 return -EINVAL; 933 } 934 935 return 0; 936 } 937 938 static snd_pcm_sframes_t 939 i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 940 { 941 struct i2s_dai *i2s = to_info(dai); 942 u32 reg = readl(i2s->addr + I2SFIC); 943 snd_pcm_sframes_t delay; 944 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs; 945 946 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 947 delay = FIC_RXCOUNT(reg); 948 else if (is_secondary(i2s)) 949 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS)); 950 else 951 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f; 952 953 return delay; 954 } 955 956 #ifdef CONFIG_PM 957 static int i2s_suspend(struct snd_soc_dai *dai) 958 { 959 struct i2s_dai *i2s = to_info(dai); 960 961 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD); 962 i2s->suspend_i2scon = readl(i2s->addr + I2SCON); 963 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR); 964 965 return 0; 966 } 967 968 static int i2s_resume(struct snd_soc_dai *dai) 969 { 970 struct i2s_dai *i2s = to_info(dai); 971 972 writel(i2s->suspend_i2scon, i2s->addr + I2SCON); 973 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD); 974 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR); 975 976 return 0; 977 } 978 #else 979 #define i2s_suspend NULL 980 #define i2s_resume NULL 981 #endif 982 983 static int samsung_i2s_dai_probe(struct snd_soc_dai *dai) 984 { 985 struct i2s_dai *i2s = to_info(dai); 986 struct i2s_dai *other = get_other_dai(i2s); 987 unsigned long flags; 988 989 if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */ 990 samsung_asoc_init_dma_data(dai, &other->sec_dai->dma_playback, 991 NULL); 992 } else { 993 samsung_asoc_init_dma_data(dai, &i2s->dma_playback, 994 &i2s->dma_capture); 995 996 if (i2s->quirks & QUIRK_NEED_RSTCLR) 997 writel(CON_RSTCLR, i2s->addr + I2SCON); 998 999 if (i2s->quirks & QUIRK_SUPPORTS_IDMA) 1000 idma_reg_addr_init(i2s->addr, 1001 i2s->sec_dai->idma_playback.dma_addr); 1002 } 1003 1004 /* Reset any constraint on RFS and BFS */ 1005 i2s->rfs = 0; 1006 i2s->bfs = 0; 1007 i2s->rclk_srcrate = 0; 1008 1009 spin_lock_irqsave(i2s->lock, flags); 1010 i2s_txctrl(i2s, 0); 1011 i2s_rxctrl(i2s, 0); 1012 i2s_fifo(i2s, FIC_TXFLUSH); 1013 i2s_fifo(other, FIC_TXFLUSH); 1014 i2s_fifo(i2s, FIC_RXFLUSH); 1015 spin_unlock_irqrestore(i2s->lock, flags); 1016 1017 /* Gate CDCLK by default */ 1018 if (!is_opened(other)) 1019 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK, 1020 0, SND_SOC_CLOCK_IN); 1021 1022 return 0; 1023 } 1024 1025 static int samsung_i2s_dai_remove(struct snd_soc_dai *dai) 1026 { 1027 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai); 1028 1029 if (!is_secondary(i2s)) { 1030 if (i2s->quirks & QUIRK_NEED_RSTCLR) { 1031 spin_lock(i2s->lock); 1032 writel(0, i2s->addr + I2SCON); 1033 spin_unlock(i2s->lock); 1034 } 1035 } 1036 1037 return 0; 1038 } 1039 1040 static const struct snd_soc_dai_ops samsung_i2s_dai_ops = { 1041 .trigger = i2s_trigger, 1042 .hw_params = i2s_hw_params, 1043 .set_fmt = i2s_set_fmt, 1044 .set_clkdiv = i2s_set_clkdiv, 1045 .set_sysclk = i2s_set_sysclk, 1046 .startup = i2s_startup, 1047 .shutdown = i2s_shutdown, 1048 .delay = i2s_delay, 1049 }; 1050 1051 static const struct snd_soc_component_driver samsung_i2s_component = { 1052 .name = "samsung-i2s", 1053 }; 1054 1055 #define SAMSUNG_I2S_RATES SNDRV_PCM_RATE_8000_96000 1056 1057 #define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1058 SNDRV_PCM_FMTBIT_S16_LE | \ 1059 SNDRV_PCM_FMTBIT_S24_LE) 1060 1061 static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev, bool sec) 1062 { 1063 struct i2s_dai *i2s; 1064 int ret; 1065 1066 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL); 1067 if (i2s == NULL) 1068 return NULL; 1069 1070 i2s->pdev = pdev; 1071 i2s->pri_dai = NULL; 1072 i2s->sec_dai = NULL; 1073 i2s->i2s_dai_drv.symmetric_rates = 1; 1074 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe; 1075 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove; 1076 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops; 1077 i2s->i2s_dai_drv.suspend = i2s_suspend; 1078 i2s->i2s_dai_drv.resume = i2s_resume; 1079 i2s->i2s_dai_drv.playback.channels_min = 1; 1080 i2s->i2s_dai_drv.playback.channels_max = 2; 1081 i2s->i2s_dai_drv.playback.rates = SAMSUNG_I2S_RATES; 1082 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS; 1083 1084 if (!sec) { 1085 i2s->i2s_dai_drv.capture.channels_min = 1; 1086 i2s->i2s_dai_drv.capture.channels_max = 2; 1087 i2s->i2s_dai_drv.capture.rates = SAMSUNG_I2S_RATES; 1088 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS; 1089 dev_set_drvdata(&i2s->pdev->dev, i2s); 1090 } else { /* Create a new platform_device for Secondary */ 1091 i2s->pdev = platform_device_alloc("samsung-i2s-sec", -1); 1092 if (!i2s->pdev) 1093 return NULL; 1094 1095 i2s->pdev->dev.parent = &pdev->dev; 1096 1097 platform_set_drvdata(i2s->pdev, i2s); 1098 ret = platform_device_add(i2s->pdev); 1099 if (ret < 0) 1100 return NULL; 1101 } 1102 1103 return i2s; 1104 } 1105 1106 static const struct of_device_id exynos_i2s_match[]; 1107 1108 static inline const struct samsung_i2s_dai_data *samsung_i2s_get_driver_data( 1109 struct platform_device *pdev) 1110 { 1111 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { 1112 const struct of_device_id *match; 1113 match = of_match_node(exynos_i2s_match, pdev->dev.of_node); 1114 return match ? match->data : NULL; 1115 } else { 1116 return (struct samsung_i2s_dai_data *) 1117 platform_get_device_id(pdev)->driver_data; 1118 } 1119 } 1120 1121 #ifdef CONFIG_PM 1122 static int i2s_runtime_suspend(struct device *dev) 1123 { 1124 struct i2s_dai *i2s = dev_get_drvdata(dev); 1125 1126 clk_disable_unprepare(i2s->clk); 1127 1128 return 0; 1129 } 1130 1131 static int i2s_runtime_resume(struct device *dev) 1132 { 1133 struct i2s_dai *i2s = dev_get_drvdata(dev); 1134 1135 clk_prepare_enable(i2s->clk); 1136 1137 return 0; 1138 } 1139 #endif /* CONFIG_PM */ 1140 1141 static void i2s_unregister_clocks(struct i2s_dai *i2s) 1142 { 1143 int i; 1144 1145 for (i = 0; i < i2s->clk_data.clk_num; i++) { 1146 if (!IS_ERR(i2s->clk_table[i])) 1147 clk_unregister(i2s->clk_table[i]); 1148 } 1149 } 1150 1151 static void i2s_unregister_clock_provider(struct platform_device *pdev) 1152 { 1153 struct i2s_dai *i2s = dev_get_drvdata(&pdev->dev); 1154 1155 of_clk_del_provider(pdev->dev.of_node); 1156 i2s_unregister_clocks(i2s); 1157 } 1158 1159 static int i2s_register_clock_provider(struct platform_device *pdev) 1160 { 1161 struct device *dev = &pdev->dev; 1162 struct i2s_dai *i2s = dev_get_drvdata(dev); 1163 const char *clk_name[2] = { "i2s_opclk0", "i2s_opclk1" }; 1164 const char *p_names[2] = { NULL }; 1165 const struct samsung_i2s_variant_regs *reg_info = i2s->variant_regs; 1166 struct clk *rclksrc; 1167 int ret, i; 1168 1169 /* Register the clock provider only if it's expected in the DTB */ 1170 if (!of_find_property(dev->of_node, "#clock-cells", NULL)) 1171 return 0; 1172 1173 /* Get the RCLKSRC mux clock parent clock names */ 1174 for (i = 0; i < ARRAY_SIZE(p_names); i++) { 1175 rclksrc = clk_get(dev, clk_name[i]); 1176 if (IS_ERR(rclksrc)) 1177 continue; 1178 p_names[i] = __clk_get_name(rclksrc); 1179 clk_put(rclksrc); 1180 } 1181 1182 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) { 1183 /* Activate the prescaler */ 1184 u32 val = readl(i2s->addr + I2SPSR); 1185 writel(val | PSR_PSREN, i2s->addr + I2SPSR); 1186 1187 i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(NULL, 1188 "i2s_rclksrc", p_names, ARRAY_SIZE(p_names), 1189 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, 1190 i2s->addr + I2SMOD, reg_info->rclksrc_off, 1191 1, 0, i2s->lock); 1192 1193 i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(NULL, 1194 "i2s_presc", "i2s_rclksrc", 1195 CLK_SET_RATE_PARENT, 1196 i2s->addr + I2SPSR, 8, 6, 0, i2s->lock); 1197 1198 p_names[0] = "i2s_presc"; 1199 i2s->clk_data.clk_num = 2; 1200 } 1201 of_property_read_string_index(dev->of_node, 1202 "clock-output-names", 0, &clk_name[0]); 1203 1204 i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(NULL, clk_name[0], 1205 p_names[0], CLK_SET_RATE_PARENT, 1206 i2s->addr + I2SMOD, reg_info->cdclkcon_off, 1207 CLK_GATE_SET_TO_DISABLE, i2s->lock); 1208 1209 i2s->clk_data.clk_num += 1; 1210 i2s->clk_data.clks = i2s->clk_table; 1211 1212 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, 1213 &i2s->clk_data); 1214 if (ret < 0) { 1215 dev_err(dev, "failed to add clock provider: %d\n", ret); 1216 i2s_unregister_clocks(i2s); 1217 } 1218 1219 return ret; 1220 } 1221 1222 static int samsung_i2s_probe(struct platform_device *pdev) 1223 { 1224 struct i2s_dai *pri_dai, *sec_dai = NULL; 1225 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data; 1226 struct samsung_i2s *i2s_cfg = NULL; 1227 struct resource *res; 1228 u32 regs_base, quirks = 0, idma_addr = 0; 1229 struct device_node *np = pdev->dev.of_node; 1230 const struct samsung_i2s_dai_data *i2s_dai_data; 1231 int ret; 1232 1233 /* Call during Seconday interface registration */ 1234 i2s_dai_data = samsung_i2s_get_driver_data(pdev); 1235 1236 if (i2s_dai_data->dai_type == TYPE_SEC) { 1237 sec_dai = dev_get_drvdata(&pdev->dev); 1238 if (!sec_dai) { 1239 dev_err(&pdev->dev, "Unable to get drvdata\n"); 1240 return -EFAULT; 1241 } 1242 ret = devm_snd_soc_register_component(&sec_dai->pdev->dev, 1243 &samsung_i2s_component, 1244 &sec_dai->i2s_dai_drv, 1); 1245 if (ret != 0) 1246 return ret; 1247 1248 return samsung_asoc_dma_platform_register(&pdev->dev, 1249 sec_dai->filter); 1250 } 1251 1252 pri_dai = i2s_alloc_dai(pdev, false); 1253 if (!pri_dai) { 1254 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n"); 1255 return -ENOMEM; 1256 } 1257 1258 spin_lock_init(&pri_dai->spinlock); 1259 pri_dai->lock = &pri_dai->spinlock; 1260 1261 if (!np) { 1262 if (i2s_pdata == NULL) { 1263 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n"); 1264 return -EINVAL; 1265 } 1266 1267 pri_dai->dma_playback.slave = i2s_pdata->dma_playback; 1268 pri_dai->dma_capture.slave = i2s_pdata->dma_capture; 1269 pri_dai->filter = i2s_pdata->dma_filter; 1270 1271 if (&i2s_pdata->type) 1272 i2s_cfg = &i2s_pdata->type.i2s; 1273 1274 if (i2s_cfg) { 1275 quirks = i2s_cfg->quirks; 1276 idma_addr = i2s_cfg->idma_addr; 1277 } 1278 } else { 1279 quirks = i2s_dai_data->quirks; 1280 if (of_property_read_u32(np, "samsung,idma-addr", 1281 &idma_addr)) { 1282 if (quirks & QUIRK_SUPPORTS_IDMA) { 1283 dev_info(&pdev->dev, "idma address is not"\ 1284 "specified"); 1285 } 1286 } 1287 } 1288 1289 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1290 pri_dai->addr = devm_ioremap_resource(&pdev->dev, res); 1291 if (IS_ERR(pri_dai->addr)) 1292 return PTR_ERR(pri_dai->addr); 1293 1294 regs_base = res->start; 1295 1296 pri_dai->clk = devm_clk_get(&pdev->dev, "iis"); 1297 if (IS_ERR(pri_dai->clk)) { 1298 dev_err(&pdev->dev, "Failed to get iis clock\n"); 1299 return PTR_ERR(pri_dai->clk); 1300 } 1301 1302 ret = clk_prepare_enable(pri_dai->clk); 1303 if (ret != 0) { 1304 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret); 1305 return ret; 1306 } 1307 pri_dai->dma_playback.dma_addr = regs_base + I2STXD; 1308 pri_dai->dma_capture.dma_addr = regs_base + I2SRXD; 1309 pri_dai->dma_playback.ch_name = "tx"; 1310 pri_dai->dma_capture.ch_name = "rx"; 1311 pri_dai->dma_playback.dma_size = 4; 1312 pri_dai->dma_capture.dma_size = 4; 1313 pri_dai->quirks = quirks; 1314 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs; 1315 1316 if (quirks & QUIRK_PRI_6CHAN) 1317 pri_dai->i2s_dai_drv.playback.channels_max = 6; 1318 1319 if (quirks & QUIRK_SEC_DAI) { 1320 sec_dai = i2s_alloc_dai(pdev, true); 1321 if (!sec_dai) { 1322 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n"); 1323 return -ENOMEM; 1324 } 1325 1326 sec_dai->lock = &pri_dai->spinlock; 1327 sec_dai->variant_regs = pri_dai->variant_regs; 1328 sec_dai->dma_playback.dma_addr = regs_base + I2STXDS; 1329 sec_dai->dma_playback.ch_name = "tx-sec"; 1330 1331 if (!np) { 1332 sec_dai->dma_playback.slave = i2s_pdata->dma_play_sec; 1333 sec_dai->filter = i2s_pdata->dma_filter; 1334 } 1335 1336 sec_dai->dma_playback.dma_size = 4; 1337 sec_dai->addr = pri_dai->addr; 1338 sec_dai->clk = pri_dai->clk; 1339 sec_dai->quirks = quirks; 1340 sec_dai->idma_playback.dma_addr = idma_addr; 1341 sec_dai->pri_dai = pri_dai; 1342 pri_dai->sec_dai = sec_dai; 1343 } 1344 1345 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) { 1346 dev_err(&pdev->dev, "Unable to configure gpio\n"); 1347 return -EINVAL; 1348 } 1349 1350 devm_snd_soc_register_component(&pri_dai->pdev->dev, 1351 &samsung_i2s_component, 1352 &pri_dai->i2s_dai_drv, 1); 1353 1354 pm_runtime_enable(&pdev->dev); 1355 1356 ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter); 1357 if (ret != 0) 1358 return ret; 1359 1360 return i2s_register_clock_provider(pdev); 1361 } 1362 1363 static int samsung_i2s_remove(struct platform_device *pdev) 1364 { 1365 struct i2s_dai *i2s, *other; 1366 1367 i2s = dev_get_drvdata(&pdev->dev); 1368 other = get_other_dai(i2s); 1369 1370 if (other) { 1371 other->pri_dai = NULL; 1372 other->sec_dai = NULL; 1373 } else { 1374 pm_runtime_disable(&pdev->dev); 1375 } 1376 1377 if (!is_secondary(i2s)) { 1378 i2s_unregister_clock_provider(pdev); 1379 clk_disable_unprepare(i2s->clk); 1380 } 1381 1382 i2s->pri_dai = NULL; 1383 i2s->sec_dai = NULL; 1384 1385 return 0; 1386 } 1387 1388 static const struct samsung_i2s_variant_regs i2sv3_regs = { 1389 .bfs_off = 1, 1390 .rfs_off = 3, 1391 .sdf_off = 5, 1392 .txr_off = 8, 1393 .rclksrc_off = 10, 1394 .mss_off = 11, 1395 .cdclkcon_off = 12, 1396 .lrp_off = 7, 1397 .bfs_mask = 0x3, 1398 .rfs_mask = 0x3, 1399 .ftx0cnt_off = 8, 1400 }; 1401 1402 static const struct samsung_i2s_variant_regs i2sv6_regs = { 1403 .bfs_off = 0, 1404 .rfs_off = 4, 1405 .sdf_off = 6, 1406 .txr_off = 8, 1407 .rclksrc_off = 10, 1408 .mss_off = 11, 1409 .cdclkcon_off = 12, 1410 .lrp_off = 15, 1411 .bfs_mask = 0xf, 1412 .rfs_mask = 0x3, 1413 .ftx0cnt_off = 8, 1414 }; 1415 1416 static const struct samsung_i2s_variant_regs i2sv7_regs = { 1417 .bfs_off = 0, 1418 .rfs_off = 4, 1419 .sdf_off = 7, 1420 .txr_off = 9, 1421 .rclksrc_off = 11, 1422 .mss_off = 12, 1423 .cdclkcon_off = 22, 1424 .lrp_off = 15, 1425 .bfs_mask = 0xf, 1426 .rfs_mask = 0x7, 1427 .ftx0cnt_off = 0, 1428 }; 1429 1430 static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = { 1431 .bfs_off = 0, 1432 .rfs_off = 3, 1433 .sdf_off = 6, 1434 .txr_off = 8, 1435 .rclksrc_off = 10, 1436 .mss_off = 11, 1437 .cdclkcon_off = 12, 1438 .lrp_off = 15, 1439 .bfs_mask = 0x7, 1440 .rfs_mask = 0x7, 1441 .ftx0cnt_off = 8, 1442 }; 1443 1444 static const struct samsung_i2s_dai_data i2sv3_dai_type = { 1445 .dai_type = TYPE_PRI, 1446 .quirks = QUIRK_NO_MUXPSR, 1447 .i2s_variant_regs = &i2sv3_regs, 1448 }; 1449 1450 static const struct samsung_i2s_dai_data i2sv5_dai_type = { 1451 .dai_type = TYPE_PRI, 1452 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR | 1453 QUIRK_SUPPORTS_IDMA, 1454 .i2s_variant_regs = &i2sv3_regs, 1455 }; 1456 1457 static const struct samsung_i2s_dai_data i2sv6_dai_type = { 1458 .dai_type = TYPE_PRI, 1459 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR | 1460 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA, 1461 .i2s_variant_regs = &i2sv6_regs, 1462 }; 1463 1464 static const struct samsung_i2s_dai_data i2sv7_dai_type = { 1465 .dai_type = TYPE_PRI, 1466 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR | 1467 QUIRK_SUPPORTS_TDM, 1468 .i2s_variant_regs = &i2sv7_regs, 1469 }; 1470 1471 static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = { 1472 .dai_type = TYPE_PRI, 1473 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR, 1474 .i2s_variant_regs = &i2sv5_i2s1_regs, 1475 }; 1476 1477 static const struct samsung_i2s_dai_data samsung_dai_type_pri = { 1478 .dai_type = TYPE_PRI, 1479 }; 1480 1481 static const struct samsung_i2s_dai_data samsung_dai_type_sec = { 1482 .dai_type = TYPE_SEC, 1483 }; 1484 1485 static const struct platform_device_id samsung_i2s_driver_ids[] = { 1486 { 1487 .name = "samsung-i2s", 1488 .driver_data = (kernel_ulong_t)&i2sv3_dai_type, 1489 }, { 1490 .name = "samsung-i2s-sec", 1491 .driver_data = (kernel_ulong_t)&samsung_dai_type_sec, 1492 }, { 1493 .name = "samsung-i2sv4", 1494 .driver_data = (kernel_ulong_t)&i2sv5_dai_type, 1495 }, 1496 {}, 1497 }; 1498 MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids); 1499 1500 #ifdef CONFIG_OF 1501 static const struct of_device_id exynos_i2s_match[] = { 1502 { 1503 .compatible = "samsung,s3c6410-i2s", 1504 .data = &i2sv3_dai_type, 1505 }, { 1506 .compatible = "samsung,s5pv210-i2s", 1507 .data = &i2sv5_dai_type, 1508 }, { 1509 .compatible = "samsung,exynos5420-i2s", 1510 .data = &i2sv6_dai_type, 1511 }, { 1512 .compatible = "samsung,exynos7-i2s", 1513 .data = &i2sv7_dai_type, 1514 }, { 1515 .compatible = "samsung,exynos7-i2s1", 1516 .data = &i2sv5_dai_type_i2s1, 1517 }, 1518 {}, 1519 }; 1520 MODULE_DEVICE_TABLE(of, exynos_i2s_match); 1521 #endif 1522 1523 static const struct dev_pm_ops samsung_i2s_pm = { 1524 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, 1525 i2s_runtime_resume, NULL) 1526 }; 1527 1528 static struct platform_driver samsung_i2s_driver = { 1529 .probe = samsung_i2s_probe, 1530 .remove = samsung_i2s_remove, 1531 .id_table = samsung_i2s_driver_ids, 1532 .driver = { 1533 .name = "samsung-i2s", 1534 .of_match_table = of_match_ptr(exynos_i2s_match), 1535 .pm = &samsung_i2s_pm, 1536 }, 1537 }; 1538 1539 module_platform_driver(samsung_i2s_driver); 1540 1541 /* Module information */ 1542 MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>"); 1543 MODULE_DESCRIPTION("Samsung I2S Interface"); 1544 MODULE_ALIAS("platform:samsung-i2s"); 1545 MODULE_LICENSE("GPL"); 1546