1 // SPDX-License-Identifier: GPL-2.0-only
2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
3 
4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd.
5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com>
6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
7 
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/of_gpio.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/spinlock.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm_params.h>
22 
23 #include "rockchip_i2s_tdm.h"
24 
25 #define DRV_NAME "rockchip-i2s-tdm"
26 
27 #define DEFAULT_MCLK_FS				256
28 #define CH_GRP_MAX				4  /* The max channel 8 / 2 */
29 #define MULTIPLEX_CH_MAX			10
30 #define CLK_PPM_MIN				-1000
31 #define CLK_PPM_MAX				1000
32 
33 #define TRCM_TXRX 0
34 #define TRCM_TX 1
35 #define TRCM_RX 2
36 
37 struct txrx_config {
38 	u32 addr;
39 	u32 reg;
40 	u32 txonly;
41 	u32 rxonly;
42 };
43 
44 struct rk_i2s_soc_data {
45 	u32 softrst_offset;
46 	u32 grf_reg_offset;
47 	u32 grf_shift;
48 	int config_count;
49 	const struct txrx_config *configs;
50 	int (*init)(struct device *dev, u32 addr);
51 };
52 
53 struct rk_i2s_tdm_dev {
54 	struct device *dev;
55 	struct clk *hclk;
56 	struct clk *mclk_tx;
57 	struct clk *mclk_rx;
58 	/* The mclk_tx_src is parent of mclk_tx */
59 	struct clk *mclk_tx_src;
60 	/* The mclk_rx_src is parent of mclk_rx */
61 	struct clk *mclk_rx_src;
62 	/*
63 	 * The mclk_root0 and mclk_root1 are root parent and supplies for
64 	 * the different FS.
65 	 *
66 	 * e.g:
67 	 * mclk_root0 is VPLL0, used for FS=48000Hz
68 	 * mclk_root1 is VPLL1, used for FS=44100Hz
69 	 */
70 	struct clk *mclk_root0;
71 	struct clk *mclk_root1;
72 	struct regmap *regmap;
73 	struct regmap *grf;
74 	struct snd_dmaengine_dai_dma_data capture_dma_data;
75 	struct snd_dmaengine_dai_dma_data playback_dma_data;
76 	struct reset_control *tx_reset;
77 	struct reset_control *rx_reset;
78 	struct rk_i2s_soc_data *soc_data;
79 	bool is_master_mode;
80 	bool io_multiplex;
81 	bool mclk_calibrate;
82 	bool tdm_mode;
83 	unsigned int mclk_rx_freq;
84 	unsigned int mclk_tx_freq;
85 	unsigned int mclk_root0_freq;
86 	unsigned int mclk_root1_freq;
87 	unsigned int mclk_root0_initial_freq;
88 	unsigned int mclk_root1_initial_freq;
89 	unsigned int frame_width;
90 	unsigned int clk_trcm;
91 	unsigned int i2s_sdis[CH_GRP_MAX];
92 	unsigned int i2s_sdos[CH_GRP_MAX];
93 	int clk_ppm;
94 	int refcount;
95 	spinlock_t lock; /* xfer lock */
96 	bool has_playback;
97 	bool has_capture;
98 	struct snd_soc_dai_driver *dai;
99 };
100 
101 static int to_ch_num(unsigned int val)
102 {
103 	switch (val) {
104 	case I2S_CHN_4:
105 		return 4;
106 	case I2S_CHN_6:
107 		return 6;
108 	case I2S_CHN_8:
109 		return 8;
110 	default:
111 		return 2;
112 	}
113 }
114 
115 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
116 {
117 	clk_disable_unprepare(i2s_tdm->mclk_tx);
118 	clk_disable_unprepare(i2s_tdm->mclk_rx);
119 	if (i2s_tdm->mclk_calibrate) {
120 		clk_disable_unprepare(i2s_tdm->mclk_tx_src);
121 		clk_disable_unprepare(i2s_tdm->mclk_rx_src);
122 		clk_disable_unprepare(i2s_tdm->mclk_root0);
123 		clk_disable_unprepare(i2s_tdm->mclk_root1);
124 	}
125 }
126 
127 /**
128  * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
129  *				 failure.
130  * @i2s_tdm: rk_i2s_tdm_dev struct
131  *
132  * This function attempts to enable all mclk clocks, but cleans up after
133  * itself on failure. Guarantees to balance its calls.
134  *
135  * Returns success (0) or negative errno.
136  */
137 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
138 {
139 	int ret = 0;
140 
141 	ret = clk_prepare_enable(i2s_tdm->mclk_tx);
142 	if (ret)
143 		goto err_mclk_tx;
144 	ret = clk_prepare_enable(i2s_tdm->mclk_rx);
145 	if (ret)
146 		goto err_mclk_rx;
147 	if (i2s_tdm->mclk_calibrate) {
148 		ret = clk_prepare_enable(i2s_tdm->mclk_tx_src);
149 		if (ret)
150 			goto err_mclk_rx;
151 		ret = clk_prepare_enable(i2s_tdm->mclk_rx_src);
152 		if (ret)
153 			goto err_mclk_rx_src;
154 		ret = clk_prepare_enable(i2s_tdm->mclk_root0);
155 		if (ret)
156 			goto err_mclk_root0;
157 		ret = clk_prepare_enable(i2s_tdm->mclk_root1);
158 		if (ret)
159 			goto err_mclk_root1;
160 	}
161 
162 	return 0;
163 
164 err_mclk_root1:
165 	clk_disable_unprepare(i2s_tdm->mclk_root0);
166 err_mclk_root0:
167 	clk_disable_unprepare(i2s_tdm->mclk_rx_src);
168 err_mclk_rx_src:
169 	clk_disable_unprepare(i2s_tdm->mclk_tx_src);
170 err_mclk_rx:
171 	clk_disable_unprepare(i2s_tdm->mclk_tx);
172 err_mclk_tx:
173 	return ret;
174 }
175 
176 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev)
177 {
178 	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
179 
180 	regcache_cache_only(i2s_tdm->regmap, true);
181 	i2s_tdm_disable_unprepare_mclk(i2s_tdm);
182 
183 	clk_disable_unprepare(i2s_tdm->hclk);
184 
185 	return 0;
186 }
187 
188 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev)
189 {
190 	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
191 	int ret;
192 
193 	ret = clk_prepare_enable(i2s_tdm->hclk);
194 	if (ret)
195 		goto err_hclk;
196 
197 	ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
198 	if (ret)
199 		goto err_mclk;
200 
201 	regcache_cache_only(i2s_tdm->regmap, false);
202 	regcache_mark_dirty(i2s_tdm->regmap);
203 
204 	ret = regcache_sync(i2s_tdm->regmap);
205 	if (ret)
206 		goto err_regcache;
207 
208 	return 0;
209 
210 err_regcache:
211 	i2s_tdm_disable_unprepare_mclk(i2s_tdm);
212 err_mclk:
213 	clk_disable_unprepare(i2s_tdm->hclk);
214 err_hclk:
215 	return ret;
216 }
217 
218 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
219 {
220 	return snd_soc_dai_get_drvdata(dai);
221 }
222 
223 /*
224  * Makes sure that both tx and rx are reset at the same time to sync lrck
225  * when clk_trcm > 0.
226  */
227 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
228 {
229 	/* This is technically race-y.
230 	 *
231 	 * In an ideal world, we could atomically assert both resets at the
232 	 * same time, through an atomic bulk reset API. This API however does
233 	 * not exist, so what the downstream vendor code used to do was
234 	 * implement half a reset controller here and require the CRU to be
235 	 * passed to the driver as a device tree node. Violating abstractions
236 	 * like that is bad, especially when it influences something like the
237 	 * bindings which are supposed to describe the hardware, not whatever
238 	 * workarounds the driver needs, so it was dropped.
239 	 *
240 	 * In practice, asserting the resets one by one appears to work just
241 	 * fine for playback. During duplex (playback + capture) operation,
242 	 * this might become an issue, but that should be solved by the
243 	 * implementation of the aforementioned API, not by shoving a reset
244 	 * controller into an audio driver.
245 	 */
246 
247 	reset_control_assert(i2s_tdm->tx_reset);
248 	reset_control_assert(i2s_tdm->rx_reset);
249 	udelay(10);
250 	reset_control_deassert(i2s_tdm->tx_reset);
251 	reset_control_deassert(i2s_tdm->rx_reset);
252 	udelay(10);
253 }
254 
255 static void rockchip_snd_reset(struct reset_control *rc)
256 {
257 	reset_control_assert(rc);
258 	udelay(10);
259 	reset_control_deassert(rc);
260 	udelay(10);
261 }
262 
263 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
264 				    unsigned int clr)
265 {
266 	unsigned int xfer_mask = 0;
267 	unsigned int xfer_val = 0;
268 	unsigned int val;
269 	int retry = 10;
270 	bool tx = clr & I2S_CLR_TXC;
271 	bool rx = clr & I2S_CLR_RXC;
272 
273 	if (!(rx || tx))
274 		return;
275 
276 	if (tx) {
277 		xfer_mask = I2S_XFER_TXS_START;
278 		xfer_val = I2S_XFER_TXS_STOP;
279 	}
280 	if (rx) {
281 		xfer_mask |= I2S_XFER_RXS_START;
282 		xfer_val |= I2S_XFER_RXS_STOP;
283 	}
284 
285 	regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
286 	udelay(150);
287 	regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
288 
289 	regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
290 	/* Wait on the clear operation to finish */
291 	while (val) {
292 		udelay(15);
293 		regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
294 		retry--;
295 		if (!retry) {
296 			dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
297 				 tx ? "tx" : "", rx ? "rx" : "");
298 			if (rx && tx)
299 				rockchip_snd_xfer_sync_reset(i2s_tdm);
300 			else if (tx)
301 				rockchip_snd_reset(i2s_tdm->tx_reset);
302 			else if (rx)
303 				rockchip_snd_reset(i2s_tdm->rx_reset);
304 			break;
305 		}
306 	}
307 }
308 
309 static inline void rockchip_enable_tde(struct regmap *regmap)
310 {
311 	regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
312 			   I2S_DMACR_TDE_ENABLE);
313 }
314 
315 static inline void rockchip_disable_tde(struct regmap *regmap)
316 {
317 	regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
318 			   I2S_DMACR_TDE_DISABLE);
319 }
320 
321 static inline void rockchip_enable_rde(struct regmap *regmap)
322 {
323 	regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
324 			   I2S_DMACR_RDE_ENABLE);
325 }
326 
327 static inline void rockchip_disable_rde(struct regmap *regmap)
328 {
329 	regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
330 			   I2S_DMACR_RDE_DISABLE);
331 }
332 
333 /* only used when clk_trcm > 0 */
334 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
335 				  struct snd_soc_dai *dai, int on)
336 {
337 	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
338 	unsigned long flags;
339 
340 	spin_lock_irqsave(&i2s_tdm->lock, flags);
341 	if (on) {
342 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
343 			rockchip_enable_tde(i2s_tdm->regmap);
344 		else
345 			rockchip_enable_rde(i2s_tdm->regmap);
346 
347 		if (++i2s_tdm->refcount == 1) {
348 			rockchip_snd_xfer_sync_reset(i2s_tdm);
349 			regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
350 					   I2S_XFER_TXS_START |
351 					   I2S_XFER_RXS_START,
352 					   I2S_XFER_TXS_START |
353 					   I2S_XFER_RXS_START);
354 		}
355 	} else {
356 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
357 			rockchip_disable_tde(i2s_tdm->regmap);
358 		else
359 			rockchip_disable_rde(i2s_tdm->regmap);
360 
361 		if (--i2s_tdm->refcount == 0) {
362 			rockchip_snd_xfer_clear(i2s_tdm,
363 						I2S_CLR_TXC | I2S_CLR_RXC);
364 		}
365 	}
366 	spin_unlock_irqrestore(&i2s_tdm->lock, flags);
367 }
368 
369 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
370 {
371 	if (on) {
372 		rockchip_enable_tde(i2s_tdm->regmap);
373 
374 		regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
375 				   I2S_XFER_TXS_START,
376 				   I2S_XFER_TXS_START);
377 	} else {
378 		rockchip_disable_tde(i2s_tdm->regmap);
379 
380 		rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
381 	}
382 }
383 
384 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
385 {
386 	if (on) {
387 		rockchip_enable_rde(i2s_tdm->regmap);
388 
389 		regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
390 				   I2S_XFER_RXS_START,
391 				   I2S_XFER_RXS_START);
392 	} else {
393 		rockchip_disable_rde(i2s_tdm->regmap);
394 
395 		rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
396 	}
397 }
398 
399 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
400 				    unsigned int fmt)
401 {
402 	struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
403 	unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
404 	int ret;
405 	bool is_tdm = i2s_tdm->tdm_mode;
406 
407 	ret = pm_runtime_get_sync(cpu_dai->dev);
408 	if (ret < 0 && ret != -EACCES) {
409 		pm_runtime_put_noidle(cpu_dai->dev);
410 		return ret;
411 	}
412 
413 	mask = I2S_CKR_MSS_MASK;
414 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
415 	case SND_SOC_DAIFMT_CBC_CFC:
416 		val = I2S_CKR_MSS_MASTER;
417 		i2s_tdm->is_master_mode = true;
418 		break;
419 	case SND_SOC_DAIFMT_CBP_CFP:
420 		val = I2S_CKR_MSS_SLAVE;
421 		i2s_tdm->is_master_mode = false;
422 		break;
423 	default:
424 		ret = -EINVAL;
425 		goto err_pm_put;
426 	}
427 
428 	regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
429 
430 	mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
431 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
432 	case SND_SOC_DAIFMT_NB_NF:
433 		val = I2S_CKR_CKP_NORMAL |
434 		      I2S_CKR_TLP_NORMAL |
435 		      I2S_CKR_RLP_NORMAL;
436 		break;
437 	case SND_SOC_DAIFMT_NB_IF:
438 		val = I2S_CKR_CKP_NORMAL |
439 		      I2S_CKR_TLP_INVERTED |
440 		      I2S_CKR_RLP_INVERTED;
441 		break;
442 	case SND_SOC_DAIFMT_IB_NF:
443 		val = I2S_CKR_CKP_INVERTED |
444 		      I2S_CKR_TLP_NORMAL |
445 		      I2S_CKR_RLP_NORMAL;
446 		break;
447 	case SND_SOC_DAIFMT_IB_IF:
448 		val = I2S_CKR_CKP_INVERTED |
449 		      I2S_CKR_TLP_INVERTED |
450 		      I2S_CKR_RLP_INVERTED;
451 		break;
452 	default:
453 		ret = -EINVAL;
454 		goto err_pm_put;
455 	}
456 
457 	regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
458 
459 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
460 	case SND_SOC_DAIFMT_RIGHT_J:
461 		txcr_val = I2S_TXCR_IBM_RSJM;
462 		rxcr_val = I2S_RXCR_IBM_RSJM;
463 		break;
464 	case SND_SOC_DAIFMT_LEFT_J:
465 		txcr_val = I2S_TXCR_IBM_LSJM;
466 		rxcr_val = I2S_RXCR_IBM_LSJM;
467 		break;
468 	case SND_SOC_DAIFMT_I2S:
469 		txcr_val = I2S_TXCR_IBM_NORMAL;
470 		rxcr_val = I2S_RXCR_IBM_NORMAL;
471 		break;
472 	case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
473 		txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
474 		rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
475 		break;
476 	case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
477 		txcr_val = I2S_TXCR_TFS_PCM;
478 		rxcr_val = I2S_RXCR_TFS_PCM;
479 		break;
480 	default:
481 		ret = -EINVAL;
482 		goto err_pm_put;
483 	}
484 
485 	mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
486 	regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
487 
488 	mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
489 	regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
490 
491 	if (is_tdm) {
492 		switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
493 		case SND_SOC_DAIFMT_RIGHT_J:
494 			val = I2S_TXCR_TFS_TDM_I2S;
495 			tdm_val = TDM_SHIFT_CTRL(2);
496 			break;
497 		case SND_SOC_DAIFMT_LEFT_J:
498 			val = I2S_TXCR_TFS_TDM_I2S;
499 			tdm_val = TDM_SHIFT_CTRL(1);
500 			break;
501 		case SND_SOC_DAIFMT_I2S:
502 			val = I2S_TXCR_TFS_TDM_I2S;
503 			tdm_val = TDM_SHIFT_CTRL(0);
504 			break;
505 		case SND_SOC_DAIFMT_DSP_A:
506 			val = I2S_TXCR_TFS_TDM_PCM;
507 			tdm_val = TDM_SHIFT_CTRL(0);
508 			break;
509 		case SND_SOC_DAIFMT_DSP_B:
510 			val = I2S_TXCR_TFS_TDM_PCM;
511 			tdm_val = TDM_SHIFT_CTRL(2);
512 			break;
513 		default:
514 			ret = -EINVAL;
515 			goto err_pm_put;
516 		}
517 
518 		tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
519 		tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
520 
521 		mask = I2S_TXCR_TFS_MASK;
522 		regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
523 		regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
524 
525 		mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
526 		       TDM_SHIFT_CTRL_MSK;
527 		regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
528 				   mask, tdm_val);
529 		regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
530 				   mask, tdm_val);
531 	}
532 
533 err_pm_put:
534 	pm_runtime_put(cpu_dai->dev);
535 
536 	return ret;
537 }
538 
539 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
540 					struct rk_i2s_tdm_dev *i2s_tdm)
541 {
542 	int stream;
543 
544 	stream = SNDRV_PCM_STREAM_LAST - substream->stream;
545 	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
546 		rockchip_disable_tde(i2s_tdm->regmap);
547 	else
548 		rockchip_disable_rde(i2s_tdm->regmap);
549 
550 	rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
551 }
552 
553 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
554 					 struct rk_i2s_tdm_dev *i2s_tdm)
555 {
556 	int stream;
557 
558 	stream = SNDRV_PCM_STREAM_LAST - substream->stream;
559 	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
560 		rockchip_enable_tde(i2s_tdm->regmap);
561 	else
562 		rockchip_enable_rde(i2s_tdm->regmap);
563 
564 	regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
565 			   I2S_XFER_TXS_START |
566 			   I2S_XFER_RXS_START,
567 			   I2S_XFER_TXS_START |
568 			   I2S_XFER_RXS_START);
569 }
570 
571 static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
572 					 struct clk *clk, unsigned long rate,
573 					 int ppm)
574 {
575 	unsigned long rate_target;
576 	int delta, ret;
577 
578 	if (ppm == i2s_tdm->clk_ppm)
579 		return 0;
580 
581 	if (ppm < 0)
582 		delta = -1;
583 	else
584 		delta = 1;
585 
586 	delta *= (int)div64_u64((u64)rate * (u64)abs(ppm) + 500000,
587 				1000000);
588 
589 	rate_target = rate + delta;
590 
591 	if (!rate_target)
592 		return -EINVAL;
593 
594 	ret = clk_set_rate(clk, rate_target);
595 	if (ret)
596 		return ret;
597 
598 	i2s_tdm->clk_ppm = ppm;
599 
600 	return 0;
601 }
602 
603 static int rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
604 					   struct snd_pcm_substream *substream,
605 					   unsigned int lrck_freq)
606 {
607 	struct clk *mclk_root;
608 	struct clk *mclk_parent;
609 	unsigned int mclk_root_freq;
610 	unsigned int mclk_root_initial_freq;
611 	unsigned int mclk_parent_freq;
612 	unsigned int div, delta;
613 	u64 ppm;
614 	int ret;
615 
616 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
617 		mclk_parent = i2s_tdm->mclk_tx_src;
618 	else
619 		mclk_parent = i2s_tdm->mclk_rx_src;
620 
621 	switch (lrck_freq) {
622 	case 8000:
623 	case 16000:
624 	case 24000:
625 	case 32000:
626 	case 48000:
627 	case 64000:
628 	case 96000:
629 	case 192000:
630 		mclk_root = i2s_tdm->mclk_root0;
631 		mclk_root_freq = i2s_tdm->mclk_root0_freq;
632 		mclk_root_initial_freq = i2s_tdm->mclk_root0_initial_freq;
633 		mclk_parent_freq = DEFAULT_MCLK_FS * 192000;
634 		break;
635 	case 11025:
636 	case 22050:
637 	case 44100:
638 	case 88200:
639 	case 176400:
640 		mclk_root = i2s_tdm->mclk_root1;
641 		mclk_root_freq = i2s_tdm->mclk_root1_freq;
642 		mclk_root_initial_freq = i2s_tdm->mclk_root1_initial_freq;
643 		mclk_parent_freq = DEFAULT_MCLK_FS * 176400;
644 		break;
645 	default:
646 		dev_err(i2s_tdm->dev, "Invalid LRCK frequency: %u Hz\n",
647 			lrck_freq);
648 		return -EINVAL;
649 	}
650 
651 	ret = clk_set_parent(mclk_parent, mclk_root);
652 	if (ret)
653 		return ret;
654 
655 	ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, mclk_root,
656 					    mclk_root_freq, 0);
657 	if (ret)
658 		return ret;
659 
660 	delta = abs(mclk_root_freq % mclk_parent_freq - mclk_parent_freq);
661 	ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)mclk_root_freq);
662 
663 	if (ppm) {
664 		div = DIV_ROUND_CLOSEST(mclk_root_initial_freq, mclk_parent_freq);
665 		if (!div)
666 			return -EINVAL;
667 
668 		mclk_root_freq = mclk_parent_freq * round_up(div, 2);
669 
670 		ret = clk_set_rate(mclk_root, mclk_root_freq);
671 		if (ret)
672 			return ret;
673 
674 		i2s_tdm->mclk_root0_freq = clk_get_rate(i2s_tdm->mclk_root0);
675 		i2s_tdm->mclk_root1_freq = clk_get_rate(i2s_tdm->mclk_root1);
676 	}
677 
678 	return clk_set_rate(mclk_parent, mclk_parent_freq);
679 }
680 
681 static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
682 				     struct snd_pcm_substream *substream,
683 				     struct clk **mclk)
684 {
685 	unsigned int mclk_freq;
686 	int ret;
687 
688 	if (i2s_tdm->clk_trcm) {
689 		if (i2s_tdm->mclk_tx_freq != i2s_tdm->mclk_rx_freq) {
690 			dev_err(i2s_tdm->dev,
691 				"clk_trcm, tx: %d and rx: %d should be the same\n",
692 				i2s_tdm->mclk_tx_freq,
693 				i2s_tdm->mclk_rx_freq);
694 			return -EINVAL;
695 		}
696 
697 		ret = clk_set_rate(i2s_tdm->mclk_tx, i2s_tdm->mclk_tx_freq);
698 		if (ret)
699 			return ret;
700 
701 		ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
702 		if (ret)
703 			return ret;
704 
705 		/* mclk_rx is also ok. */
706 		*mclk = i2s_tdm->mclk_tx;
707 	} else {
708 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
709 			*mclk = i2s_tdm->mclk_tx;
710 			mclk_freq = i2s_tdm->mclk_tx_freq;
711 		} else {
712 			*mclk = i2s_tdm->mclk_rx;
713 			mclk_freq = i2s_tdm->mclk_rx_freq;
714 		}
715 
716 		ret = clk_set_rate(*mclk, mclk_freq);
717 		if (ret)
718 			return ret;
719 	}
720 
721 	return 0;
722 }
723 
724 static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture)
725 {
726 	if (substream_capture) {
727 		switch (ch) {
728 		case I2S_CHN_4:
729 			return I2S_IO_6CH_OUT_4CH_IN;
730 		case I2S_CHN_6:
731 			return I2S_IO_4CH_OUT_6CH_IN;
732 		case I2S_CHN_8:
733 			return I2S_IO_2CH_OUT_8CH_IN;
734 		default:
735 			return I2S_IO_8CH_OUT_2CH_IN;
736 		}
737 	} else {
738 		switch (ch) {
739 		case I2S_CHN_4:
740 			return I2S_IO_4CH_OUT_6CH_IN;
741 		case I2S_CHN_6:
742 			return I2S_IO_6CH_OUT_4CH_IN;
743 		case I2S_CHN_8:
744 			return I2S_IO_8CH_OUT_2CH_IN;
745 		default:
746 			return I2S_IO_2CH_OUT_8CH_IN;
747 		}
748 	}
749 }
750 
751 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
752 				     struct snd_soc_dai *dai)
753 {
754 	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
755 	int usable_chs = MULTIPLEX_CH_MAX;
756 	unsigned int val = 0;
757 
758 	if (!i2s_tdm->io_multiplex)
759 		return 0;
760 
761 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
762 		struct snd_pcm_str *playback_str =
763 			&substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
764 
765 		if (playback_str->substream_opened) {
766 			regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
767 			val &= I2S_TXCR_CSR_MASK;
768 			usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
769 		}
770 
771 		regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
772 		val &= I2S_RXCR_CSR_MASK;
773 
774 		if (to_ch_num(val) > usable_chs) {
775 			dev_err(i2s_tdm->dev,
776 				"Capture channels (%d) > usable channels (%d)\n",
777 				to_ch_num(val), usable_chs);
778 			return -EINVAL;
779 		}
780 
781 		rockchip_i2s_ch_to_io(val, true);
782 	} else {
783 		struct snd_pcm_str *capture_str =
784 			&substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
785 
786 		if (capture_str->substream_opened) {
787 			regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
788 			val &= I2S_RXCR_CSR_MASK;
789 			usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
790 		}
791 
792 		regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
793 		val &= I2S_TXCR_CSR_MASK;
794 
795 		if (to_ch_num(val) > usable_chs) {
796 			dev_err(i2s_tdm->dev,
797 				"Playback channels (%d) > usable channels (%d)\n",
798 				to_ch_num(val), usable_chs);
799 			return -EINVAL;
800 		}
801 	}
802 
803 	val <<= i2s_tdm->soc_data->grf_shift;
804 	val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
805 	regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
806 
807 	return 0;
808 }
809 
810 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
811 				  struct snd_soc_dai *dai,
812 				  unsigned int div_bclk,
813 				  unsigned int div_lrck,
814 				  unsigned int fmt)
815 {
816 	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
817 	unsigned long flags;
818 
819 	if (!i2s_tdm->clk_trcm)
820 		return 0;
821 
822 	spin_lock_irqsave(&i2s_tdm->lock, flags);
823 	if (i2s_tdm->refcount)
824 		rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
825 
826 	regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
827 			   I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
828 			   I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
829 	regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
830 			   I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
831 			   I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
832 
833 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
834 		regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
835 				   I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
836 				   fmt);
837 	else
838 		regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
839 				   I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
840 				   fmt);
841 
842 	if (i2s_tdm->refcount)
843 		rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
844 	spin_unlock_irqrestore(&i2s_tdm->lock, flags);
845 
846 	return 0;
847 }
848 
849 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
850 				      struct snd_pcm_hw_params *params,
851 				      struct snd_soc_dai *dai)
852 {
853 	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
854 	struct clk *mclk;
855 	int ret = 0;
856 	unsigned int val = 0;
857 	unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
858 
859 	if (i2s_tdm->is_master_mode) {
860 		if (i2s_tdm->mclk_calibrate)
861 			rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
862 							params_rate(params));
863 
864 		ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
865 		if (ret)
866 			return ret;
867 
868 		mclk_rate = clk_get_rate(mclk);
869 		bclk_rate = i2s_tdm->frame_width * params_rate(params);
870 		if (!bclk_rate)
871 			return -EINVAL;
872 
873 		div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
874 		div_lrck = bclk_rate / params_rate(params);
875 	}
876 
877 	switch (params_format(params)) {
878 	case SNDRV_PCM_FORMAT_S8:
879 		val |= I2S_TXCR_VDW(8);
880 		break;
881 	case SNDRV_PCM_FORMAT_S16_LE:
882 		val |= I2S_TXCR_VDW(16);
883 		break;
884 	case SNDRV_PCM_FORMAT_S20_3LE:
885 		val |= I2S_TXCR_VDW(20);
886 		break;
887 	case SNDRV_PCM_FORMAT_S24_LE:
888 		val |= I2S_TXCR_VDW(24);
889 		break;
890 	case SNDRV_PCM_FORMAT_S32_LE:
891 		val |= I2S_TXCR_VDW(32);
892 		break;
893 	default:
894 		return -EINVAL;
895 	}
896 
897 	switch (params_channels(params)) {
898 	case 8:
899 		val |= I2S_CHN_8;
900 		break;
901 	case 6:
902 		val |= I2S_CHN_6;
903 		break;
904 	case 4:
905 		val |= I2S_CHN_4;
906 		break;
907 	case 2:
908 		val |= I2S_CHN_2;
909 		break;
910 	default:
911 		return -EINVAL;
912 	}
913 
914 	if (i2s_tdm->clk_trcm) {
915 		rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
916 	} else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
917 		regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
918 				   I2S_CLKDIV_TXM_MASK,
919 				   I2S_CLKDIV_TXM(div_bclk));
920 		regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
921 				   I2S_CKR_TSD_MASK,
922 				   I2S_CKR_TSD(div_lrck));
923 		regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
924 				   I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
925 				   val);
926 	} else {
927 		regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
928 				   I2S_CLKDIV_RXM_MASK,
929 				   I2S_CLKDIV_RXM(div_bclk));
930 		regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
931 				   I2S_CKR_RSD_MASK,
932 				   I2S_CKR_RSD(div_lrck));
933 		regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
934 				   I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
935 				   val);
936 	}
937 
938 	return rockchip_i2s_io_multiplex(substream, dai);
939 }
940 
941 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
942 				    int cmd, struct snd_soc_dai *dai)
943 {
944 	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
945 
946 	switch (cmd) {
947 	case SNDRV_PCM_TRIGGER_START:
948 	case SNDRV_PCM_TRIGGER_RESUME:
949 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
950 		if (i2s_tdm->clk_trcm)
951 			rockchip_snd_txrxctrl(substream, dai, 1);
952 		else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
953 			rockchip_snd_rxctrl(i2s_tdm, 1);
954 		else
955 			rockchip_snd_txctrl(i2s_tdm, 1);
956 		break;
957 	case SNDRV_PCM_TRIGGER_SUSPEND:
958 	case SNDRV_PCM_TRIGGER_STOP:
959 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
960 		if (i2s_tdm->clk_trcm)
961 			rockchip_snd_txrxctrl(substream, dai, 0);
962 		else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
963 			rockchip_snd_rxctrl(i2s_tdm, 0);
964 		else
965 			rockchip_snd_txctrl(i2s_tdm, 0);
966 		break;
967 	default:
968 		return -EINVAL;
969 	}
970 
971 	return 0;
972 }
973 
974 static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
975 				       unsigned int freq, int dir)
976 {
977 	struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
978 
979 	/* Put set mclk rate into rockchip_i2s_tdm_set_mclk() */
980 	if (i2s_tdm->clk_trcm) {
981 		i2s_tdm->mclk_tx_freq = freq;
982 		i2s_tdm->mclk_rx_freq = freq;
983 	} else {
984 		if (stream == SNDRV_PCM_STREAM_PLAYBACK)
985 			i2s_tdm->mclk_tx_freq = freq;
986 		else
987 			i2s_tdm->mclk_rx_freq = freq;
988 	}
989 
990 	dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
991 		stream ? "rx" : "tx", freq);
992 
993 	return 0;
994 }
995 
996 static int rockchip_i2s_tdm_clk_compensation_info(struct snd_kcontrol *kcontrol,
997 						  struct snd_ctl_elem_info *uinfo)
998 {
999 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1000 	uinfo->count = 1;
1001 	uinfo->value.integer.min = CLK_PPM_MIN;
1002 	uinfo->value.integer.max = CLK_PPM_MAX;
1003 	uinfo->value.integer.step = 1;
1004 
1005 	return 0;
1006 }
1007 
1008 static int rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
1009 						 struct snd_ctl_elem_value *ucontrol)
1010 {
1011 	struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1012 	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1013 
1014 	ucontrol->value.integer.value[0] = i2s_tdm->clk_ppm;
1015 
1016 	return 0;
1017 }
1018 
1019 static int rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
1020 						 struct snd_ctl_elem_value *ucontrol)
1021 {
1022 	struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1023 	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1024 	int ret = 0, ppm = 0;
1025 	int changed = 0;
1026 	unsigned long old_rate;
1027 
1028 	if (ucontrol->value.integer.value[0] < CLK_PPM_MIN ||
1029 	    ucontrol->value.integer.value[0] > CLK_PPM_MAX)
1030 		return -EINVAL;
1031 
1032 	ppm = ucontrol->value.integer.value[0];
1033 
1034 	old_rate = clk_get_rate(i2s_tdm->mclk_root0);
1035 	ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root0,
1036 					    i2s_tdm->mclk_root0_freq, ppm);
1037 	if (ret)
1038 		return ret;
1039 	if (old_rate != clk_get_rate(i2s_tdm->mclk_root0))
1040 		changed = 1;
1041 
1042 	if (clk_is_match(i2s_tdm->mclk_root0, i2s_tdm->mclk_root1))
1043 		return changed;
1044 
1045 	old_rate = clk_get_rate(i2s_tdm->mclk_root1);
1046 	ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root1,
1047 					    i2s_tdm->mclk_root1_freq, ppm);
1048 	if (ret)
1049 		return ret;
1050 	if (old_rate != clk_get_rate(i2s_tdm->mclk_root1))
1051 		changed = 1;
1052 
1053 	return changed;
1054 }
1055 
1056 static struct snd_kcontrol_new rockchip_i2s_tdm_compensation_control = {
1057 	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1058 	.name = "PCM Clock Compensation in PPM",
1059 	.info = rockchip_i2s_tdm_clk_compensation_info,
1060 	.get = rockchip_i2s_tdm_clk_compensation_get,
1061 	.put = rockchip_i2s_tdm_clk_compensation_put,
1062 };
1063 
1064 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
1065 {
1066 	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1067 
1068 	if (i2s_tdm->has_capture)
1069 		dai->capture_dma_data = &i2s_tdm->capture_dma_data;
1070 	if (i2s_tdm->has_playback)
1071 		dai->playback_dma_data = &i2s_tdm->playback_dma_data;
1072 
1073 	if (i2s_tdm->mclk_calibrate)
1074 		snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1);
1075 
1076 	return 0;
1077 }
1078 
1079 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
1080 				 unsigned int tx_mask, unsigned int rx_mask,
1081 				 int slots, int slot_width)
1082 {
1083 	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1084 	unsigned int mask, val;
1085 
1086 	i2s_tdm->tdm_mode = true;
1087 	i2s_tdm->frame_width = slots * slot_width;
1088 	mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
1089 	val = TDM_SLOT_BIT_WIDTH(slot_width) |
1090 	      TDM_FRAME_WIDTH(slots * slot_width);
1091 	regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
1092 			   mask, val);
1093 	regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
1094 			   mask, val);
1095 
1096 	return 0;
1097 }
1098 
1099 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
1100 					   unsigned int ratio)
1101 {
1102 	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1103 
1104 	if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
1105 		return -EINVAL;
1106 
1107 	i2s_tdm->frame_width = ratio;
1108 
1109 	return 0;
1110 }
1111 
1112 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
1113 	.hw_params = rockchip_i2s_tdm_hw_params,
1114 	.set_bclk_ratio	= rockchip_i2s_tdm_set_bclk_ratio,
1115 	.set_sysclk = rockchip_i2s_tdm_set_sysclk,
1116 	.set_fmt = rockchip_i2s_tdm_set_fmt,
1117 	.set_tdm_slot = rockchip_dai_tdm_slot,
1118 	.trigger = rockchip_i2s_tdm_trigger,
1119 };
1120 
1121 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
1122 	.name = DRV_NAME,
1123 };
1124 
1125 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
1126 {
1127 	switch (reg) {
1128 	case I2S_TXCR:
1129 	case I2S_RXCR:
1130 	case I2S_CKR:
1131 	case I2S_DMACR:
1132 	case I2S_INTCR:
1133 	case I2S_XFER:
1134 	case I2S_CLR:
1135 	case I2S_TXDR:
1136 	case I2S_TDM_TXCR:
1137 	case I2S_TDM_RXCR:
1138 	case I2S_CLKDIV:
1139 		return true;
1140 	default:
1141 		return false;
1142 	}
1143 }
1144 
1145 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
1146 {
1147 	switch (reg) {
1148 	case I2S_TXCR:
1149 	case I2S_RXCR:
1150 	case I2S_CKR:
1151 	case I2S_DMACR:
1152 	case I2S_INTCR:
1153 	case I2S_XFER:
1154 	case I2S_CLR:
1155 	case I2S_TXDR:
1156 	case I2S_RXDR:
1157 	case I2S_TXFIFOLR:
1158 	case I2S_INTSR:
1159 	case I2S_RXFIFOLR:
1160 	case I2S_TDM_TXCR:
1161 	case I2S_TDM_RXCR:
1162 	case I2S_CLKDIV:
1163 		return true;
1164 	default:
1165 		return false;
1166 	}
1167 }
1168 
1169 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
1170 {
1171 	switch (reg) {
1172 	case I2S_TXFIFOLR:
1173 	case I2S_INTSR:
1174 	case I2S_CLR:
1175 	case I2S_TXDR:
1176 	case I2S_RXDR:
1177 	case I2S_RXFIFOLR:
1178 		return true;
1179 	default:
1180 		return false;
1181 	}
1182 }
1183 
1184 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
1185 {
1186 	if (reg == I2S_RXDR)
1187 		return true;
1188 	return false;
1189 }
1190 
1191 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
1192 	{0x00, 0x7200000f},
1193 	{0x04, 0x01c8000f},
1194 	{0x08, 0x00001f1f},
1195 	{0x10, 0x001f0000},
1196 	{0x14, 0x01f00000},
1197 	{0x30, 0x00003eff},
1198 	{0x34, 0x00003eff},
1199 	{0x38, 0x00000707},
1200 };
1201 
1202 static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
1203 	.reg_bits = 32,
1204 	.reg_stride = 4,
1205 	.val_bits = 32,
1206 	.max_register = I2S_CLKDIV,
1207 	.reg_defaults = rockchip_i2s_tdm_reg_defaults,
1208 	.num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
1209 	.writeable_reg = rockchip_i2s_tdm_wr_reg,
1210 	.readable_reg = rockchip_i2s_tdm_rd_reg,
1211 	.volatile_reg = rockchip_i2s_tdm_volatile_reg,
1212 	.precious_reg = rockchip_i2s_tdm_precious_reg,
1213 	.cache_type = REGCACHE_FLAT,
1214 };
1215 
1216 static int common_soc_init(struct device *dev, u32 addr)
1217 {
1218 	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1219 	const struct txrx_config *configs = i2s_tdm->soc_data->configs;
1220 	u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
1221 	int i;
1222 
1223 	if (trcm == TRCM_TXRX)
1224 		return 0;
1225 
1226 	for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
1227 		if (addr != configs[i].addr)
1228 			continue;
1229 		reg = configs[i].reg;
1230 		if (trcm == TRCM_TX)
1231 			val = configs[i].txonly;
1232 		else
1233 			val = configs[i].rxonly;
1234 
1235 		if (reg)
1236 			regmap_write(i2s_tdm->grf, reg, val);
1237 	}
1238 
1239 	return 0;
1240 }
1241 
1242 static const struct txrx_config px30_txrx_config[] = {
1243 	{ 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
1244 };
1245 
1246 static const struct txrx_config rk1808_txrx_config[] = {
1247 	{ 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
1248 };
1249 
1250 static const struct txrx_config rk3308_txrx_config[] = {
1251 	{ 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
1252 	{ 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
1253 };
1254 
1255 static const struct txrx_config rk3568_txrx_config[] = {
1256 	{ 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
1257 	{ 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
1258 	{ 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
1259 	{ 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
1260 	{ 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
1261 	{ 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
1262 };
1263 
1264 static const struct txrx_config rv1126_txrx_config[] = {
1265 	{ 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
1266 };
1267 
1268 static struct rk_i2s_soc_data px30_i2s_soc_data = {
1269 	.softrst_offset = 0x0300,
1270 	.configs = px30_txrx_config,
1271 	.config_count = ARRAY_SIZE(px30_txrx_config),
1272 	.init = common_soc_init,
1273 };
1274 
1275 static struct rk_i2s_soc_data rk1808_i2s_soc_data = {
1276 	.softrst_offset = 0x0300,
1277 	.configs = rk1808_txrx_config,
1278 	.config_count = ARRAY_SIZE(rk1808_txrx_config),
1279 	.init = common_soc_init,
1280 };
1281 
1282 static struct rk_i2s_soc_data rk3308_i2s_soc_data = {
1283 	.softrst_offset = 0x0400,
1284 	.grf_reg_offset = 0x0308,
1285 	.grf_shift = 5,
1286 	.configs = rk3308_txrx_config,
1287 	.config_count = ARRAY_SIZE(rk3308_txrx_config),
1288 	.init = common_soc_init,
1289 };
1290 
1291 static struct rk_i2s_soc_data rk3568_i2s_soc_data = {
1292 	.softrst_offset = 0x0400,
1293 	.configs = rk3568_txrx_config,
1294 	.config_count = ARRAY_SIZE(rk3568_txrx_config),
1295 	.init = common_soc_init,
1296 };
1297 
1298 static struct rk_i2s_soc_data rv1126_i2s_soc_data = {
1299 	.softrst_offset = 0x0300,
1300 	.configs = rv1126_txrx_config,
1301 	.config_count = ARRAY_SIZE(rv1126_txrx_config),
1302 	.init = common_soc_init,
1303 };
1304 
1305 static const struct of_device_id rockchip_i2s_tdm_match[] = {
1306 	{ .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
1307 	{ .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
1308 	{ .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
1309 	{ .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1310 	{ .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1311 	{},
1312 };
1313 
1314 static const struct snd_soc_dai_driver i2s_tdm_dai = {
1315 	.probe = rockchip_i2s_tdm_dai_probe,
1316 	.ops = &rockchip_i2s_tdm_dai_ops,
1317 };
1318 
1319 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
1320 {
1321 	struct snd_soc_dai_driver *dai;
1322 	struct property *dma_names;
1323 	const char *dma_name;
1324 	u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
1325 		       SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
1326 		       SNDRV_PCM_FMTBIT_S32_LE);
1327 	struct device_node *node = i2s_tdm->dev->of_node;
1328 
1329 	of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1330 		if (!strcmp(dma_name, "tx"))
1331 			i2s_tdm->has_playback = true;
1332 		if (!strcmp(dma_name, "rx"))
1333 			i2s_tdm->has_capture = true;
1334 	}
1335 
1336 	dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
1337 			   sizeof(*dai), GFP_KERNEL);
1338 	if (!dai)
1339 		return -ENOMEM;
1340 
1341 	if (i2s_tdm->has_playback) {
1342 		dai->playback.stream_name  = "Playback";
1343 		dai->playback.channels_min = 2;
1344 		dai->playback.channels_max = 8;
1345 		dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
1346 		dai->playback.formats = formats;
1347 	}
1348 
1349 	if (i2s_tdm->has_capture) {
1350 		dai->capture.stream_name  = "Capture";
1351 		dai->capture.channels_min = 2;
1352 		dai->capture.channels_max = 8;
1353 		dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
1354 		dai->capture.formats = formats;
1355 	}
1356 
1357 	if (i2s_tdm->clk_trcm != TRCM_TXRX)
1358 		dai->symmetric_rate = 1;
1359 
1360 	i2s_tdm->dai = dai;
1361 
1362 	return 0;
1363 }
1364 
1365 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
1366 				       int num,
1367 				       bool is_rx_path)
1368 {
1369 	unsigned int *i2s_data;
1370 	int i, j;
1371 
1372 	if (is_rx_path)
1373 		i2s_data = i2s_tdm->i2s_sdis;
1374 	else
1375 		i2s_data = i2s_tdm->i2s_sdos;
1376 
1377 	for (i = 0; i < num; i++) {
1378 		if (i2s_data[i] > CH_GRP_MAX - 1) {
1379 			dev_err(i2s_tdm->dev,
1380 				"%s path i2s_data[%d]: %d is too high, max is: %d\n",
1381 				is_rx_path ? "RX" : "TX",
1382 				i, i2s_data[i], CH_GRP_MAX);
1383 			return -EINVAL;
1384 		}
1385 
1386 		for (j = 0; j < num; j++) {
1387 			if (i == j)
1388 				continue;
1389 
1390 			if (i2s_data[i] == i2s_data[j]) {
1391 				dev_err(i2s_tdm->dev,
1392 					"%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
1393 					is_rx_path ? "RX" : "TX",
1394 					i, i2s_data[i],
1395 					j, i2s_data[j]);
1396 				return -EINVAL;
1397 			}
1398 		}
1399 	}
1400 
1401 	return 0;
1402 }
1403 
1404 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1405 					    int num)
1406 {
1407 	int idx;
1408 
1409 	for (idx = 0; idx < num; idx++) {
1410 		regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1411 				   I2S_TXCR_PATH_MASK(idx),
1412 				   I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
1413 	}
1414 }
1415 
1416 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1417 					    int num)
1418 {
1419 	int idx;
1420 
1421 	for (idx = 0; idx < num; idx++) {
1422 		regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1423 				   I2S_RXCR_PATH_MASK(idx),
1424 				   I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
1425 	}
1426 }
1427 
1428 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1429 					 int num, bool is_rx_path)
1430 {
1431 	if (is_rx_path)
1432 		rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
1433 	else
1434 		rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
1435 }
1436 
1437 static int rockchip_i2s_tdm_get_calibrate_mclks(struct rk_i2s_tdm_dev *i2s_tdm)
1438 {
1439 	int num_mclks = 0;
1440 
1441 	i2s_tdm->mclk_tx_src = devm_clk_get(i2s_tdm->dev, "mclk_tx_src");
1442 	if (!IS_ERR(i2s_tdm->mclk_tx_src))
1443 		num_mclks++;
1444 
1445 	i2s_tdm->mclk_rx_src = devm_clk_get(i2s_tdm->dev, "mclk_rx_src");
1446 	if (!IS_ERR(i2s_tdm->mclk_rx_src))
1447 		num_mclks++;
1448 
1449 	i2s_tdm->mclk_root0 = devm_clk_get(i2s_tdm->dev, "mclk_root0");
1450 	if (!IS_ERR(i2s_tdm->mclk_root0))
1451 		num_mclks++;
1452 
1453 	i2s_tdm->mclk_root1 = devm_clk_get(i2s_tdm->dev, "mclk_root1");
1454 	if (!IS_ERR(i2s_tdm->mclk_root1))
1455 		num_mclks++;
1456 
1457 	if (num_mclks < 4 && num_mclks != 0)
1458 		return -ENOENT;
1459 
1460 	if (num_mclks == 4)
1461 		i2s_tdm->mclk_calibrate = 1;
1462 
1463 	return 0;
1464 }
1465 
1466 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1467 					 struct device_node *np,
1468 					 bool is_rx_path)
1469 {
1470 	char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
1471 	char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
1472 	char *i2s_path_prop;
1473 	unsigned int *i2s_data;
1474 	int num, ret = 0;
1475 
1476 	if (is_rx_path) {
1477 		i2s_path_prop = i2s_rx_path_prop;
1478 		i2s_data = i2s_tdm->i2s_sdis;
1479 	} else {
1480 		i2s_path_prop = i2s_tx_path_prop;
1481 		i2s_data = i2s_tdm->i2s_sdos;
1482 	}
1483 
1484 	num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
1485 	if (num < 0) {
1486 		if (num != -ENOENT) {
1487 			dev_err(i2s_tdm->dev,
1488 				"Failed to read '%s' num: %d\n",
1489 				i2s_path_prop, num);
1490 			ret = num;
1491 		}
1492 		return ret;
1493 	} else if (num != CH_GRP_MAX) {
1494 		dev_err(i2s_tdm->dev,
1495 			"The num: %d should be: %d\n", num, CH_GRP_MAX);
1496 		return -EINVAL;
1497 	}
1498 
1499 	ret = of_property_read_u32_array(np, i2s_path_prop,
1500 					 i2s_data, num);
1501 	if (ret < 0) {
1502 		dev_err(i2s_tdm->dev,
1503 			"Failed to read '%s': %d\n",
1504 			i2s_path_prop, ret);
1505 		return ret;
1506 	}
1507 
1508 	ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
1509 	if (ret < 0) {
1510 		dev_err(i2s_tdm->dev,
1511 			"Failed to check i2s data bus: %d\n", ret);
1512 		return ret;
1513 	}
1514 
1515 	rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
1516 
1517 	return 0;
1518 }
1519 
1520 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1521 					    struct device_node *np)
1522 {
1523 	return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
1524 }
1525 
1526 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1527 					    struct device_node *np)
1528 {
1529 	return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1530 }
1531 
1532 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1533 {
1534 	struct device_node *node = pdev->dev.of_node;
1535 	const struct of_device_id *of_id;
1536 	struct rk_i2s_tdm_dev *i2s_tdm;
1537 	struct resource *res;
1538 	void __iomem *regs;
1539 	int ret;
1540 
1541 	i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
1542 	if (!i2s_tdm)
1543 		return -ENOMEM;
1544 
1545 	i2s_tdm->dev = &pdev->dev;
1546 
1547 	of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
1548 	if (!of_id || !of_id->data)
1549 		return -EINVAL;
1550 
1551 	spin_lock_init(&i2s_tdm->lock);
1552 	i2s_tdm->soc_data = (struct rk_i2s_soc_data *)of_id->data;
1553 
1554 	i2s_tdm->frame_width = 64;
1555 
1556 	i2s_tdm->clk_trcm = TRCM_TXRX;
1557 	if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
1558 		i2s_tdm->clk_trcm = TRCM_TX;
1559 	if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
1560 		if (i2s_tdm->clk_trcm) {
1561 			dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
1562 			return -EINVAL;
1563 		}
1564 		i2s_tdm->clk_trcm = TRCM_RX;
1565 	}
1566 
1567 	ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
1568 	if (ret)
1569 		return ret;
1570 
1571 	i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1572 	if (IS_ERR(i2s_tdm->grf))
1573 		return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->grf),
1574 				     "Error in rockchip,grf\n");
1575 
1576 	i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1577 								      "tx-m");
1578 	if (IS_ERR(i2s_tdm->tx_reset)) {
1579 		ret = PTR_ERR(i2s_tdm->tx_reset);
1580 		return dev_err_probe(i2s_tdm->dev, ret,
1581 				     "Error in tx-m reset control\n");
1582 	}
1583 
1584 	i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1585 								      "rx-m");
1586 	if (IS_ERR(i2s_tdm->rx_reset)) {
1587 		ret = PTR_ERR(i2s_tdm->rx_reset);
1588 		return dev_err_probe(i2s_tdm->dev, ret,
1589 				     "Error in rx-m reset control\n");
1590 	}
1591 
1592 	i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
1593 	if (IS_ERR(i2s_tdm->hclk)) {
1594 		return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
1595 				     "Failed to get clock hclk\n");
1596 	}
1597 
1598 	i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
1599 	if (IS_ERR(i2s_tdm->mclk_tx)) {
1600 		return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
1601 				     "Failed to get clock mclk_tx\n");
1602 	}
1603 
1604 	i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
1605 	if (IS_ERR(i2s_tdm->mclk_rx)) {
1606 		return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
1607 				     "Failed to get clock mclk_rx\n");
1608 	}
1609 
1610 	i2s_tdm->io_multiplex =
1611 		of_property_read_bool(node, "rockchip,io-multiplex");
1612 
1613 	ret = rockchip_i2s_tdm_get_calibrate_mclks(i2s_tdm);
1614 	if (ret)
1615 		return dev_err_probe(i2s_tdm->dev, ret,
1616 				     "mclk-calibrate clocks missing");
1617 
1618 	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1619 	if (IS_ERR(regs)) {
1620 		return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
1621 				     "Failed to get resource IORESOURCE_MEM\n");
1622 	}
1623 
1624 	i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1625 						&rockchip_i2s_tdm_regmap_config);
1626 	if (IS_ERR(i2s_tdm->regmap)) {
1627 		return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
1628 				     "Failed to initialise regmap\n");
1629 	}
1630 
1631 	if (i2s_tdm->has_playback) {
1632 		i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1633 		i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1634 		i2s_tdm->playback_dma_data.maxburst = 8;
1635 	}
1636 
1637 	if (i2s_tdm->has_capture) {
1638 		i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1639 		i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1640 		i2s_tdm->capture_dma_data.maxburst = 8;
1641 	}
1642 
1643 	ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1644 	if (ret < 0) {
1645 		dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
1646 		return ret;
1647 	}
1648 
1649 	ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
1650 	if (ret < 0) {
1651 		dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
1652 		return ret;
1653 	}
1654 
1655 	dev_set_drvdata(&pdev->dev, i2s_tdm);
1656 
1657 	ret = clk_prepare_enable(i2s_tdm->hclk);
1658 	if (ret) {
1659 		return dev_err_probe(i2s_tdm->dev, ret,
1660 				     "Failed to enable clock hclk\n");
1661 	}
1662 
1663 	ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
1664 	if (ret) {
1665 		ret = dev_err_probe(i2s_tdm->dev, ret,
1666 				    "Failed to enable one or more mclks\n");
1667 		goto err_disable_hclk;
1668 	}
1669 
1670 	if (i2s_tdm->mclk_calibrate) {
1671 		i2s_tdm->mclk_root0_initial_freq = clk_get_rate(i2s_tdm->mclk_root0);
1672 		i2s_tdm->mclk_root1_initial_freq = clk_get_rate(i2s_tdm->mclk_root1);
1673 		i2s_tdm->mclk_root0_freq = i2s_tdm->mclk_root0_initial_freq;
1674 		i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
1675 	}
1676 
1677 	pm_runtime_enable(&pdev->dev);
1678 
1679 	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1680 			   I2S_DMACR_TDL(16));
1681 	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
1682 			   I2S_DMACR_RDL(16));
1683 	regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
1684 			   i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
1685 
1686 	if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1687 		i2s_tdm->soc_data->init(&pdev->dev, res->start);
1688 
1689 	ret = devm_snd_soc_register_component(&pdev->dev,
1690 					      &rockchip_i2s_tdm_component,
1691 					      i2s_tdm->dai, 1);
1692 
1693 	if (ret) {
1694 		dev_err(&pdev->dev, "Could not register DAI\n");
1695 		goto err_suspend;
1696 	}
1697 
1698 	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1699 	if (ret) {
1700 		dev_err(&pdev->dev, "Could not register PCM\n");
1701 		goto err_suspend;
1702 	}
1703 
1704 	return 0;
1705 
1706 err_suspend:
1707 	if (!pm_runtime_status_suspended(&pdev->dev))
1708 		i2s_tdm_runtime_suspend(&pdev->dev);
1709 	pm_runtime_disable(&pdev->dev);
1710 
1711 err_disable_hclk:
1712 	clk_disable_unprepare(i2s_tdm->hclk);
1713 
1714 	return ret;
1715 }
1716 
1717 static int rockchip_i2s_tdm_remove(struct platform_device *pdev)
1718 {
1719 	if (!pm_runtime_status_suspended(&pdev->dev))
1720 		i2s_tdm_runtime_suspend(&pdev->dev);
1721 
1722 	pm_runtime_disable(&pdev->dev);
1723 
1724 	return 0;
1725 }
1726 
1727 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev)
1728 {
1729 	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1730 
1731 	regcache_mark_dirty(i2s_tdm->regmap);
1732 
1733 	return 0;
1734 }
1735 
1736 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev)
1737 {
1738 	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1739 	int ret;
1740 
1741 	ret = pm_runtime_resume_and_get(dev);
1742 	if (ret < 0)
1743 		return ret;
1744 	ret = regcache_sync(i2s_tdm->regmap);
1745 	pm_runtime_put(dev);
1746 
1747 	return ret;
1748 }
1749 
1750 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
1751 	SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
1752 			   NULL)
1753 	SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
1754 				rockchip_i2s_tdm_resume)
1755 };
1756 
1757 static struct platform_driver rockchip_i2s_tdm_driver = {
1758 	.probe = rockchip_i2s_tdm_probe,
1759 	.remove = rockchip_i2s_tdm_remove,
1760 	.driver = {
1761 		.name = DRV_NAME,
1762 		.of_match_table = of_match_ptr(rockchip_i2s_tdm_match),
1763 		.pm = &rockchip_i2s_tdm_pm_ops,
1764 	},
1765 };
1766 module_platform_driver(rockchip_i2s_tdm_driver);
1767 
1768 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
1769 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1770 MODULE_LICENSE("GPL v2");
1771 MODULE_ALIAS("platform:" DRV_NAME);
1772 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);
1773