1 // SPDX-License-Identifier: GPL-2.0-only 2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver 3 4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd. 5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com> 6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_gpio.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/spinlock.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 23 #include "rockchip_i2s_tdm.h" 24 25 #define DRV_NAME "rockchip-i2s-tdm" 26 27 #define DEFAULT_MCLK_FS 256 28 #define CH_GRP_MAX 4 /* The max channel 8 / 2 */ 29 #define MULTIPLEX_CH_MAX 10 30 31 #define TRCM_TXRX 0 32 #define TRCM_TX 1 33 #define TRCM_RX 2 34 35 struct txrx_config { 36 u32 addr; 37 u32 reg; 38 u32 txonly; 39 u32 rxonly; 40 }; 41 42 struct rk_i2s_soc_data { 43 u32 softrst_offset; 44 u32 grf_reg_offset; 45 u32 grf_shift; 46 int config_count; 47 const struct txrx_config *configs; 48 int (*init)(struct device *dev, u32 addr); 49 }; 50 51 struct rk_i2s_tdm_dev { 52 struct device *dev; 53 struct clk *hclk; 54 struct clk *mclk_tx; 55 struct clk *mclk_rx; 56 struct regmap *regmap; 57 struct regmap *grf; 58 struct snd_dmaengine_dai_dma_data capture_dma_data; 59 struct snd_dmaengine_dai_dma_data playback_dma_data; 60 struct reset_control *tx_reset; 61 struct reset_control *rx_reset; 62 struct rk_i2s_soc_data *soc_data; 63 bool is_master_mode; 64 bool io_multiplex; 65 bool tdm_mode; 66 unsigned int frame_width; 67 unsigned int clk_trcm; 68 unsigned int i2s_sdis[CH_GRP_MAX]; 69 unsigned int i2s_sdos[CH_GRP_MAX]; 70 int refcount; 71 spinlock_t lock; /* xfer lock */ 72 bool has_playback; 73 bool has_capture; 74 struct snd_soc_dai_driver *dai; 75 }; 76 77 static int to_ch_num(unsigned int val) 78 { 79 switch (val) { 80 case I2S_CHN_4: 81 return 4; 82 case I2S_CHN_6: 83 return 6; 84 case I2S_CHN_8: 85 return 8; 86 default: 87 return 2; 88 } 89 } 90 91 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm) 92 { 93 clk_disable_unprepare(i2s_tdm->mclk_tx); 94 clk_disable_unprepare(i2s_tdm->mclk_rx); 95 } 96 97 /** 98 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on 99 * failure. 100 * @i2s_tdm: rk_i2s_tdm_dev struct 101 * 102 * This function attempts to enable all mclk clocks, but cleans up after 103 * itself on failure. Guarantees to balance its calls. 104 * 105 * Returns success (0) or negative errno. 106 */ 107 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm) 108 { 109 int ret = 0; 110 111 ret = clk_prepare_enable(i2s_tdm->mclk_tx); 112 if (ret) 113 goto err_mclk_tx; 114 ret = clk_prepare_enable(i2s_tdm->mclk_rx); 115 if (ret) 116 goto err_mclk_rx; 117 118 return 0; 119 120 err_mclk_rx: 121 clk_disable_unprepare(i2s_tdm->mclk_tx); 122 err_mclk_tx: 123 return ret; 124 } 125 126 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev) 127 { 128 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 129 130 regcache_cache_only(i2s_tdm->regmap, true); 131 i2s_tdm_disable_unprepare_mclk(i2s_tdm); 132 133 clk_disable_unprepare(i2s_tdm->hclk); 134 135 return 0; 136 } 137 138 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev) 139 { 140 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 141 int ret; 142 143 ret = clk_prepare_enable(i2s_tdm->hclk); 144 if (ret) 145 goto err_hclk; 146 147 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm); 148 if (ret) 149 goto err_mclk; 150 151 regcache_cache_only(i2s_tdm->regmap, false); 152 regcache_mark_dirty(i2s_tdm->regmap); 153 154 ret = regcache_sync(i2s_tdm->regmap); 155 if (ret) 156 goto err_regcache; 157 158 return 0; 159 160 err_regcache: 161 i2s_tdm_disable_unprepare_mclk(i2s_tdm); 162 err_mclk: 163 clk_disable_unprepare(i2s_tdm->hclk); 164 err_hclk: 165 return ret; 166 } 167 168 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai) 169 { 170 return snd_soc_dai_get_drvdata(dai); 171 } 172 173 /* 174 * Makes sure that both tx and rx are reset at the same time to sync lrck 175 * when clk_trcm > 0. 176 */ 177 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm) 178 { 179 /* This is technically race-y. 180 * 181 * In an ideal world, we could atomically assert both resets at the 182 * same time, through an atomic bulk reset API. This API however does 183 * not exist, so what the downstream vendor code used to do was 184 * implement half a reset controller here and require the CRU to be 185 * passed to the driver as a device tree node. Violating abstractions 186 * like that is bad, especially when it influences something like the 187 * bindings which are supposed to describe the hardware, not whatever 188 * workarounds the driver needs, so it was dropped. 189 * 190 * In practice, asserting the resets one by one appears to work just 191 * fine for playback. During duplex (playback + capture) operation, 192 * this might become an issue, but that should be solved by the 193 * implementation of the aforementioned API, not by shoving a reset 194 * controller into an audio driver. 195 */ 196 197 reset_control_assert(i2s_tdm->tx_reset); 198 reset_control_assert(i2s_tdm->rx_reset); 199 udelay(10); 200 reset_control_deassert(i2s_tdm->tx_reset); 201 reset_control_deassert(i2s_tdm->rx_reset); 202 udelay(10); 203 } 204 205 static void rockchip_snd_reset(struct reset_control *rc) 206 { 207 reset_control_assert(rc); 208 udelay(10); 209 reset_control_deassert(rc); 210 udelay(10); 211 } 212 213 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm, 214 unsigned int clr) 215 { 216 unsigned int xfer_mask = 0; 217 unsigned int xfer_val = 0; 218 unsigned int val; 219 int retry = 10; 220 bool tx = clr & I2S_CLR_TXC; 221 bool rx = clr & I2S_CLR_RXC; 222 223 if (!(rx || tx)) 224 return; 225 226 if (tx) { 227 xfer_mask = I2S_XFER_TXS_START; 228 xfer_val = I2S_XFER_TXS_STOP; 229 } 230 if (rx) { 231 xfer_mask |= I2S_XFER_RXS_START; 232 xfer_val |= I2S_XFER_RXS_STOP; 233 } 234 235 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val); 236 udelay(150); 237 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr); 238 239 regmap_read(i2s_tdm->regmap, I2S_CLR, &val); 240 /* Wait on the clear operation to finish */ 241 while (val) { 242 udelay(15); 243 regmap_read(i2s_tdm->regmap, I2S_CLR, &val); 244 retry--; 245 if (!retry) { 246 dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n", 247 tx ? "tx" : "", rx ? "rx" : ""); 248 if (rx && tx) 249 rockchip_snd_xfer_sync_reset(i2s_tdm); 250 else if (tx) 251 rockchip_snd_reset(i2s_tdm->tx_reset); 252 else if (rx) 253 rockchip_snd_reset(i2s_tdm->rx_reset); 254 break; 255 } 256 } 257 } 258 259 static inline void rockchip_enable_tde(struct regmap *regmap) 260 { 261 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, 262 I2S_DMACR_TDE_ENABLE); 263 } 264 265 static inline void rockchip_disable_tde(struct regmap *regmap) 266 { 267 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, 268 I2S_DMACR_TDE_DISABLE); 269 } 270 271 static inline void rockchip_enable_rde(struct regmap *regmap) 272 { 273 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, 274 I2S_DMACR_RDE_ENABLE); 275 } 276 277 static inline void rockchip_disable_rde(struct regmap *regmap) 278 { 279 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, 280 I2S_DMACR_RDE_DISABLE); 281 } 282 283 /* only used when clk_trcm > 0 */ 284 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream, 285 struct snd_soc_dai *dai, int on) 286 { 287 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 288 unsigned long flags; 289 290 spin_lock_irqsave(&i2s_tdm->lock, flags); 291 if (on) { 292 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 293 rockchip_enable_tde(i2s_tdm->regmap); 294 else 295 rockchip_enable_rde(i2s_tdm->regmap); 296 297 if (++i2s_tdm->refcount == 1) { 298 rockchip_snd_xfer_sync_reset(i2s_tdm); 299 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 300 I2S_XFER_TXS_START | 301 I2S_XFER_RXS_START, 302 I2S_XFER_TXS_START | 303 I2S_XFER_RXS_START); 304 } 305 } else { 306 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 307 rockchip_disable_tde(i2s_tdm->regmap); 308 else 309 rockchip_disable_rde(i2s_tdm->regmap); 310 311 if (--i2s_tdm->refcount == 0) { 312 rockchip_snd_xfer_clear(i2s_tdm, 313 I2S_CLR_TXC | I2S_CLR_RXC); 314 } 315 } 316 spin_unlock_irqrestore(&i2s_tdm->lock, flags); 317 } 318 319 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on) 320 { 321 if (on) { 322 rockchip_enable_tde(i2s_tdm->regmap); 323 324 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 325 I2S_XFER_TXS_START, 326 I2S_XFER_TXS_START); 327 } else { 328 rockchip_disable_tde(i2s_tdm->regmap); 329 330 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC); 331 } 332 } 333 334 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on) 335 { 336 if (on) { 337 rockchip_enable_rde(i2s_tdm->regmap); 338 339 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 340 I2S_XFER_RXS_START, 341 I2S_XFER_RXS_START); 342 } else { 343 rockchip_disable_rde(i2s_tdm->regmap); 344 345 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC); 346 } 347 } 348 349 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai, 350 unsigned int fmt) 351 { 352 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai); 353 unsigned int mask, val, tdm_val, txcr_val, rxcr_val; 354 int ret; 355 bool is_tdm = i2s_tdm->tdm_mode; 356 357 ret = pm_runtime_resume_and_get(cpu_dai->dev); 358 if (ret < 0 && ret != -EACCES) 359 return ret; 360 361 mask = I2S_CKR_MSS_MASK; 362 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 363 case SND_SOC_DAIFMT_BP_FP: 364 val = I2S_CKR_MSS_MASTER; 365 i2s_tdm->is_master_mode = true; 366 break; 367 case SND_SOC_DAIFMT_BC_FC: 368 val = I2S_CKR_MSS_SLAVE; 369 i2s_tdm->is_master_mode = false; 370 break; 371 default: 372 ret = -EINVAL; 373 goto err_pm_put; 374 } 375 376 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val); 377 378 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK; 379 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 380 case SND_SOC_DAIFMT_NB_NF: 381 val = I2S_CKR_CKP_NORMAL | 382 I2S_CKR_TLP_NORMAL | 383 I2S_CKR_RLP_NORMAL; 384 break; 385 case SND_SOC_DAIFMT_NB_IF: 386 val = I2S_CKR_CKP_NORMAL | 387 I2S_CKR_TLP_INVERTED | 388 I2S_CKR_RLP_INVERTED; 389 break; 390 case SND_SOC_DAIFMT_IB_NF: 391 val = I2S_CKR_CKP_INVERTED | 392 I2S_CKR_TLP_NORMAL | 393 I2S_CKR_RLP_NORMAL; 394 break; 395 case SND_SOC_DAIFMT_IB_IF: 396 val = I2S_CKR_CKP_INVERTED | 397 I2S_CKR_TLP_INVERTED | 398 I2S_CKR_RLP_INVERTED; 399 break; 400 default: 401 ret = -EINVAL; 402 goto err_pm_put; 403 } 404 405 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val); 406 407 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 408 case SND_SOC_DAIFMT_RIGHT_J: 409 txcr_val = I2S_TXCR_IBM_RSJM; 410 rxcr_val = I2S_RXCR_IBM_RSJM; 411 break; 412 case SND_SOC_DAIFMT_LEFT_J: 413 txcr_val = I2S_TXCR_IBM_LSJM; 414 rxcr_val = I2S_RXCR_IBM_LSJM; 415 break; 416 case SND_SOC_DAIFMT_I2S: 417 txcr_val = I2S_TXCR_IBM_NORMAL; 418 rxcr_val = I2S_RXCR_IBM_NORMAL; 419 break; 420 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */ 421 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); 422 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); 423 break; 424 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 425 txcr_val = I2S_TXCR_TFS_PCM; 426 rxcr_val = I2S_RXCR_TFS_PCM; 427 break; 428 default: 429 ret = -EINVAL; 430 goto err_pm_put; 431 } 432 433 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; 434 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val); 435 436 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; 437 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val); 438 439 if (is_tdm) { 440 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 441 case SND_SOC_DAIFMT_RIGHT_J: 442 val = I2S_TXCR_TFS_TDM_I2S; 443 tdm_val = TDM_SHIFT_CTRL(2); 444 break; 445 case SND_SOC_DAIFMT_LEFT_J: 446 val = I2S_TXCR_TFS_TDM_I2S; 447 tdm_val = TDM_SHIFT_CTRL(1); 448 break; 449 case SND_SOC_DAIFMT_I2S: 450 val = I2S_TXCR_TFS_TDM_I2S; 451 tdm_val = TDM_SHIFT_CTRL(0); 452 break; 453 case SND_SOC_DAIFMT_DSP_A: 454 val = I2S_TXCR_TFS_TDM_PCM; 455 tdm_val = TDM_SHIFT_CTRL(0); 456 break; 457 case SND_SOC_DAIFMT_DSP_B: 458 val = I2S_TXCR_TFS_TDM_PCM; 459 tdm_val = TDM_SHIFT_CTRL(2); 460 break; 461 default: 462 ret = -EINVAL; 463 goto err_pm_put; 464 } 465 466 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1); 467 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME; 468 469 mask = I2S_TXCR_TFS_MASK; 470 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val); 471 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val); 472 473 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK | 474 TDM_SHIFT_CTRL_MSK; 475 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR, 476 mask, tdm_val); 477 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR, 478 mask, tdm_val); 479 } 480 481 err_pm_put: 482 pm_runtime_put(cpu_dai->dev); 483 484 return ret; 485 } 486 487 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream, 488 struct rk_i2s_tdm_dev *i2s_tdm) 489 { 490 int stream; 491 492 stream = SNDRV_PCM_STREAM_LAST - substream->stream; 493 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 494 rockchip_disable_tde(i2s_tdm->regmap); 495 else 496 rockchip_disable_rde(i2s_tdm->regmap); 497 498 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC); 499 } 500 501 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream, 502 struct rk_i2s_tdm_dev *i2s_tdm) 503 { 504 int stream; 505 506 stream = SNDRV_PCM_STREAM_LAST - substream->stream; 507 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 508 rockchip_enable_tde(i2s_tdm->regmap); 509 else 510 rockchip_enable_rde(i2s_tdm->regmap); 511 512 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 513 I2S_XFER_TXS_START | 514 I2S_XFER_RXS_START, 515 I2S_XFER_TXS_START | 516 I2S_XFER_RXS_START); 517 } 518 519 static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture) 520 { 521 if (substream_capture) { 522 switch (ch) { 523 case I2S_CHN_4: 524 return I2S_IO_6CH_OUT_4CH_IN; 525 case I2S_CHN_6: 526 return I2S_IO_4CH_OUT_6CH_IN; 527 case I2S_CHN_8: 528 return I2S_IO_2CH_OUT_8CH_IN; 529 default: 530 return I2S_IO_8CH_OUT_2CH_IN; 531 } 532 } else { 533 switch (ch) { 534 case I2S_CHN_4: 535 return I2S_IO_4CH_OUT_6CH_IN; 536 case I2S_CHN_6: 537 return I2S_IO_6CH_OUT_4CH_IN; 538 case I2S_CHN_8: 539 return I2S_IO_8CH_OUT_2CH_IN; 540 default: 541 return I2S_IO_2CH_OUT_8CH_IN; 542 } 543 } 544 } 545 546 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream, 547 struct snd_soc_dai *dai) 548 { 549 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 550 int usable_chs = MULTIPLEX_CH_MAX; 551 unsigned int val = 0; 552 553 if (!i2s_tdm->io_multiplex) 554 return 0; 555 556 if (IS_ERR_OR_NULL(i2s_tdm->grf)) { 557 dev_err(i2s_tdm->dev, 558 "io multiplex not supported for this device\n"); 559 return -EINVAL; 560 } 561 562 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 563 struct snd_pcm_str *playback_str = 564 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK]; 565 566 if (playback_str->substream_opened) { 567 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val); 568 val &= I2S_TXCR_CSR_MASK; 569 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val); 570 } 571 572 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val); 573 val &= I2S_RXCR_CSR_MASK; 574 575 if (to_ch_num(val) > usable_chs) { 576 dev_err(i2s_tdm->dev, 577 "Capture channels (%d) > usable channels (%d)\n", 578 to_ch_num(val), usable_chs); 579 return -EINVAL; 580 } 581 582 rockchip_i2s_ch_to_io(val, true); 583 } else { 584 struct snd_pcm_str *capture_str = 585 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE]; 586 587 if (capture_str->substream_opened) { 588 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val); 589 val &= I2S_RXCR_CSR_MASK; 590 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val); 591 } 592 593 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val); 594 val &= I2S_TXCR_CSR_MASK; 595 596 if (to_ch_num(val) > usable_chs) { 597 dev_err(i2s_tdm->dev, 598 "Playback channels (%d) > usable channels (%d)\n", 599 to_ch_num(val), usable_chs); 600 return -EINVAL; 601 } 602 } 603 604 val <<= i2s_tdm->soc_data->grf_shift; 605 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16; 606 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val); 607 608 return 0; 609 } 610 611 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream, 612 struct snd_soc_dai *dai, 613 unsigned int div_bclk, 614 unsigned int div_lrck, 615 unsigned int fmt) 616 { 617 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 618 unsigned long flags; 619 620 if (!i2s_tdm->clk_trcm) 621 return 0; 622 623 spin_lock_irqsave(&i2s_tdm->lock, flags); 624 if (i2s_tdm->refcount) 625 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm); 626 627 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 628 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK, 629 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk)); 630 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 631 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK, 632 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck)); 633 634 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 635 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 636 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 637 fmt); 638 else 639 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 640 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 641 fmt); 642 643 if (i2s_tdm->refcount) 644 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm); 645 spin_unlock_irqrestore(&i2s_tdm->lock, flags); 646 647 return 0; 648 } 649 650 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream, 651 struct snd_pcm_hw_params *params, 652 struct snd_soc_dai *dai) 653 { 654 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 655 unsigned int val = 0; 656 unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64; 657 int err; 658 659 if (i2s_tdm->is_master_mode) { 660 struct clk *mclk; 661 662 if (i2s_tdm->clk_trcm == TRCM_TX) { 663 mclk = i2s_tdm->mclk_tx; 664 } else if (i2s_tdm->clk_trcm == TRCM_RX) { 665 mclk = i2s_tdm->mclk_rx; 666 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 667 mclk = i2s_tdm->mclk_tx; 668 } else { 669 mclk = i2s_tdm->mclk_rx; 670 } 671 672 err = clk_set_rate(mclk, DEFAULT_MCLK_FS * params_rate(params)); 673 if (err) 674 return err; 675 676 mclk_rate = clk_get_rate(mclk); 677 bclk_rate = i2s_tdm->frame_width * params_rate(params); 678 if (!bclk_rate) 679 return -EINVAL; 680 681 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); 682 div_lrck = bclk_rate / params_rate(params); 683 } 684 685 switch (params_format(params)) { 686 case SNDRV_PCM_FORMAT_S8: 687 val |= I2S_TXCR_VDW(8); 688 break; 689 case SNDRV_PCM_FORMAT_S16_LE: 690 val |= I2S_TXCR_VDW(16); 691 break; 692 case SNDRV_PCM_FORMAT_S20_3LE: 693 val |= I2S_TXCR_VDW(20); 694 break; 695 case SNDRV_PCM_FORMAT_S24_LE: 696 val |= I2S_TXCR_VDW(24); 697 break; 698 case SNDRV_PCM_FORMAT_S32_LE: 699 val |= I2S_TXCR_VDW(32); 700 break; 701 default: 702 return -EINVAL; 703 } 704 705 switch (params_channels(params)) { 706 case 8: 707 val |= I2S_CHN_8; 708 break; 709 case 6: 710 val |= I2S_CHN_6; 711 break; 712 case 4: 713 val |= I2S_CHN_4; 714 break; 715 case 2: 716 val |= I2S_CHN_2; 717 break; 718 default: 719 return -EINVAL; 720 } 721 722 if (i2s_tdm->clk_trcm) { 723 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val); 724 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 725 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 726 I2S_CLKDIV_TXM_MASK, 727 I2S_CLKDIV_TXM(div_bclk)); 728 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 729 I2S_CKR_TSD_MASK, 730 I2S_CKR_TSD(div_lrck)); 731 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 732 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 733 val); 734 } else { 735 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 736 I2S_CLKDIV_RXM_MASK, 737 I2S_CLKDIV_RXM(div_bclk)); 738 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 739 I2S_CKR_RSD_MASK, 740 I2S_CKR_RSD(div_lrck)); 741 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 742 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 743 val); 744 } 745 746 return rockchip_i2s_io_multiplex(substream, dai); 747 } 748 749 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream, 750 int cmd, struct snd_soc_dai *dai) 751 { 752 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 753 754 switch (cmd) { 755 case SNDRV_PCM_TRIGGER_START: 756 case SNDRV_PCM_TRIGGER_RESUME: 757 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 758 if (i2s_tdm->clk_trcm) 759 rockchip_snd_txrxctrl(substream, dai, 1); 760 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 761 rockchip_snd_rxctrl(i2s_tdm, 1); 762 else 763 rockchip_snd_txctrl(i2s_tdm, 1); 764 break; 765 case SNDRV_PCM_TRIGGER_SUSPEND: 766 case SNDRV_PCM_TRIGGER_STOP: 767 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 768 if (i2s_tdm->clk_trcm) 769 rockchip_snd_txrxctrl(substream, dai, 0); 770 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 771 rockchip_snd_rxctrl(i2s_tdm, 0); 772 else 773 rockchip_snd_txctrl(i2s_tdm, 0); 774 break; 775 default: 776 return -EINVAL; 777 } 778 779 return 0; 780 } 781 782 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai) 783 { 784 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 785 786 if (i2s_tdm->has_capture) 787 snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data); 788 if (i2s_tdm->has_playback) 789 snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data); 790 791 return 0; 792 } 793 794 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai, 795 unsigned int tx_mask, unsigned int rx_mask, 796 int slots, int slot_width) 797 { 798 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 799 unsigned int mask, val; 800 801 i2s_tdm->tdm_mode = true; 802 i2s_tdm->frame_width = slots * slot_width; 803 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK; 804 val = TDM_SLOT_BIT_WIDTH(slot_width) | 805 TDM_FRAME_WIDTH(slots * slot_width); 806 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR, 807 mask, val); 808 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR, 809 mask, val); 810 811 return 0; 812 } 813 814 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai, 815 unsigned int ratio) 816 { 817 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 818 819 if (ratio < 32 || ratio > 512 || ratio % 2 == 1) 820 return -EINVAL; 821 822 i2s_tdm->frame_width = ratio; 823 824 return 0; 825 } 826 827 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = { 828 .probe = rockchip_i2s_tdm_dai_probe, 829 .hw_params = rockchip_i2s_tdm_hw_params, 830 .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio, 831 .set_fmt = rockchip_i2s_tdm_set_fmt, 832 .set_tdm_slot = rockchip_dai_tdm_slot, 833 .trigger = rockchip_i2s_tdm_trigger, 834 }; 835 836 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = { 837 .name = DRV_NAME, 838 .legacy_dai_naming = 1, 839 }; 840 841 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg) 842 { 843 switch (reg) { 844 case I2S_TXCR: 845 case I2S_RXCR: 846 case I2S_CKR: 847 case I2S_DMACR: 848 case I2S_INTCR: 849 case I2S_XFER: 850 case I2S_CLR: 851 case I2S_TXDR: 852 case I2S_TDM_TXCR: 853 case I2S_TDM_RXCR: 854 case I2S_CLKDIV: 855 return true; 856 default: 857 return false; 858 } 859 } 860 861 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg) 862 { 863 switch (reg) { 864 case I2S_TXCR: 865 case I2S_RXCR: 866 case I2S_CKR: 867 case I2S_DMACR: 868 case I2S_INTCR: 869 case I2S_XFER: 870 case I2S_CLR: 871 case I2S_TXDR: 872 case I2S_RXDR: 873 case I2S_TXFIFOLR: 874 case I2S_INTSR: 875 case I2S_RXFIFOLR: 876 case I2S_TDM_TXCR: 877 case I2S_TDM_RXCR: 878 case I2S_CLKDIV: 879 return true; 880 default: 881 return false; 882 } 883 } 884 885 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg) 886 { 887 switch (reg) { 888 case I2S_TXFIFOLR: 889 case I2S_INTSR: 890 case I2S_CLR: 891 case I2S_TXDR: 892 case I2S_RXDR: 893 case I2S_RXFIFOLR: 894 return true; 895 default: 896 return false; 897 } 898 } 899 900 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg) 901 { 902 if (reg == I2S_RXDR) 903 return true; 904 return false; 905 } 906 907 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = { 908 {0x00, 0x7200000f}, 909 {0x04, 0x01c8000f}, 910 {0x08, 0x00001f1f}, 911 {0x10, 0x001f0000}, 912 {0x14, 0x01f00000}, 913 {0x30, 0x00003eff}, 914 {0x34, 0x00003eff}, 915 {0x38, 0x00000707}, 916 }; 917 918 static const struct regmap_config rockchip_i2s_tdm_regmap_config = { 919 .reg_bits = 32, 920 .reg_stride = 4, 921 .val_bits = 32, 922 .max_register = I2S_CLKDIV, 923 .reg_defaults = rockchip_i2s_tdm_reg_defaults, 924 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults), 925 .writeable_reg = rockchip_i2s_tdm_wr_reg, 926 .readable_reg = rockchip_i2s_tdm_rd_reg, 927 .volatile_reg = rockchip_i2s_tdm_volatile_reg, 928 .precious_reg = rockchip_i2s_tdm_precious_reg, 929 .cache_type = REGCACHE_FLAT, 930 }; 931 932 static int common_soc_init(struct device *dev, u32 addr) 933 { 934 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 935 const struct txrx_config *configs = i2s_tdm->soc_data->configs; 936 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm; 937 int i; 938 939 if (trcm == TRCM_TXRX) 940 return 0; 941 942 if (IS_ERR_OR_NULL(i2s_tdm->grf)) { 943 dev_err(i2s_tdm->dev, 944 "no grf present but non-txrx TRCM specified\n"); 945 return -EINVAL; 946 } 947 948 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) { 949 if (addr != configs[i].addr) 950 continue; 951 reg = configs[i].reg; 952 if (trcm == TRCM_TX) 953 val = configs[i].txonly; 954 else 955 val = configs[i].rxonly; 956 957 if (reg) 958 regmap_write(i2s_tdm->grf, reg, val); 959 } 960 961 return 0; 962 } 963 964 static const struct txrx_config px30_txrx_config[] = { 965 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY }, 966 }; 967 968 static const struct txrx_config rk1808_txrx_config[] = { 969 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY }, 970 }; 971 972 static const struct txrx_config rk3308_txrx_config[] = { 973 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY }, 974 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY }, 975 }; 976 977 static const struct txrx_config rk3568_txrx_config[] = { 978 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY }, 979 { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE }, 980 { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE }, 981 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY }, 982 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY }, 983 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE }, 984 }; 985 986 static const struct txrx_config rv1126_txrx_config[] = { 987 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY }, 988 }; 989 990 static struct rk_i2s_soc_data px30_i2s_soc_data = { 991 .softrst_offset = 0x0300, 992 .configs = px30_txrx_config, 993 .config_count = ARRAY_SIZE(px30_txrx_config), 994 .init = common_soc_init, 995 }; 996 997 static struct rk_i2s_soc_data rk1808_i2s_soc_data = { 998 .softrst_offset = 0x0300, 999 .configs = rk1808_txrx_config, 1000 .config_count = ARRAY_SIZE(rk1808_txrx_config), 1001 .init = common_soc_init, 1002 }; 1003 1004 static struct rk_i2s_soc_data rk3308_i2s_soc_data = { 1005 .softrst_offset = 0x0400, 1006 .grf_reg_offset = 0x0308, 1007 .grf_shift = 5, 1008 .configs = rk3308_txrx_config, 1009 .config_count = ARRAY_SIZE(rk3308_txrx_config), 1010 .init = common_soc_init, 1011 }; 1012 1013 static struct rk_i2s_soc_data rk3568_i2s_soc_data = { 1014 .softrst_offset = 0x0400, 1015 .configs = rk3568_txrx_config, 1016 .config_count = ARRAY_SIZE(rk3568_txrx_config), 1017 .init = common_soc_init, 1018 }; 1019 1020 static struct rk_i2s_soc_data rv1126_i2s_soc_data = { 1021 .softrst_offset = 0x0300, 1022 .configs = rv1126_txrx_config, 1023 .config_count = ARRAY_SIZE(rv1126_txrx_config), 1024 .init = common_soc_init, 1025 }; 1026 1027 static const struct of_device_id rockchip_i2s_tdm_match[] = { 1028 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data }, 1029 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data }, 1030 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data }, 1031 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data }, 1032 { .compatible = "rockchip,rk3588-i2s-tdm" }, 1033 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data }, 1034 {}, 1035 }; 1036 1037 static const struct snd_soc_dai_driver i2s_tdm_dai = { 1038 .ops = &rockchip_i2s_tdm_dai_ops, 1039 }; 1040 1041 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm) 1042 { 1043 struct snd_soc_dai_driver *dai; 1044 struct property *dma_names; 1045 const char *dma_name; 1046 u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | 1047 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | 1048 SNDRV_PCM_FMTBIT_S32_LE); 1049 struct device_node *node = i2s_tdm->dev->of_node; 1050 1051 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { 1052 if (!strcmp(dma_name, "tx")) 1053 i2s_tdm->has_playback = true; 1054 if (!strcmp(dma_name, "rx")) 1055 i2s_tdm->has_capture = true; 1056 } 1057 1058 dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai, 1059 sizeof(*dai), GFP_KERNEL); 1060 if (!dai) 1061 return -ENOMEM; 1062 1063 if (i2s_tdm->has_playback) { 1064 dai->playback.stream_name = "Playback"; 1065 dai->playback.channels_min = 2; 1066 dai->playback.channels_max = 8; 1067 dai->playback.rates = SNDRV_PCM_RATE_8000_192000; 1068 dai->playback.formats = formats; 1069 } 1070 1071 if (i2s_tdm->has_capture) { 1072 dai->capture.stream_name = "Capture"; 1073 dai->capture.channels_min = 2; 1074 dai->capture.channels_max = 8; 1075 dai->capture.rates = SNDRV_PCM_RATE_8000_192000; 1076 dai->capture.formats = formats; 1077 } 1078 1079 if (i2s_tdm->clk_trcm != TRCM_TXRX) 1080 dai->symmetric_rate = 1; 1081 1082 i2s_tdm->dai = dai; 1083 1084 return 0; 1085 } 1086 1087 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm, 1088 int num, 1089 bool is_rx_path) 1090 { 1091 unsigned int *i2s_data; 1092 int i, j; 1093 1094 if (is_rx_path) 1095 i2s_data = i2s_tdm->i2s_sdis; 1096 else 1097 i2s_data = i2s_tdm->i2s_sdos; 1098 1099 for (i = 0; i < num; i++) { 1100 if (i2s_data[i] > CH_GRP_MAX - 1) { 1101 dev_err(i2s_tdm->dev, 1102 "%s path i2s_data[%d]: %d is too high, max is: %d\n", 1103 is_rx_path ? "RX" : "TX", 1104 i, i2s_data[i], CH_GRP_MAX); 1105 return -EINVAL; 1106 } 1107 1108 for (j = 0; j < num; j++) { 1109 if (i == j) 1110 continue; 1111 1112 if (i2s_data[i] == i2s_data[j]) { 1113 dev_err(i2s_tdm->dev, 1114 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n", 1115 is_rx_path ? "RX" : "TX", 1116 i, i2s_data[i], 1117 j, i2s_data[j]); 1118 return -EINVAL; 1119 } 1120 } 1121 } 1122 1123 return 0; 1124 } 1125 1126 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1127 int num) 1128 { 1129 int idx; 1130 1131 for (idx = 0; idx < num; idx++) { 1132 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 1133 I2S_TXCR_PATH_MASK(idx), 1134 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx])); 1135 } 1136 } 1137 1138 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1139 int num) 1140 { 1141 int idx; 1142 1143 for (idx = 0; idx < num; idx++) { 1144 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 1145 I2S_RXCR_PATH_MASK(idx), 1146 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx])); 1147 } 1148 } 1149 1150 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1151 int num, bool is_rx_path) 1152 { 1153 if (is_rx_path) 1154 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num); 1155 else 1156 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num); 1157 } 1158 1159 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1160 struct device_node *np, 1161 bool is_rx_path) 1162 { 1163 char *i2s_tx_path_prop = "rockchip,i2s-tx-route"; 1164 char *i2s_rx_path_prop = "rockchip,i2s-rx-route"; 1165 char *i2s_path_prop; 1166 unsigned int *i2s_data; 1167 int num, ret = 0; 1168 1169 if (is_rx_path) { 1170 i2s_path_prop = i2s_rx_path_prop; 1171 i2s_data = i2s_tdm->i2s_sdis; 1172 } else { 1173 i2s_path_prop = i2s_tx_path_prop; 1174 i2s_data = i2s_tdm->i2s_sdos; 1175 } 1176 1177 num = of_count_phandle_with_args(np, i2s_path_prop, NULL); 1178 if (num < 0) { 1179 if (num != -ENOENT) { 1180 dev_err(i2s_tdm->dev, 1181 "Failed to read '%s' num: %d\n", 1182 i2s_path_prop, num); 1183 ret = num; 1184 } 1185 return ret; 1186 } else if (num != CH_GRP_MAX) { 1187 dev_err(i2s_tdm->dev, 1188 "The num: %d should be: %d\n", num, CH_GRP_MAX); 1189 return -EINVAL; 1190 } 1191 1192 ret = of_property_read_u32_array(np, i2s_path_prop, 1193 i2s_data, num); 1194 if (ret < 0) { 1195 dev_err(i2s_tdm->dev, 1196 "Failed to read '%s': %d\n", 1197 i2s_path_prop, ret); 1198 return ret; 1199 } 1200 1201 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path); 1202 if (ret < 0) { 1203 dev_err(i2s_tdm->dev, 1204 "Failed to check i2s data bus: %d\n", ret); 1205 return ret; 1206 } 1207 1208 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path); 1209 1210 return 0; 1211 } 1212 1213 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1214 struct device_node *np) 1215 { 1216 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0); 1217 } 1218 1219 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1220 struct device_node *np) 1221 { 1222 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1); 1223 } 1224 1225 static int rockchip_i2s_tdm_probe(struct platform_device *pdev) 1226 { 1227 struct device_node *node = pdev->dev.of_node; 1228 const struct of_device_id *of_id; 1229 struct rk_i2s_tdm_dev *i2s_tdm; 1230 struct resource *res; 1231 void __iomem *regs; 1232 int ret; 1233 1234 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL); 1235 if (!i2s_tdm) 1236 return -ENOMEM; 1237 1238 i2s_tdm->dev = &pdev->dev; 1239 1240 of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev); 1241 if (!of_id) 1242 return -EINVAL; 1243 1244 spin_lock_init(&i2s_tdm->lock); 1245 i2s_tdm->soc_data = (struct rk_i2s_soc_data *)of_id->data; 1246 1247 i2s_tdm->frame_width = 64; 1248 1249 i2s_tdm->clk_trcm = TRCM_TXRX; 1250 if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only")) 1251 i2s_tdm->clk_trcm = TRCM_TX; 1252 if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) { 1253 if (i2s_tdm->clk_trcm) { 1254 dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n"); 1255 return -EINVAL; 1256 } 1257 i2s_tdm->clk_trcm = TRCM_RX; 1258 } 1259 1260 ret = rockchip_i2s_tdm_init_dai(i2s_tdm); 1261 if (ret) 1262 return ret; 1263 1264 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); 1265 i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1266 "tx-m"); 1267 if (IS_ERR(i2s_tdm->tx_reset)) { 1268 ret = PTR_ERR(i2s_tdm->tx_reset); 1269 return dev_err_probe(i2s_tdm->dev, ret, 1270 "Error in tx-m reset control\n"); 1271 } 1272 1273 i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1274 "rx-m"); 1275 if (IS_ERR(i2s_tdm->rx_reset)) { 1276 ret = PTR_ERR(i2s_tdm->rx_reset); 1277 return dev_err_probe(i2s_tdm->dev, ret, 1278 "Error in rx-m reset control\n"); 1279 } 1280 1281 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk"); 1282 if (IS_ERR(i2s_tdm->hclk)) { 1283 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk), 1284 "Failed to get clock hclk\n"); 1285 } 1286 1287 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx"); 1288 if (IS_ERR(i2s_tdm->mclk_tx)) { 1289 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx), 1290 "Failed to get clock mclk_tx\n"); 1291 } 1292 1293 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx"); 1294 if (IS_ERR(i2s_tdm->mclk_rx)) { 1295 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx), 1296 "Failed to get clock mclk_rx\n"); 1297 } 1298 1299 i2s_tdm->io_multiplex = 1300 of_property_read_bool(node, "rockchip,io-multiplex"); 1301 1302 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1303 if (IS_ERR(regs)) { 1304 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs), 1305 "Failed to get resource IORESOURCE_MEM\n"); 1306 } 1307 1308 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1309 &rockchip_i2s_tdm_regmap_config); 1310 if (IS_ERR(i2s_tdm->regmap)) { 1311 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap), 1312 "Failed to initialise regmap\n"); 1313 } 1314 1315 if (i2s_tdm->has_playback) { 1316 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR; 1317 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1318 i2s_tdm->playback_dma_data.maxburst = 8; 1319 } 1320 1321 if (i2s_tdm->has_capture) { 1322 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR; 1323 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1324 i2s_tdm->capture_dma_data.maxburst = 8; 1325 } 1326 1327 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node); 1328 if (ret < 0) { 1329 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret); 1330 return ret; 1331 } 1332 1333 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node); 1334 if (ret < 0) { 1335 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret); 1336 return ret; 1337 } 1338 1339 dev_set_drvdata(&pdev->dev, i2s_tdm); 1340 1341 ret = clk_prepare_enable(i2s_tdm->hclk); 1342 if (ret) { 1343 return dev_err_probe(i2s_tdm->dev, ret, 1344 "Failed to enable clock hclk\n"); 1345 } 1346 1347 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm); 1348 if (ret) { 1349 ret = dev_err_probe(i2s_tdm->dev, ret, 1350 "Failed to enable one or more mclks\n"); 1351 goto err_disable_hclk; 1352 } 1353 1354 pm_runtime_enable(&pdev->dev); 1355 1356 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 1357 I2S_DMACR_TDL(16)); 1358 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 1359 I2S_DMACR_RDL(16)); 1360 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK, 1361 i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT); 1362 1363 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init) 1364 i2s_tdm->soc_data->init(&pdev->dev, res->start); 1365 1366 ret = devm_snd_soc_register_component(&pdev->dev, 1367 &rockchip_i2s_tdm_component, 1368 i2s_tdm->dai, 1); 1369 1370 if (ret) { 1371 dev_err(&pdev->dev, "Could not register DAI\n"); 1372 goto err_suspend; 1373 } 1374 1375 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1376 if (ret) { 1377 dev_err(&pdev->dev, "Could not register PCM\n"); 1378 goto err_suspend; 1379 } 1380 1381 return 0; 1382 1383 err_suspend: 1384 if (!pm_runtime_status_suspended(&pdev->dev)) 1385 i2s_tdm_runtime_suspend(&pdev->dev); 1386 pm_runtime_disable(&pdev->dev); 1387 1388 err_disable_hclk: 1389 clk_disable_unprepare(i2s_tdm->hclk); 1390 1391 return ret; 1392 } 1393 1394 static int rockchip_i2s_tdm_remove(struct platform_device *pdev) 1395 { 1396 if (!pm_runtime_status_suspended(&pdev->dev)) 1397 i2s_tdm_runtime_suspend(&pdev->dev); 1398 1399 pm_runtime_disable(&pdev->dev); 1400 1401 return 0; 1402 } 1403 1404 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev) 1405 { 1406 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 1407 1408 regcache_mark_dirty(i2s_tdm->regmap); 1409 1410 return 0; 1411 } 1412 1413 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev) 1414 { 1415 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 1416 int ret; 1417 1418 ret = pm_runtime_resume_and_get(dev); 1419 if (ret < 0) 1420 return ret; 1421 ret = regcache_sync(i2s_tdm->regmap); 1422 pm_runtime_put(dev); 1423 1424 return ret; 1425 } 1426 1427 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = { 1428 SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume, 1429 NULL) 1430 SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend, 1431 rockchip_i2s_tdm_resume) 1432 }; 1433 1434 static struct platform_driver rockchip_i2s_tdm_driver = { 1435 .probe = rockchip_i2s_tdm_probe, 1436 .remove = rockchip_i2s_tdm_remove, 1437 .driver = { 1438 .name = DRV_NAME, 1439 .of_match_table = of_match_ptr(rockchip_i2s_tdm_match), 1440 .pm = &rockchip_i2s_tdm_pm_ops, 1441 }, 1442 }; 1443 module_platform_driver(rockchip_i2s_tdm_driver); 1444 1445 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface"); 1446 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>"); 1447 MODULE_LICENSE("GPL v2"); 1448 MODULE_ALIAS("platform:" DRV_NAME); 1449 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match); 1450