1 /* 2 * sound/soc/rockchip/rockchip_i2s.h 3 * 4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver 5 * 6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd. 7 * Author: Jianqun xu <jay.xu@rock-chips.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #ifndef _ROCKCHIP_IIS_H 15 #define _ROCKCHIP_IIS_H 16 17 /* 18 * TXCR 19 * transmit operation control register 20 */ 21 #define I2S_TXCR_RCNT_SHIFT 17 22 #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT) 23 #define I2S_TXCR_CSR_SHIFT 15 24 #define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT) 25 #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT) 26 #define I2S_TXCR_HWT BIT(14) 27 #define I2S_TXCR_SJM_SHIFT 12 28 #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT) 29 #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT) 30 #define I2S_TXCR_FBM_SHIFT 11 31 #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT) 32 #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT) 33 #define I2S_TXCR_IBM_SHIFT 9 34 #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT) 35 #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT) 36 #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT) 37 #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT) 38 #define I2S_TXCR_PBM_SHIFT 7 39 #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT) 40 #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT) 41 #define I2S_TXCR_TFS_SHIFT 5 42 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) 43 #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) 44 #define I2S_TXCR_VDW_SHIFT 0 45 #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) 46 #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) 47 48 /* 49 * RXCR 50 * receive operation control register 51 */ 52 #define I2S_RXCR_CSR_SHIFT 15 53 #define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT) 54 #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT) 55 #define I2S_RXCR_HWT BIT(14) 56 #define I2S_RXCR_SJM_SHIFT 12 57 #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT) 58 #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT) 59 #define I2S_RXCR_FBM_SHIFT 11 60 #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT) 61 #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT) 62 #define I2S_RXCR_IBM_SHIFT 9 63 #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT) 64 #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT) 65 #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT) 66 #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT) 67 #define I2S_RXCR_PBM_SHIFT 7 68 #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT) 69 #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT) 70 #define I2S_RXCR_TFS_SHIFT 5 71 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) 72 #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) 73 #define I2S_RXCR_VDW_SHIFT 0 74 #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) 75 #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) 76 77 /* 78 * CKR 79 * clock generation register 80 */ 81 #define I2S_CKR_TRCM_SHIFT 28 82 #define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHIFT) 83 #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT) 84 #define I2S_CKR_TRCM_TXSHARE (1 << I2S_CKR_TRCM_SHIFT) 85 #define I2S_CKR_TRCM_RXSHARE (2 << I2S_CKR_TRCM_SHIFT) 86 #define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT) 87 #define I2S_CKR_MSS_SHIFT 27 88 #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) 89 #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) 90 #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT) 91 #define I2S_CKR_CKP_SHIFT 26 92 #define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT) 93 #define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT) 94 #define I2S_CKR_RLP_SHIFT 25 95 #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) 96 #define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT) 97 #define I2S_CKR_TLP_SHIFT 24 98 #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT) 99 #define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT) 100 #define I2S_CKR_MDIV_SHIFT 16 101 #define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT) 102 #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT) 103 #define I2S_CKR_RSD_SHIFT 8 104 #define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT) 105 #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT) 106 #define I2S_CKR_TSD_SHIFT 0 107 #define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT) 108 #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT) 109 110 /* 111 * FIFOLR 112 * FIFO level register 113 */ 114 #define I2S_FIFOLR_RFL_SHIFT 24 115 #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT) 116 #define I2S_FIFOLR_TFL3_SHIFT 18 117 #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT) 118 #define I2S_FIFOLR_TFL2_SHIFT 12 119 #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT) 120 #define I2S_FIFOLR_TFL1_SHIFT 6 121 #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT) 122 #define I2S_FIFOLR_TFL0_SHIFT 0 123 #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT) 124 125 /* 126 * DMACR 127 * DMA control register 128 */ 129 #define I2S_DMACR_RDE_SHIFT 24 130 #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT) 131 #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT) 132 #define I2S_DMACR_RDL_SHIFT 16 133 #define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT) 134 #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT) 135 #define I2S_DMACR_TDE_SHIFT 8 136 #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT) 137 #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT) 138 #define I2S_DMACR_TDL_SHIFT 0 139 #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT) 140 #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT) 141 142 /* 143 * INTCR 144 * interrupt control register 145 */ 146 #define I2S_INTCR_RFT_SHIFT 20 147 #define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT) 148 #define I2S_INTCR_RXOIC BIT(18) 149 #define I2S_INTCR_RXOIE_SHIFT 17 150 #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT) 151 #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT) 152 #define I2S_INTCR_RXFIE_SHIFT 16 153 #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT) 154 #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT) 155 #define I2S_INTCR_TFT_SHIFT 4 156 #define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT) 157 #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT) 158 #define I2S_INTCR_TXUIC BIT(2) 159 #define I2S_INTCR_TXUIE_SHIFT 1 160 #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT) 161 #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT) 162 163 /* 164 * INTSR 165 * interrupt status register 166 */ 167 #define I2S_INTSR_TXEIE_SHIFT 0 168 #define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT) 169 #define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT) 170 #define I2S_INTSR_RXOI_SHIFT 17 171 #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT) 172 #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT) 173 #define I2S_INTSR_RXFI_SHIFT 16 174 #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT) 175 #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT) 176 #define I2S_INTSR_TXUI_SHIFT 1 177 #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT) 178 #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT) 179 #define I2S_INTSR_TXEI_SHIFT 0 180 #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT) 181 #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT) 182 183 /* 184 * XFER 185 * Transfer start register 186 */ 187 #define I2S_XFER_RXS_SHIFT 1 188 #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT) 189 #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT) 190 #define I2S_XFER_TXS_SHIFT 0 191 #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT) 192 #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT) 193 194 /* 195 * CLR 196 * clear SCLK domain logic register 197 */ 198 #define I2S_CLR_RXC BIT(1) 199 #define I2S_CLR_TXC BIT(0) 200 201 /* 202 * TXDR 203 * Transimt FIFO data register, write only. 204 */ 205 #define I2S_TXDR_MASK (0xff) 206 207 /* 208 * RXDR 209 * Receive FIFO data register, write only. 210 */ 211 #define I2S_RXDR_MASK (0xff) 212 213 /* Clock divider id */ 214 enum { 215 ROCKCHIP_DIV_MCLK = 0, 216 ROCKCHIP_DIV_BCLK, 217 }; 218 219 /* channel select */ 220 #define I2S_CSR_SHIFT 15 221 #define I2S_CHN_2 (0 << I2S_CSR_SHIFT) 222 #define I2S_CHN_4 (1 << I2S_CSR_SHIFT) 223 #define I2S_CHN_6 (2 << I2S_CSR_SHIFT) 224 #define I2S_CHN_8 (3 << I2S_CSR_SHIFT) 225 226 /* I2S REGS */ 227 #define I2S_TXCR (0x0000) 228 #define I2S_RXCR (0x0004) 229 #define I2S_CKR (0x0008) 230 #define I2S_FIFOLR (0x000c) 231 #define I2S_DMACR (0x0010) 232 #define I2S_INTCR (0x0014) 233 #define I2S_INTSR (0x0018) 234 #define I2S_XFER (0x001c) 235 #define I2S_CLR (0x0020) 236 #define I2S_TXDR (0x0024) 237 #define I2S_RXDR (0x0028) 238 239 #endif /* _ROCKCHIP_IIS_H */ 240