1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2018, Linaro Limited 4 5 #include <linux/slab.h> 6 #include <linux/kernel.h> 7 #include <linux/uaccess.h> 8 #include <linux/wait.h> 9 #include <linux/jiffies.h> 10 #include <linux/sched.h> 11 #include <linux/module.h> 12 #include <linux/kref.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/spinlock.h> 16 #include <linux/delay.h> 17 #include <linux/soc/qcom/apr.h> 18 #include <sound/soc.h> 19 #include <sound/soc-dai.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include "q6dsp-errno.h" 23 #include "q6core.h" 24 #include "q6afe.h" 25 26 /* AFE CMDs */ 27 #define AFE_PORT_CMD_DEVICE_START 0x000100E5 28 #define AFE_PORT_CMD_DEVICE_STOP 0x000100E6 29 #define AFE_PORT_CMD_SET_PARAM_V2 0x000100EF 30 #define AFE_SVC_CMD_SET_PARAM 0x000100f3 31 #define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106 32 #define AFE_PARAM_ID_HDMI_CONFIG 0x00010210 33 #define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C 34 #define AFE_MODULE_TDM 0x0001028A 35 36 #define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235 37 38 #define AFE_PARAM_ID_LPAIF_CLK_CONFIG 0x00010238 39 #define AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG 0x00010239 40 41 #define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212 42 #define AFE_PARAM_ID_I2S_CONFIG 0x0001020D 43 #define AFE_PARAM_ID_TDM_CONFIG 0x0001029D 44 #define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297 45 #define AFE_PARAM_ID_CODEC_DMA_CONFIG 0x000102B8 46 #define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f4 47 #define AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f5 48 #define AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST 0x000100f6 49 50 /* I2S config specific */ 51 #define AFE_API_VERSION_I2S_CONFIG 0x1 52 #define AFE_PORT_I2S_SD0 0x1 53 #define AFE_PORT_I2S_SD1 0x2 54 #define AFE_PORT_I2S_SD2 0x3 55 #define AFE_PORT_I2S_SD3 0x4 56 #define AFE_PORT_I2S_SD0_MASK BIT(0x0) 57 #define AFE_PORT_I2S_SD1_MASK BIT(0x1) 58 #define AFE_PORT_I2S_SD2_MASK BIT(0x2) 59 #define AFE_PORT_I2S_SD3_MASK BIT(0x3) 60 #define AFE_PORT_I2S_SD0_1_MASK GENMASK(1, 0) 61 #define AFE_PORT_I2S_SD2_3_MASK GENMASK(3, 2) 62 #define AFE_PORT_I2S_SD0_1_2_MASK GENMASK(2, 0) 63 #define AFE_PORT_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 64 #define AFE_PORT_I2S_QUAD01 0x5 65 #define AFE_PORT_I2S_QUAD23 0x6 66 #define AFE_PORT_I2S_6CHS 0x7 67 #define AFE_PORT_I2S_8CHS 0x8 68 #define AFE_PORT_I2S_MONO 0x0 69 #define AFE_PORT_I2S_STEREO 0x1 70 #define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL 0x0 71 #define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL 0x1 72 #define AFE_LINEAR_PCM_DATA 0x0 73 74 75 /* Port IDs */ 76 #define AFE_API_VERSION_HDMI_CONFIG 0x1 77 #define AFE_PORT_ID_MULTICHAN_HDMI_RX 0x100E 78 #define AFE_PORT_ID_HDMI_OVER_DP_RX 0x6020 79 80 #define AFE_API_VERSION_SLIMBUS_CONFIG 0x1 81 /* Clock set API version */ 82 #define AFE_API_VERSION_CLOCK_SET 1 83 #define Q6AFE_LPASS_CLK_CONFIG_API_VERSION 0x1 84 #define AFE_MODULE_CLOCK_SET 0x0001028F 85 #define AFE_PARAM_ID_CLOCK_SET 0x00010290 86 87 /* SLIMbus Rx port on channel 0. */ 88 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX 0x4000 89 /* SLIMbus Tx port on channel 0. */ 90 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX 0x4001 91 /* SLIMbus Rx port on channel 1. */ 92 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX 0x4002 93 /* SLIMbus Tx port on channel 1. */ 94 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX 0x4003 95 /* SLIMbus Rx port on channel 2. */ 96 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX 0x4004 97 /* SLIMbus Tx port on channel 2. */ 98 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX 0x4005 99 /* SLIMbus Rx port on channel 3. */ 100 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX 0x4006 101 /* SLIMbus Tx port on channel 3. */ 102 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX 0x4007 103 /* SLIMbus Rx port on channel 4. */ 104 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX 0x4008 105 /* SLIMbus Tx port on channel 4. */ 106 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX 0x4009 107 /* SLIMbus Rx port on channel 5. */ 108 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX 0x400a 109 /* SLIMbus Tx port on channel 5. */ 110 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX 0x400b 111 /* SLIMbus Rx port on channel 6. */ 112 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX 0x400c 113 /* SLIMbus Tx port on channel 6. */ 114 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX 0x400d 115 #define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000 116 #define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001 117 #define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002 118 #define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003 119 #define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004 120 #define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005 121 #define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006 122 #define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 123 #define AFE_PORT_ID_QUINARY_MI2S_RX 0x1016 124 #define AFE_PORT_ID_QUINARY_MI2S_TX 0x1017 125 126 /* Start of the range of port IDs for TDM devices. */ 127 #define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000 128 129 /* End of the range of port IDs for TDM devices. */ 130 #define AFE_PORT_ID_TDM_PORT_RANGE_END \ 131 (AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1) 132 133 /* Size of the range of port IDs for TDM ports. */ 134 #define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \ 135 (AFE_PORT_ID_TDM_PORT_RANGE_END - \ 136 AFE_PORT_ID_TDM_PORT_RANGE_START+1) 137 138 #define AFE_PORT_ID_PRIMARY_TDM_RX \ 139 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00) 140 #define AFE_PORT_ID_PRIMARY_TDM_RX_1 \ 141 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x02) 142 #define AFE_PORT_ID_PRIMARY_TDM_RX_2 \ 143 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x04) 144 #define AFE_PORT_ID_PRIMARY_TDM_RX_3 \ 145 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x06) 146 #define AFE_PORT_ID_PRIMARY_TDM_RX_4 \ 147 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x08) 148 #define AFE_PORT_ID_PRIMARY_TDM_RX_5 \ 149 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A) 150 #define AFE_PORT_ID_PRIMARY_TDM_RX_6 \ 151 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C) 152 #define AFE_PORT_ID_PRIMARY_TDM_RX_7 \ 153 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E) 154 155 #define AFE_PORT_ID_PRIMARY_TDM_TX \ 156 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01) 157 #define AFE_PORT_ID_PRIMARY_TDM_TX_1 \ 158 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x02) 159 #define AFE_PORT_ID_PRIMARY_TDM_TX_2 \ 160 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x04) 161 #define AFE_PORT_ID_PRIMARY_TDM_TX_3 \ 162 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x06) 163 #define AFE_PORT_ID_PRIMARY_TDM_TX_4 \ 164 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x08) 165 #define AFE_PORT_ID_PRIMARY_TDM_TX_5 \ 166 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A) 167 #define AFE_PORT_ID_PRIMARY_TDM_TX_6 \ 168 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C) 169 #define AFE_PORT_ID_PRIMARY_TDM_TX_7 \ 170 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E) 171 172 #define AFE_PORT_ID_SECONDARY_TDM_RX \ 173 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10) 174 #define AFE_PORT_ID_SECONDARY_TDM_RX_1 \ 175 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x02) 176 #define AFE_PORT_ID_SECONDARY_TDM_RX_2 \ 177 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x04) 178 #define AFE_PORT_ID_SECONDARY_TDM_RX_3 \ 179 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x06) 180 #define AFE_PORT_ID_SECONDARY_TDM_RX_4 \ 181 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x08) 182 #define AFE_PORT_ID_SECONDARY_TDM_RX_5 \ 183 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A) 184 #define AFE_PORT_ID_SECONDARY_TDM_RX_6 \ 185 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C) 186 #define AFE_PORT_ID_SECONDARY_TDM_RX_7 \ 187 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E) 188 189 #define AFE_PORT_ID_SECONDARY_TDM_TX \ 190 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11) 191 #define AFE_PORT_ID_SECONDARY_TDM_TX_1 \ 192 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x02) 193 #define AFE_PORT_ID_SECONDARY_TDM_TX_2 \ 194 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x04) 195 #define AFE_PORT_ID_SECONDARY_TDM_TX_3 \ 196 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x06) 197 #define AFE_PORT_ID_SECONDARY_TDM_TX_4 \ 198 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x08) 199 #define AFE_PORT_ID_SECONDARY_TDM_TX_5 \ 200 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A) 201 #define AFE_PORT_ID_SECONDARY_TDM_TX_6 \ 202 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C) 203 #define AFE_PORT_ID_SECONDARY_TDM_TX_7 \ 204 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E) 205 206 #define AFE_PORT_ID_TERTIARY_TDM_RX \ 207 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20) 208 #define AFE_PORT_ID_TERTIARY_TDM_RX_1 \ 209 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x02) 210 #define AFE_PORT_ID_TERTIARY_TDM_RX_2 \ 211 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x04) 212 #define AFE_PORT_ID_TERTIARY_TDM_RX_3 \ 213 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x06) 214 #define AFE_PORT_ID_TERTIARY_TDM_RX_4 \ 215 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x08) 216 #define AFE_PORT_ID_TERTIARY_TDM_RX_5 \ 217 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A) 218 #define AFE_PORT_ID_TERTIARY_TDM_RX_6 \ 219 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C) 220 #define AFE_PORT_ID_TERTIARY_TDM_RX_7 \ 221 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E) 222 223 #define AFE_PORT_ID_TERTIARY_TDM_TX \ 224 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21) 225 #define AFE_PORT_ID_TERTIARY_TDM_TX_1 \ 226 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x02) 227 #define AFE_PORT_ID_TERTIARY_TDM_TX_2 \ 228 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x04) 229 #define AFE_PORT_ID_TERTIARY_TDM_TX_3 \ 230 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x06) 231 #define AFE_PORT_ID_TERTIARY_TDM_TX_4 \ 232 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x08) 233 #define AFE_PORT_ID_TERTIARY_TDM_TX_5 \ 234 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A) 235 #define AFE_PORT_ID_TERTIARY_TDM_TX_6 \ 236 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C) 237 #define AFE_PORT_ID_TERTIARY_TDM_TX_7 \ 238 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E) 239 240 #define AFE_PORT_ID_QUATERNARY_TDM_RX \ 241 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30) 242 #define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \ 243 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02) 244 #define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \ 245 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04) 246 #define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \ 247 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06) 248 #define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \ 249 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08) 250 #define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \ 251 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A) 252 #define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \ 253 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C) 254 #define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \ 255 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E) 256 257 #define AFE_PORT_ID_QUATERNARY_TDM_TX \ 258 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31) 259 #define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \ 260 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02) 261 #define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \ 262 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04) 263 #define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \ 264 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06) 265 #define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \ 266 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08) 267 #define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \ 268 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A) 269 #define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \ 270 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C) 271 #define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \ 272 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E) 273 274 #define AFE_PORT_ID_QUINARY_TDM_RX \ 275 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40) 276 #define AFE_PORT_ID_QUINARY_TDM_RX_1 \ 277 (AFE_PORT_ID_QUINARY_TDM_RX + 0x02) 278 #define AFE_PORT_ID_QUINARY_TDM_RX_2 \ 279 (AFE_PORT_ID_QUINARY_TDM_RX + 0x04) 280 #define AFE_PORT_ID_QUINARY_TDM_RX_3 \ 281 (AFE_PORT_ID_QUINARY_TDM_RX + 0x06) 282 #define AFE_PORT_ID_QUINARY_TDM_RX_4 \ 283 (AFE_PORT_ID_QUINARY_TDM_RX + 0x08) 284 #define AFE_PORT_ID_QUINARY_TDM_RX_5 \ 285 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0A) 286 #define AFE_PORT_ID_QUINARY_TDM_RX_6 \ 287 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0C) 288 #define AFE_PORT_ID_QUINARY_TDM_RX_7 \ 289 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0E) 290 291 #define AFE_PORT_ID_QUINARY_TDM_TX \ 292 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41) 293 #define AFE_PORT_ID_QUINARY_TDM_TX_1 \ 294 (AFE_PORT_ID_QUINARY_TDM_TX + 0x02) 295 #define AFE_PORT_ID_QUINARY_TDM_TX_2 \ 296 (AFE_PORT_ID_QUINARY_TDM_TX + 0x04) 297 #define AFE_PORT_ID_QUINARY_TDM_TX_3 \ 298 (AFE_PORT_ID_QUINARY_TDM_TX + 0x06) 299 #define AFE_PORT_ID_QUINARY_TDM_TX_4 \ 300 (AFE_PORT_ID_QUINARY_TDM_TX + 0x08) 301 #define AFE_PORT_ID_QUINARY_TDM_TX_5 \ 302 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0A) 303 #define AFE_PORT_ID_QUINARY_TDM_TX_6 \ 304 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0C) 305 #define AFE_PORT_ID_QUINARY_TDM_TX_7 \ 306 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0E) 307 308 /* AFE WSA Codec DMA Rx port 0 */ 309 #define AFE_PORT_ID_WSA_CODEC_DMA_RX_0 0xB000 310 /* AFE WSA Codec DMA Tx port 0 */ 311 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_0 0xB001 312 /* AFE WSA Codec DMA Rx port 1 */ 313 #define AFE_PORT_ID_WSA_CODEC_DMA_RX_1 0xB002 314 /* AFE WSA Codec DMA Tx port 1 */ 315 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_1 0xB003 316 /* AFE WSA Codec DMA Tx port 2 */ 317 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_2 0xB005 318 /* AFE VA Codec DMA Tx port 0 */ 319 #define AFE_PORT_ID_VA_CODEC_DMA_TX_0 0xB021 320 /* AFE VA Codec DMA Tx port 1 */ 321 #define AFE_PORT_ID_VA_CODEC_DMA_TX_1 0xB023 322 /* AFE VA Codec DMA Tx port 2 */ 323 #define AFE_PORT_ID_VA_CODEC_DMA_TX_2 0xB025 324 /* AFE Rx Codec DMA Rx port 0 */ 325 #define AFE_PORT_ID_RX_CODEC_DMA_RX_0 0xB030 326 /* AFE Tx Codec DMA Tx port 0 */ 327 #define AFE_PORT_ID_TX_CODEC_DMA_TX_0 0xB031 328 /* AFE Rx Codec DMA Rx port 1 */ 329 #define AFE_PORT_ID_RX_CODEC_DMA_RX_1 0xB032 330 /* AFE Tx Codec DMA Tx port 1 */ 331 #define AFE_PORT_ID_TX_CODEC_DMA_TX_1 0xB033 332 /* AFE Rx Codec DMA Rx port 2 */ 333 #define AFE_PORT_ID_RX_CODEC_DMA_RX_2 0xB034 334 /* AFE Tx Codec DMA Tx port 2 */ 335 #define AFE_PORT_ID_TX_CODEC_DMA_TX_2 0xB035 336 /* AFE Rx Codec DMA Rx port 3 */ 337 #define AFE_PORT_ID_RX_CODEC_DMA_RX_3 0xB036 338 /* AFE Tx Codec DMA Tx port 3 */ 339 #define AFE_PORT_ID_TX_CODEC_DMA_TX_3 0xB037 340 /* AFE Rx Codec DMA Rx port 4 */ 341 #define AFE_PORT_ID_RX_CODEC_DMA_RX_4 0xB038 342 /* AFE Tx Codec DMA Tx port 4 */ 343 #define AFE_PORT_ID_TX_CODEC_DMA_TX_4 0xB039 344 /* AFE Rx Codec DMA Rx port 5 */ 345 #define AFE_PORT_ID_RX_CODEC_DMA_RX_5 0xB03A 346 /* AFE Tx Codec DMA Tx port 5 */ 347 #define AFE_PORT_ID_TX_CODEC_DMA_TX_5 0xB03B 348 /* AFE Rx Codec DMA Rx port 6 */ 349 #define AFE_PORT_ID_RX_CODEC_DMA_RX_6 0xB03C 350 /* AFE Rx Codec DMA Rx port 7 */ 351 #define AFE_PORT_ID_RX_CODEC_DMA_RX_7 0xB03E 352 353 #define Q6AFE_LPASS_MODE_CLK1_VALID 1 354 #define Q6AFE_LPASS_MODE_CLK2_VALID 2 355 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 356 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 357 #define AFE_API_VERSION_TDM_CONFIG 1 358 #define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1 359 #define AFE_API_VERSION_CODEC_DMA_CONFIG 1 360 361 #define TIMEOUT_MS 1000 362 #define AFE_CMD_RESP_AVAIL 0 363 #define AFE_CMD_RESP_NONE 1 364 #define AFE_CLK_TOKEN 1024 365 366 struct q6afe { 367 struct apr_device *apr; 368 struct device *dev; 369 struct q6core_svc_api_info ainfo; 370 struct mutex lock; 371 struct aprv2_ibasic_rsp_result_t result; 372 wait_queue_head_t wait; 373 struct list_head port_list; 374 spinlock_t port_list_lock; 375 }; 376 377 struct afe_port_cmd_device_start { 378 u16 port_id; 379 u16 reserved; 380 } __packed; 381 382 struct afe_port_cmd_device_stop { 383 u16 port_id; 384 u16 reserved; 385 /* Reserved for 32-bit alignment. This field must be set to 0.*/ 386 } __packed; 387 388 struct afe_port_param_data_v2 { 389 u32 module_id; 390 u32 param_id; 391 u16 param_size; 392 u16 reserved; 393 } __packed; 394 395 struct afe_svc_cmd_set_param { 396 uint32_t payload_size; 397 uint32_t payload_address_lsw; 398 uint32_t payload_address_msw; 399 uint32_t mem_map_handle; 400 } __packed; 401 402 struct afe_port_cmd_set_param_v2 { 403 u16 port_id; 404 u16 payload_size; 405 u32 payload_address_lsw; 406 u32 payload_address_msw; 407 u32 mem_map_handle; 408 } __packed; 409 410 struct afe_param_id_hdmi_multi_chan_audio_cfg { 411 u32 hdmi_cfg_minor_version; 412 u16 datatype; 413 u16 channel_allocation; 414 u32 sample_rate; 415 u16 bit_width; 416 u16 reserved; 417 } __packed; 418 419 struct afe_param_id_slimbus_cfg { 420 u32 sb_cfg_minor_version; 421 /* Minor version used for tracking the version of the SLIMBUS 422 * configuration interface. 423 * Supported values: #AFE_API_VERSION_SLIMBUS_CONFIG 424 */ 425 426 u16 slimbus_dev_id; 427 /* SLIMbus hardware device ID, which is required to handle 428 * multiple SLIMbus hardware blocks. 429 * Supported values: - #AFE_SLIMBUS_DEVICE_1 - #AFE_SLIMBUS_DEVICE_2 430 */ 431 u16 bit_width; 432 /* Bit width of the sample. 433 * Supported values: 16, 24 434 */ 435 u16 data_format; 436 /* Data format supported by the SLIMbus hardware. The default is 437 * 0 (#AFE_SB_DATA_FORMAT_NOT_INDICATED), which indicates the 438 * hardware does not perform any format conversions before the data 439 * transfer. 440 */ 441 u16 num_channels; 442 /* Number of channels. 443 * Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT 444 */ 445 u8 shared_ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 446 /* Mapping of shared channel IDs (128 to 255) to which the 447 * master port is to be connected. 448 * Shared_channel_mapping[i] represents the shared channel assigned 449 * for audio channel i in multichannel audio data. 450 */ 451 u32 sample_rate; 452 /* Sampling rate of the port. 453 * Supported values: 454 * - #AFE_PORT_SAMPLE_RATE_8K 455 * - #AFE_PORT_SAMPLE_RATE_16K 456 * - #AFE_PORT_SAMPLE_RATE_48K 457 * - #AFE_PORT_SAMPLE_RATE_96K 458 * - #AFE_PORT_SAMPLE_RATE_192K 459 */ 460 } __packed; 461 462 struct afe_clk_cfg { 463 u32 i2s_cfg_minor_version; 464 u32 clk_val1; 465 u32 clk_val2; 466 u16 clk_src; 467 u16 clk_root; 468 u16 clk_set_mode; 469 u16 reserved; 470 } __packed; 471 472 struct afe_digital_clk_cfg { 473 u32 i2s_cfg_minor_version; 474 u32 clk_val; 475 u16 clk_root; 476 u16 reserved; 477 } __packed; 478 479 struct afe_param_id_i2s_cfg { 480 u32 i2s_cfg_minor_version; 481 u16 bit_width; 482 u16 channel_mode; 483 u16 mono_stereo; 484 u16 ws_src; 485 u32 sample_rate; 486 u16 data_format; 487 u16 reserved; 488 } __packed; 489 490 struct afe_param_id_tdm_cfg { 491 u32 tdm_cfg_minor_version; 492 u32 num_channels; 493 u32 sample_rate; 494 u32 bit_width; 495 u16 data_format; 496 u16 sync_mode; 497 u16 sync_src; 498 u16 nslots_per_frame; 499 u16 ctrl_data_out_enable; 500 u16 ctrl_invert_sync_pulse; 501 u16 ctrl_sync_data_delay; 502 u16 slot_width; 503 u32 slot_mask; 504 } __packed; 505 506 struct afe_param_id_cdc_dma_cfg { 507 u32 cdc_dma_cfg_minor_version; 508 u32 sample_rate; 509 u16 bit_width; 510 u16 data_format; 511 u16 num_channels; 512 u16 active_channels_mask; 513 } __packed; 514 515 union afe_port_config { 516 struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch; 517 struct afe_param_id_slimbus_cfg slim_cfg; 518 struct afe_param_id_i2s_cfg i2s_cfg; 519 struct afe_param_id_tdm_cfg tdm_cfg; 520 struct afe_param_id_cdc_dma_cfg dma_cfg; 521 } __packed; 522 523 524 struct afe_clk_set { 525 uint32_t clk_set_minor_version; 526 uint32_t clk_id; 527 uint32_t clk_freq_in_hz; 528 uint16_t clk_attri; 529 uint16_t clk_root; 530 uint32_t enable; 531 }; 532 533 struct afe_param_id_slot_mapping_cfg { 534 u32 minor_version; 535 u16 num_channels; 536 u16 bitwidth; 537 u32 data_align_type; 538 u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 539 } __packed; 540 541 struct q6afe_port { 542 wait_queue_head_t wait; 543 union afe_port_config port_cfg; 544 struct afe_param_id_slot_mapping_cfg *scfg; 545 struct aprv2_ibasic_rsp_result_t result; 546 int token; 547 int id; 548 int cfg_type; 549 struct q6afe *afe; 550 struct kref refcount; 551 struct list_head node; 552 }; 553 554 struct afe_cmd_remote_lpass_core_hw_vote_request { 555 uint32_t hw_block_id; 556 char client_name[8]; 557 } __packed; 558 559 struct afe_cmd_remote_lpass_core_hw_devote_request { 560 uint32_t hw_block_id; 561 uint32_t client_handle; 562 } __packed; 563 564 565 566 struct afe_port_map { 567 int port_id; 568 int token; 569 int is_rx; 570 int is_dig_pcm; 571 }; 572 573 /* 574 * Mapping between Virtual Port IDs to DSP AFE Port ID 575 * On B Family SoCs DSP Port IDs are consistent across multiple SoCs 576 * on A Family SoCs DSP port IDs are same as virtual Port IDs. 577 */ 578 579 static struct afe_port_map port_maps[AFE_PORT_MAX] = { 580 [HDMI_RX] = { AFE_PORT_ID_MULTICHAN_HDMI_RX, HDMI_RX, 1, 1}, 581 [SLIMBUS_0_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX, 582 SLIMBUS_0_RX, 1, 1}, 583 [SLIMBUS_1_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX, 584 SLIMBUS_1_RX, 1, 1}, 585 [SLIMBUS_2_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX, 586 SLIMBUS_2_RX, 1, 1}, 587 [SLIMBUS_3_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX, 588 SLIMBUS_3_RX, 1, 1}, 589 [SLIMBUS_4_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX, 590 SLIMBUS_4_RX, 1, 1}, 591 [SLIMBUS_5_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX, 592 SLIMBUS_5_RX, 1, 1}, 593 [SLIMBUS_6_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX, 594 SLIMBUS_6_RX, 1, 1}, 595 [SLIMBUS_0_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX, 596 SLIMBUS_0_TX, 0, 1}, 597 [SLIMBUS_1_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX, 598 SLIMBUS_1_TX, 0, 1}, 599 [SLIMBUS_2_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX, 600 SLIMBUS_2_TX, 0, 1}, 601 [SLIMBUS_3_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX, 602 SLIMBUS_3_TX, 0, 1}, 603 [SLIMBUS_4_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX, 604 SLIMBUS_4_TX, 0, 1}, 605 [SLIMBUS_5_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX, 606 SLIMBUS_5_TX, 0, 1}, 607 [SLIMBUS_6_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX, 608 SLIMBUS_6_TX, 0, 1}, 609 [PRIMARY_MI2S_RX] = { AFE_PORT_ID_PRIMARY_MI2S_RX, 610 PRIMARY_MI2S_RX, 1, 1}, 611 [PRIMARY_MI2S_TX] = { AFE_PORT_ID_PRIMARY_MI2S_TX, 612 PRIMARY_MI2S_RX, 0, 1}, 613 [SECONDARY_MI2S_RX] = { AFE_PORT_ID_SECONDARY_MI2S_RX, 614 SECONDARY_MI2S_RX, 1, 1}, 615 [SECONDARY_MI2S_TX] = { AFE_PORT_ID_SECONDARY_MI2S_TX, 616 SECONDARY_MI2S_TX, 0, 1}, 617 [TERTIARY_MI2S_RX] = { AFE_PORT_ID_TERTIARY_MI2S_RX, 618 TERTIARY_MI2S_RX, 1, 1}, 619 [TERTIARY_MI2S_TX] = { AFE_PORT_ID_TERTIARY_MI2S_TX, 620 TERTIARY_MI2S_TX, 0, 1}, 621 [QUATERNARY_MI2S_RX] = { AFE_PORT_ID_QUATERNARY_MI2S_RX, 622 QUATERNARY_MI2S_RX, 1, 1}, 623 [QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX, 624 QUATERNARY_MI2S_TX, 0, 1}, 625 [QUINARY_MI2S_RX] = { AFE_PORT_ID_QUINARY_MI2S_RX, 626 QUINARY_MI2S_RX, 1, 1}, 627 [QUINARY_MI2S_TX] = { AFE_PORT_ID_QUINARY_MI2S_TX, 628 QUINARY_MI2S_TX, 0, 1}, 629 [PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX, 630 PRIMARY_TDM_RX_0, 1, 1}, 631 [PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX, 632 PRIMARY_TDM_TX_0, 0, 1}, 633 [PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1, 634 PRIMARY_TDM_RX_1, 1, 1}, 635 [PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1, 636 PRIMARY_TDM_TX_1, 0, 1}, 637 [PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2, 638 PRIMARY_TDM_RX_2, 1, 1}, 639 [PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2, 640 PRIMARY_TDM_TX_2, 0, 1}, 641 [PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3, 642 PRIMARY_TDM_RX_3, 1, 1}, 643 [PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3, 644 PRIMARY_TDM_TX_3, 0, 1}, 645 [PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4, 646 PRIMARY_TDM_RX_4, 1, 1}, 647 [PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4, 648 PRIMARY_TDM_TX_4, 0, 1}, 649 [PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5, 650 PRIMARY_TDM_RX_5, 1, 1}, 651 [PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5, 652 PRIMARY_TDM_TX_5, 0, 1}, 653 [PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6, 654 PRIMARY_TDM_RX_6, 1, 1}, 655 [PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6, 656 PRIMARY_TDM_TX_6, 0, 1}, 657 [PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7, 658 PRIMARY_TDM_RX_7, 1, 1}, 659 [PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7, 660 PRIMARY_TDM_TX_7, 0, 1}, 661 [SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX, 662 SECONDARY_TDM_RX_0, 1, 1}, 663 [SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX, 664 SECONDARY_TDM_TX_0, 0, 1}, 665 [SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1, 666 SECONDARY_TDM_RX_1, 1, 1}, 667 [SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1, 668 SECONDARY_TDM_TX_1, 0, 1}, 669 [SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2, 670 SECONDARY_TDM_RX_2, 1, 1}, 671 [SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2, 672 SECONDARY_TDM_TX_2, 0, 1}, 673 [SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3, 674 SECONDARY_TDM_RX_3, 1, 1}, 675 [SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3, 676 SECONDARY_TDM_TX_3, 0, 1}, 677 [SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4, 678 SECONDARY_TDM_RX_4, 1, 1}, 679 [SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4, 680 SECONDARY_TDM_TX_4, 0, 1}, 681 [SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5, 682 SECONDARY_TDM_RX_5, 1, 1}, 683 [SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5, 684 SECONDARY_TDM_TX_5, 0, 1}, 685 [SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6, 686 SECONDARY_TDM_RX_6, 1, 1}, 687 [SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6, 688 SECONDARY_TDM_TX_6, 0, 1}, 689 [SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7, 690 SECONDARY_TDM_RX_7, 1, 1}, 691 [SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7, 692 SECONDARY_TDM_TX_7, 0, 1}, 693 [TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX, 694 TERTIARY_TDM_RX_0, 1, 1}, 695 [TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX, 696 TERTIARY_TDM_TX_0, 0, 1}, 697 [TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1, 698 TERTIARY_TDM_RX_1, 1, 1}, 699 [TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1, 700 TERTIARY_TDM_TX_1, 0, 1}, 701 [TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2, 702 TERTIARY_TDM_RX_2, 1, 1}, 703 [TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2, 704 TERTIARY_TDM_TX_2, 0, 1}, 705 [TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3, 706 TERTIARY_TDM_RX_3, 1, 1}, 707 [TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3, 708 TERTIARY_TDM_TX_3, 0, 1}, 709 [TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4, 710 TERTIARY_TDM_RX_4, 1, 1}, 711 [TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4, 712 TERTIARY_TDM_TX_4, 0, 1}, 713 [TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5, 714 TERTIARY_TDM_RX_5, 1, 1}, 715 [TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5, 716 TERTIARY_TDM_TX_5, 0, 1}, 717 [TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6, 718 TERTIARY_TDM_RX_6, 1, 1}, 719 [TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6, 720 TERTIARY_TDM_TX_6, 0, 1}, 721 [TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7, 722 TERTIARY_TDM_RX_7, 1, 1}, 723 [TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7, 724 TERTIARY_TDM_TX_7, 0, 1}, 725 [QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX, 726 QUATERNARY_TDM_RX_0, 1, 1}, 727 [QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX, 728 QUATERNARY_TDM_TX_0, 0, 1}, 729 [QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1, 730 QUATERNARY_TDM_RX_1, 1, 1}, 731 [QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1, 732 QUATERNARY_TDM_TX_1, 0, 1}, 733 [QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2, 734 QUATERNARY_TDM_RX_2, 1, 1}, 735 [QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2, 736 QUATERNARY_TDM_TX_2, 0, 1}, 737 [QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3, 738 QUATERNARY_TDM_RX_3, 1, 1}, 739 [QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3, 740 QUATERNARY_TDM_TX_3, 0, 1}, 741 [QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4, 742 QUATERNARY_TDM_RX_4, 1, 1}, 743 [QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4, 744 QUATERNARY_TDM_TX_4, 0, 1}, 745 [QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5, 746 QUATERNARY_TDM_RX_5, 1, 1}, 747 [QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5, 748 QUATERNARY_TDM_TX_5, 0, 1}, 749 [QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6, 750 QUATERNARY_TDM_RX_6, 1, 1}, 751 [QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6, 752 QUATERNARY_TDM_TX_6, 0, 1}, 753 [QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7, 754 QUATERNARY_TDM_RX_7, 1, 1}, 755 [QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7, 756 QUATERNARY_TDM_TX_7, 0, 1}, 757 [QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX, 758 QUINARY_TDM_RX_0, 1, 1}, 759 [QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX, 760 QUINARY_TDM_TX_0, 0, 1}, 761 [QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1, 762 QUINARY_TDM_RX_1, 1, 1}, 763 [QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1, 764 QUINARY_TDM_TX_1, 0, 1}, 765 [QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2, 766 QUINARY_TDM_RX_2, 1, 1}, 767 [QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2, 768 QUINARY_TDM_TX_2, 0, 1}, 769 [QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3, 770 QUINARY_TDM_RX_3, 1, 1}, 771 [QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3, 772 QUINARY_TDM_TX_3, 0, 1}, 773 [QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4, 774 QUINARY_TDM_RX_4, 1, 1}, 775 [QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4, 776 QUINARY_TDM_TX_4, 0, 1}, 777 [QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5, 778 QUINARY_TDM_RX_5, 1, 1}, 779 [QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5, 780 QUINARY_TDM_TX_5, 0, 1}, 781 [QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6, 782 QUINARY_TDM_RX_6, 1, 1}, 783 [QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6, 784 QUINARY_TDM_TX_6, 0, 1}, 785 [QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7, 786 QUINARY_TDM_RX_7, 1, 1}, 787 [QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7, 788 QUINARY_TDM_TX_7, 0, 1}, 789 [DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX, 790 DISPLAY_PORT_RX, 1, 1}, 791 [WSA_CODEC_DMA_RX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_0, 792 WSA_CODEC_DMA_RX_0, 1, 1}, 793 [WSA_CODEC_DMA_TX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_0, 794 WSA_CODEC_DMA_TX_0, 0, 1}, 795 [WSA_CODEC_DMA_RX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_1, 796 WSA_CODEC_DMA_RX_1, 1, 1}, 797 [WSA_CODEC_DMA_TX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_1, 798 WSA_CODEC_DMA_TX_1, 0, 1}, 799 [WSA_CODEC_DMA_TX_2] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_2, 800 WSA_CODEC_DMA_TX_2, 0, 1}, 801 [VA_CODEC_DMA_TX_0] = { AFE_PORT_ID_VA_CODEC_DMA_TX_0, 802 VA_CODEC_DMA_TX_0, 0, 1}, 803 [VA_CODEC_DMA_TX_1] = { AFE_PORT_ID_VA_CODEC_DMA_TX_1, 804 VA_CODEC_DMA_TX_1, 0, 1}, 805 [VA_CODEC_DMA_TX_2] = { AFE_PORT_ID_VA_CODEC_DMA_TX_2, 806 VA_CODEC_DMA_TX_2, 0, 1}, 807 [RX_CODEC_DMA_RX_0] = { AFE_PORT_ID_RX_CODEC_DMA_RX_0, 808 RX_CODEC_DMA_RX_0, 1, 1}, 809 [TX_CODEC_DMA_TX_0] = { AFE_PORT_ID_TX_CODEC_DMA_TX_0, 810 TX_CODEC_DMA_TX_0, 0, 1}, 811 [RX_CODEC_DMA_RX_1] = { AFE_PORT_ID_RX_CODEC_DMA_RX_1, 812 RX_CODEC_DMA_RX_1, 1, 1}, 813 [TX_CODEC_DMA_TX_1] = { AFE_PORT_ID_TX_CODEC_DMA_TX_1, 814 TX_CODEC_DMA_TX_1, 0, 1}, 815 [RX_CODEC_DMA_RX_2] = { AFE_PORT_ID_RX_CODEC_DMA_RX_2, 816 RX_CODEC_DMA_RX_2, 1, 1}, 817 [TX_CODEC_DMA_TX_2] = { AFE_PORT_ID_TX_CODEC_DMA_TX_2, 818 TX_CODEC_DMA_TX_2, 0, 1}, 819 [RX_CODEC_DMA_RX_3] = { AFE_PORT_ID_RX_CODEC_DMA_RX_3, 820 RX_CODEC_DMA_RX_3, 1, 1}, 821 [TX_CODEC_DMA_TX_3] = { AFE_PORT_ID_TX_CODEC_DMA_TX_3, 822 TX_CODEC_DMA_TX_3, 0, 1}, 823 [RX_CODEC_DMA_RX_4] = { AFE_PORT_ID_RX_CODEC_DMA_RX_4, 824 RX_CODEC_DMA_RX_4, 1, 1}, 825 [TX_CODEC_DMA_TX_4] = { AFE_PORT_ID_TX_CODEC_DMA_TX_4, 826 TX_CODEC_DMA_TX_4, 0, 1}, 827 [RX_CODEC_DMA_RX_5] = { AFE_PORT_ID_RX_CODEC_DMA_RX_5, 828 RX_CODEC_DMA_RX_5, 1, 1}, 829 [TX_CODEC_DMA_TX_5] = { AFE_PORT_ID_TX_CODEC_DMA_TX_5, 830 TX_CODEC_DMA_TX_5, 0, 1}, 831 [RX_CODEC_DMA_RX_6] = { AFE_PORT_ID_RX_CODEC_DMA_RX_6, 832 RX_CODEC_DMA_RX_6, 1, 1}, 833 [RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7, 834 RX_CODEC_DMA_RX_7, 1, 1}, 835 }; 836 837 static void q6afe_port_free(struct kref *ref) 838 { 839 struct q6afe_port *port; 840 struct q6afe *afe; 841 unsigned long flags; 842 843 port = container_of(ref, struct q6afe_port, refcount); 844 afe = port->afe; 845 spin_lock_irqsave(&afe->port_list_lock, flags); 846 list_del(&port->node); 847 spin_unlock_irqrestore(&afe->port_list_lock, flags); 848 kfree(port->scfg); 849 kfree(port); 850 } 851 852 static struct q6afe_port *q6afe_find_port(struct q6afe *afe, int token) 853 { 854 struct q6afe_port *p; 855 struct q6afe_port *ret = NULL; 856 unsigned long flags; 857 858 spin_lock_irqsave(&afe->port_list_lock, flags); 859 list_for_each_entry(p, &afe->port_list, node) 860 if (p->token == token) { 861 ret = p; 862 kref_get(&p->refcount); 863 break; 864 } 865 866 spin_unlock_irqrestore(&afe->port_list_lock, flags); 867 return ret; 868 } 869 870 static int q6afe_callback(struct apr_device *adev, struct apr_resp_pkt *data) 871 { 872 struct q6afe *afe = dev_get_drvdata(&adev->dev); 873 struct aprv2_ibasic_rsp_result_t *res; 874 struct apr_hdr *hdr = &data->hdr; 875 struct q6afe_port *port; 876 877 if (!data->payload_size) 878 return 0; 879 880 res = data->payload; 881 switch (hdr->opcode) { 882 case APR_BASIC_RSP_RESULT: { 883 if (res->status) { 884 dev_err(afe->dev, "cmd = 0x%x returned error = 0x%x\n", 885 res->opcode, res->status); 886 } 887 switch (res->opcode) { 888 case AFE_PORT_CMD_SET_PARAM_V2: 889 case AFE_PORT_CMD_DEVICE_STOP: 890 case AFE_PORT_CMD_DEVICE_START: 891 case AFE_SVC_CMD_SET_PARAM: 892 port = q6afe_find_port(afe, hdr->token); 893 if (port) { 894 port->result = *res; 895 wake_up(&port->wait); 896 kref_put(&port->refcount, q6afe_port_free); 897 } else if (hdr->token == AFE_CLK_TOKEN) { 898 afe->result = *res; 899 wake_up(&afe->wait); 900 } 901 break; 902 default: 903 dev_err(afe->dev, "Unknown cmd 0x%x\n", res->opcode); 904 break; 905 } 906 } 907 break; 908 case AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST: 909 afe->result.opcode = hdr->opcode; 910 afe->result.status = res->status; 911 wake_up(&afe->wait); 912 break; 913 default: 914 break; 915 } 916 917 return 0; 918 } 919 920 /** 921 * q6afe_get_port_id() - Get port id from a given port index 922 * 923 * @index: port index 924 * 925 * Return: Will be an negative on error or valid port_id on success 926 */ 927 int q6afe_get_port_id(int index) 928 { 929 if (index < 0 || index >= AFE_PORT_MAX) 930 return -EINVAL; 931 932 return port_maps[index].port_id; 933 } 934 EXPORT_SYMBOL_GPL(q6afe_get_port_id); 935 936 static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt, 937 struct q6afe_port *port, uint32_t rsp_opcode) 938 { 939 wait_queue_head_t *wait; 940 struct aprv2_ibasic_rsp_result_t *result; 941 int ret; 942 943 mutex_lock(&afe->lock); 944 if (port) { 945 wait = &port->wait; 946 result = &port->result; 947 } else { 948 result = &afe->result; 949 wait = &afe->wait; 950 } 951 952 result->opcode = 0; 953 result->status = 0; 954 955 ret = apr_send_pkt(afe->apr, pkt); 956 if (ret < 0) { 957 dev_err(afe->dev, "packet not transmitted (%d)\n", ret); 958 ret = -EINVAL; 959 goto err; 960 } 961 962 ret = wait_event_timeout(*wait, (result->opcode == rsp_opcode), 963 msecs_to_jiffies(TIMEOUT_MS)); 964 if (!ret) { 965 ret = -ETIMEDOUT; 966 } else if (result->status > 0) { 967 dev_err(afe->dev, "DSP returned error[%x]\n", 968 result->status); 969 ret = -EINVAL; 970 } else { 971 ret = 0; 972 } 973 974 err: 975 mutex_unlock(&afe->lock); 976 977 return ret; 978 } 979 980 static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port, 981 void *data, int param_id, int module_id, int psize, 982 int token) 983 { 984 struct afe_svc_cmd_set_param *param; 985 struct afe_port_param_data_v2 *pdata; 986 struct apr_pkt *pkt; 987 int ret, pkt_size; 988 void *p, *pl; 989 990 pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 991 p = kzalloc(pkt_size, GFP_KERNEL); 992 if (!p) 993 return -ENOMEM; 994 995 pkt = p; 996 param = p + APR_HDR_SIZE; 997 pdata = p + APR_HDR_SIZE + sizeof(*param); 998 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 999 memcpy(pl, data, psize); 1000 1001 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1002 APR_HDR_LEN(APR_HDR_SIZE), 1003 APR_PKT_VER); 1004 pkt->hdr.pkt_size = pkt_size; 1005 pkt->hdr.src_port = 0; 1006 pkt->hdr.dest_port = 0; 1007 pkt->hdr.token = token; 1008 pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM; 1009 1010 param->payload_size = sizeof(*pdata) + psize; 1011 param->payload_address_lsw = 0x00; 1012 param->payload_address_msw = 0x00; 1013 param->mem_map_handle = 0x00; 1014 pdata->module_id = module_id; 1015 pdata->param_id = param_id; 1016 pdata->param_size = psize; 1017 1018 ret = afe_apr_send_pkt(afe, pkt, port, AFE_SVC_CMD_SET_PARAM); 1019 if (ret) 1020 dev_err(afe->dev, "AFE set params failed %d\n", ret); 1021 1022 kfree(pkt); 1023 return ret; 1024 } 1025 1026 static int q6afe_port_set_param(struct q6afe_port *port, void *data, 1027 int param_id, int module_id, int psize) 1028 { 1029 return q6afe_set_param(port->afe, port, data, param_id, module_id, 1030 psize, port->token); 1031 } 1032 1033 static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data, 1034 int param_id, int module_id, int psize) 1035 { 1036 struct afe_port_cmd_set_param_v2 *param; 1037 struct afe_port_param_data_v2 *pdata; 1038 struct q6afe *afe = port->afe; 1039 struct apr_pkt *pkt; 1040 u16 port_id = port->id; 1041 int ret, pkt_size; 1042 void *p, *pl; 1043 1044 pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 1045 p = kzalloc(pkt_size, GFP_KERNEL); 1046 if (!p) 1047 return -ENOMEM; 1048 1049 pkt = p; 1050 param = p + APR_HDR_SIZE; 1051 pdata = p + APR_HDR_SIZE + sizeof(*param); 1052 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 1053 memcpy(pl, data, psize); 1054 1055 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1056 APR_HDR_LEN(APR_HDR_SIZE), 1057 APR_PKT_VER); 1058 pkt->hdr.pkt_size = pkt_size; 1059 pkt->hdr.src_port = 0; 1060 pkt->hdr.dest_port = 0; 1061 pkt->hdr.token = port->token; 1062 pkt->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; 1063 1064 param->port_id = port_id; 1065 param->payload_size = sizeof(*pdata) + psize; 1066 param->payload_address_lsw = 0x00; 1067 param->payload_address_msw = 0x00; 1068 param->mem_map_handle = 0x00; 1069 pdata->module_id = module_id; 1070 pdata->param_id = param_id; 1071 pdata->param_size = psize; 1072 1073 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_SET_PARAM_V2); 1074 if (ret) 1075 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1076 port_id, ret); 1077 1078 kfree(pkt); 1079 return ret; 1080 } 1081 1082 static int q6afe_port_set_lpass_clock(struct q6afe_port *port, 1083 struct afe_clk_cfg *cfg) 1084 { 1085 return q6afe_port_set_param_v2(port, cfg, 1086 AFE_PARAM_ID_LPAIF_CLK_CONFIG, 1087 AFE_MODULE_AUDIO_DEV_INTERFACE, 1088 sizeof(*cfg)); 1089 } 1090 1091 static int q6afe_set_lpass_clock_v2(struct q6afe_port *port, 1092 struct afe_clk_set *cfg) 1093 { 1094 return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET, 1095 AFE_MODULE_CLOCK_SET, sizeof(*cfg)); 1096 } 1097 1098 static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port, 1099 struct afe_digital_clk_cfg *cfg) 1100 { 1101 return q6afe_port_set_param_v2(port, cfg, 1102 AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG, 1103 AFE_MODULE_AUDIO_DEV_INTERFACE, 1104 sizeof(*cfg)); 1105 } 1106 1107 int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, 1108 int clk_root, unsigned int freq) 1109 { 1110 struct q6afe *afe = dev_get_drvdata(dev->parent); 1111 struct afe_clk_set cset = {0,}; 1112 1113 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1114 cset.clk_id = clk_id; 1115 cset.clk_freq_in_hz = freq; 1116 cset.clk_attri = attri; 1117 cset.clk_root = clk_root; 1118 cset.enable = !!freq; 1119 1120 return q6afe_set_param(afe, NULL, &cset, AFE_PARAM_ID_CLOCK_SET, 1121 AFE_MODULE_CLOCK_SET, sizeof(cset), 1122 AFE_CLK_TOKEN); 1123 } 1124 EXPORT_SYMBOL_GPL(q6afe_set_lpass_clock); 1125 1126 int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, 1127 int clk_src, int clk_root, 1128 unsigned int freq, int dir) 1129 { 1130 struct afe_clk_cfg ccfg = {0,}; 1131 struct afe_clk_set cset = {0,}; 1132 struct afe_digital_clk_cfg dcfg = {0,}; 1133 int ret; 1134 1135 switch (clk_id) { 1136 case LPAIF_DIG_CLK: 1137 dcfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1138 dcfg.clk_val = freq; 1139 dcfg.clk_root = clk_root; 1140 ret = q6afe_set_digital_codec_core_clock(port, &dcfg); 1141 break; 1142 case LPAIF_BIT_CLK: 1143 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1144 ccfg.clk_val1 = freq; 1145 ccfg.clk_src = clk_src; 1146 ccfg.clk_root = clk_root; 1147 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID; 1148 ret = q6afe_port_set_lpass_clock(port, &ccfg); 1149 break; 1150 1151 case LPAIF_OSR_CLK: 1152 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1153 ccfg.clk_val2 = freq; 1154 ccfg.clk_src = clk_src; 1155 ccfg.clk_root = clk_root; 1156 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID; 1157 ret = q6afe_port_set_lpass_clock(port, &ccfg); 1158 break; 1159 case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR: 1160 case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1: 1161 case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT: 1162 case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK: 1163 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1164 cset.clk_id = clk_id; 1165 cset.clk_freq_in_hz = freq; 1166 cset.clk_attri = clk_src; 1167 cset.clk_root = clk_root; 1168 cset.enable = !!freq; 1169 ret = q6afe_set_lpass_clock_v2(port, &cset); 1170 break; 1171 default: 1172 ret = -EINVAL; 1173 break; 1174 } 1175 1176 return ret; 1177 } 1178 EXPORT_SYMBOL_GPL(q6afe_port_set_sysclk); 1179 1180 /** 1181 * q6afe_port_stop() - Stop a afe port 1182 * 1183 * @port: Instance of port to stop 1184 * 1185 * Return: Will be an negative on packet size on success. 1186 */ 1187 int q6afe_port_stop(struct q6afe_port *port) 1188 { 1189 struct afe_port_cmd_device_stop *stop; 1190 struct q6afe *afe = port->afe; 1191 struct apr_pkt *pkt; 1192 int port_id = port->id; 1193 int ret = 0; 1194 int index, pkt_size; 1195 void *p; 1196 1197 index = port->token; 1198 if (index < 0 || index >= AFE_PORT_MAX) { 1199 dev_err(afe->dev, "AFE port index[%d] invalid!\n", index); 1200 return -EINVAL; 1201 } 1202 1203 pkt_size = APR_HDR_SIZE + sizeof(*stop); 1204 p = kzalloc(pkt_size, GFP_KERNEL); 1205 if (!p) 1206 return -ENOMEM; 1207 1208 pkt = p; 1209 stop = p + APR_HDR_SIZE; 1210 1211 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1212 APR_HDR_LEN(APR_HDR_SIZE), 1213 APR_PKT_VER); 1214 pkt->hdr.pkt_size = pkt_size; 1215 pkt->hdr.src_port = 0; 1216 pkt->hdr.dest_port = 0; 1217 pkt->hdr.token = index; 1218 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_STOP; 1219 stop->port_id = port_id; 1220 stop->reserved = 0; 1221 1222 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_STOP); 1223 if (ret) 1224 dev_err(afe->dev, "AFE close failed %d\n", ret); 1225 1226 kfree(pkt); 1227 return ret; 1228 } 1229 EXPORT_SYMBOL_GPL(q6afe_port_stop); 1230 1231 /** 1232 * q6afe_slim_port_prepare() - Prepare slim afe port. 1233 * 1234 * @port: Instance of afe port 1235 * @cfg: SLIM configuration for the afe port 1236 * 1237 */ 1238 void q6afe_slim_port_prepare(struct q6afe_port *port, 1239 struct q6afe_slim_cfg *cfg) 1240 { 1241 union afe_port_config *pcfg = &port->port_cfg; 1242 1243 pcfg->slim_cfg.sb_cfg_minor_version = AFE_API_VERSION_SLIMBUS_CONFIG; 1244 pcfg->slim_cfg.sample_rate = cfg->sample_rate; 1245 pcfg->slim_cfg.bit_width = cfg->bit_width; 1246 pcfg->slim_cfg.num_channels = cfg->num_channels; 1247 pcfg->slim_cfg.data_format = cfg->data_format; 1248 pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0]; 1249 pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1]; 1250 pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2]; 1251 pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3]; 1252 1253 } 1254 EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare); 1255 1256 /** 1257 * q6afe_tdm_port_prepare() - Prepare tdm afe port. 1258 * 1259 * @port: Instance of afe port 1260 * @cfg: TDM configuration for the afe port 1261 * 1262 */ 1263 void q6afe_tdm_port_prepare(struct q6afe_port *port, 1264 struct q6afe_tdm_cfg *cfg) 1265 { 1266 union afe_port_config *pcfg = &port->port_cfg; 1267 1268 pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG; 1269 pcfg->tdm_cfg.num_channels = cfg->num_channels; 1270 pcfg->tdm_cfg.sample_rate = cfg->sample_rate; 1271 pcfg->tdm_cfg.bit_width = cfg->bit_width; 1272 pcfg->tdm_cfg.data_format = cfg->data_format; 1273 pcfg->tdm_cfg.sync_mode = cfg->sync_mode; 1274 pcfg->tdm_cfg.sync_src = cfg->sync_src; 1275 pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame; 1276 1277 pcfg->tdm_cfg.slot_width = cfg->slot_width; 1278 pcfg->tdm_cfg.slot_mask = cfg->slot_mask; 1279 port->scfg = kzalloc(sizeof(*port->scfg), GFP_KERNEL); 1280 if (!port->scfg) 1281 return; 1282 1283 port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG; 1284 port->scfg->num_channels = cfg->num_channels; 1285 port->scfg->bitwidth = cfg->bit_width; 1286 port->scfg->data_align_type = cfg->data_align_type; 1287 memcpy(port->scfg->ch_mapping, cfg->ch_mapping, 1288 sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT); 1289 } 1290 EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare); 1291 1292 /** 1293 * q6afe_hdmi_port_prepare() - Prepare hdmi afe port. 1294 * 1295 * @port: Instance of afe port 1296 * @cfg: HDMI configuration for the afe port 1297 * 1298 */ 1299 void q6afe_hdmi_port_prepare(struct q6afe_port *port, 1300 struct q6afe_hdmi_cfg *cfg) 1301 { 1302 union afe_port_config *pcfg = &port->port_cfg; 1303 1304 pcfg->hdmi_multi_ch.hdmi_cfg_minor_version = 1305 AFE_API_VERSION_HDMI_CONFIG; 1306 pcfg->hdmi_multi_ch.datatype = cfg->datatype; 1307 pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation; 1308 pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate; 1309 pcfg->hdmi_multi_ch.bit_width = cfg->bit_width; 1310 } 1311 EXPORT_SYMBOL_GPL(q6afe_hdmi_port_prepare); 1312 1313 /** 1314 * q6afe_i2s_port_prepare() - Prepare i2s afe port. 1315 * 1316 * @port: Instance of afe port 1317 * @cfg: I2S configuration for the afe port 1318 * Return: Will be an negative on error and zero on success. 1319 */ 1320 int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg) 1321 { 1322 union afe_port_config *pcfg = &port->port_cfg; 1323 struct device *dev = port->afe->dev; 1324 int num_sd_lines; 1325 1326 pcfg->i2s_cfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1327 pcfg->i2s_cfg.sample_rate = cfg->sample_rate; 1328 pcfg->i2s_cfg.bit_width = cfg->bit_width; 1329 pcfg->i2s_cfg.data_format = AFE_LINEAR_PCM_DATA; 1330 1331 switch (cfg->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1332 case SND_SOC_DAIFMT_BP_FP: 1333 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL; 1334 break; 1335 case SND_SOC_DAIFMT_BC_FC: 1336 /* CPU is slave */ 1337 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL; 1338 break; 1339 default: 1340 break; 1341 } 1342 1343 num_sd_lines = hweight_long(cfg->sd_line_mask); 1344 1345 switch (num_sd_lines) { 1346 case 0: 1347 dev_err(dev, "no line is assigned\n"); 1348 return -EINVAL; 1349 case 1: 1350 switch (cfg->sd_line_mask) { 1351 case AFE_PORT_I2S_SD0_MASK: 1352 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1353 break; 1354 case AFE_PORT_I2S_SD1_MASK: 1355 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD1; 1356 break; 1357 case AFE_PORT_I2S_SD2_MASK: 1358 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1359 break; 1360 case AFE_PORT_I2S_SD3_MASK: 1361 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD3; 1362 break; 1363 default: 1364 dev_err(dev, "Invalid SD lines\n"); 1365 return -EINVAL; 1366 } 1367 break; 1368 case 2: 1369 switch (cfg->sd_line_mask) { 1370 case AFE_PORT_I2S_SD0_1_MASK: 1371 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD01; 1372 break; 1373 case AFE_PORT_I2S_SD2_3_MASK: 1374 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD23; 1375 break; 1376 default: 1377 dev_err(dev, "Invalid SD lines\n"); 1378 return -EINVAL; 1379 } 1380 break; 1381 case 3: 1382 switch (cfg->sd_line_mask) { 1383 case AFE_PORT_I2S_SD0_1_2_MASK: 1384 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_6CHS; 1385 break; 1386 default: 1387 dev_err(dev, "Invalid SD lines\n"); 1388 return -EINVAL; 1389 } 1390 break; 1391 case 4: 1392 switch (cfg->sd_line_mask) { 1393 case AFE_PORT_I2S_SD0_1_2_3_MASK: 1394 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_8CHS; 1395 1396 break; 1397 default: 1398 dev_err(dev, "Invalid SD lines\n"); 1399 return -EINVAL; 1400 } 1401 break; 1402 default: 1403 dev_err(dev, "Invalid SD lines\n"); 1404 return -EINVAL; 1405 } 1406 1407 switch (cfg->num_channels) { 1408 case 1: 1409 case 2: 1410 switch (pcfg->i2s_cfg.channel_mode) { 1411 case AFE_PORT_I2S_QUAD01: 1412 case AFE_PORT_I2S_6CHS: 1413 case AFE_PORT_I2S_8CHS: 1414 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1415 break; 1416 case AFE_PORT_I2S_QUAD23: 1417 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1418 break; 1419 } 1420 1421 if (cfg->num_channels == 2) 1422 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_STEREO; 1423 else 1424 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_MONO; 1425 1426 break; 1427 case 3: 1428 case 4: 1429 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_QUAD01) { 1430 dev_err(dev, "Invalid Channel mode\n"); 1431 return -EINVAL; 1432 } 1433 break; 1434 case 5: 1435 case 6: 1436 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_6CHS) { 1437 dev_err(dev, "Invalid Channel mode\n"); 1438 return -EINVAL; 1439 } 1440 break; 1441 case 7: 1442 case 8: 1443 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_8CHS) { 1444 dev_err(dev, "Invalid Channel mode\n"); 1445 return -EINVAL; 1446 } 1447 break; 1448 default: 1449 break; 1450 } 1451 1452 return 0; 1453 } 1454 EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare); 1455 1456 /** 1457 * q6afe_cdc_dma_port_prepare() - Prepare dma afe port. 1458 * 1459 * @port: Instance of afe port 1460 * @cfg: DMA configuration for the afe port 1461 * 1462 */ 1463 void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, 1464 struct q6afe_cdc_dma_cfg *cfg) 1465 { 1466 union afe_port_config *pcfg = &port->port_cfg; 1467 struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg; 1468 1469 dma_cfg->cdc_dma_cfg_minor_version = AFE_API_VERSION_CODEC_DMA_CONFIG; 1470 dma_cfg->sample_rate = cfg->sample_rate; 1471 dma_cfg->bit_width = cfg->bit_width; 1472 dma_cfg->data_format = cfg->data_format; 1473 dma_cfg->num_channels = cfg->num_channels; 1474 if (!cfg->active_channels_mask) 1475 dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1; 1476 } 1477 EXPORT_SYMBOL_GPL(q6afe_cdc_dma_port_prepare); 1478 /** 1479 * q6afe_port_start() - Start a afe port 1480 * 1481 * @port: Instance of port to start 1482 * 1483 * Return: Will be an negative on packet size on success. 1484 */ 1485 int q6afe_port_start(struct q6afe_port *port) 1486 { 1487 struct afe_port_cmd_device_start *start; 1488 struct q6afe *afe = port->afe; 1489 int port_id = port->id; 1490 int ret, param_id = port->cfg_type; 1491 struct apr_pkt *pkt; 1492 int pkt_size; 1493 void *p; 1494 1495 ret = q6afe_port_set_param_v2(port, &port->port_cfg, param_id, 1496 AFE_MODULE_AUDIO_DEV_INTERFACE, 1497 sizeof(port->port_cfg)); 1498 if (ret) { 1499 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1500 port_id, ret); 1501 return ret; 1502 } 1503 1504 if (port->scfg) { 1505 ret = q6afe_port_set_param_v2(port, port->scfg, 1506 AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG, 1507 AFE_MODULE_TDM, sizeof(*port->scfg)); 1508 if (ret) { 1509 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1510 port_id, ret); 1511 return ret; 1512 } 1513 } 1514 1515 pkt_size = APR_HDR_SIZE + sizeof(*start); 1516 p = kzalloc(pkt_size, GFP_KERNEL); 1517 if (!p) 1518 return -ENOMEM; 1519 1520 pkt = p; 1521 start = p + APR_HDR_SIZE; 1522 1523 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1524 APR_HDR_LEN(APR_HDR_SIZE), 1525 APR_PKT_VER); 1526 pkt->hdr.pkt_size = pkt_size; 1527 pkt->hdr.src_port = 0; 1528 pkt->hdr.dest_port = 0; 1529 pkt->hdr.token = port->token; 1530 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_START; 1531 1532 start->port_id = port_id; 1533 1534 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_START); 1535 if (ret) 1536 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1537 port_id, ret); 1538 1539 kfree(pkt); 1540 return ret; 1541 } 1542 EXPORT_SYMBOL_GPL(q6afe_port_start); 1543 1544 /** 1545 * q6afe_port_get_from_id() - Get port instance from a port id 1546 * 1547 * @dev: Pointer to afe child device. 1548 * @id: port id 1549 * 1550 * Return: Will be an error pointer on error or a valid afe port 1551 * on success. 1552 */ 1553 struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) 1554 { 1555 int port_id; 1556 struct q6afe *afe = dev_get_drvdata(dev->parent); 1557 struct q6afe_port *port; 1558 unsigned long flags; 1559 int cfg_type; 1560 1561 if (id < 0 || id >= AFE_PORT_MAX) { 1562 dev_err(dev, "AFE port token[%d] invalid!\n", id); 1563 return ERR_PTR(-EINVAL); 1564 } 1565 1566 /* if port is multiple times bind/unbind before callback finishes */ 1567 port = q6afe_find_port(afe, id); 1568 if (port) { 1569 dev_err(dev, "AFE Port already open\n"); 1570 return port; 1571 } 1572 1573 port_id = port_maps[id].port_id; 1574 1575 switch (port_id) { 1576 case AFE_PORT_ID_MULTICHAN_HDMI_RX: 1577 case AFE_PORT_ID_HDMI_OVER_DP_RX: 1578 cfg_type = AFE_PARAM_ID_HDMI_CONFIG; 1579 break; 1580 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX: 1581 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX: 1582 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX: 1583 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX: 1584 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX: 1585 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX: 1586 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX: 1587 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX: 1588 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX: 1589 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX: 1590 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX: 1591 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX: 1592 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX: 1593 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX: 1594 cfg_type = AFE_PARAM_ID_SLIMBUS_CONFIG; 1595 break; 1596 1597 case AFE_PORT_ID_PRIMARY_MI2S_RX: 1598 case AFE_PORT_ID_PRIMARY_MI2S_TX: 1599 case AFE_PORT_ID_SECONDARY_MI2S_RX: 1600 case AFE_PORT_ID_SECONDARY_MI2S_TX: 1601 case AFE_PORT_ID_TERTIARY_MI2S_RX: 1602 case AFE_PORT_ID_TERTIARY_MI2S_TX: 1603 case AFE_PORT_ID_QUATERNARY_MI2S_RX: 1604 case AFE_PORT_ID_QUATERNARY_MI2S_TX: 1605 case AFE_PORT_ID_QUINARY_MI2S_RX: 1606 case AFE_PORT_ID_QUINARY_MI2S_TX: 1607 cfg_type = AFE_PARAM_ID_I2S_CONFIG; 1608 break; 1609 case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: 1610 cfg_type = AFE_PARAM_ID_TDM_CONFIG; 1611 break; 1612 case AFE_PORT_ID_WSA_CODEC_DMA_RX_0 ... AFE_PORT_ID_RX_CODEC_DMA_RX_7: 1613 cfg_type = AFE_PARAM_ID_CODEC_DMA_CONFIG; 1614 break; 1615 default: 1616 dev_err(dev, "Invalid port id 0x%x\n", port_id); 1617 return ERR_PTR(-EINVAL); 1618 } 1619 1620 port = kzalloc(sizeof(*port), GFP_KERNEL); 1621 if (!port) 1622 return ERR_PTR(-ENOMEM); 1623 1624 init_waitqueue_head(&port->wait); 1625 1626 port->token = id; 1627 port->id = port_id; 1628 port->afe = afe; 1629 port->cfg_type = cfg_type; 1630 kref_init(&port->refcount); 1631 1632 spin_lock_irqsave(&afe->port_list_lock, flags); 1633 list_add_tail(&port->node, &afe->port_list); 1634 spin_unlock_irqrestore(&afe->port_list_lock, flags); 1635 1636 return port; 1637 1638 } 1639 EXPORT_SYMBOL_GPL(q6afe_port_get_from_id); 1640 1641 /** 1642 * q6afe_port_put() - Release port reference 1643 * 1644 * @port: Instance of port to put 1645 */ 1646 void q6afe_port_put(struct q6afe_port *port) 1647 { 1648 kref_put(&port->refcount, q6afe_port_free); 1649 } 1650 EXPORT_SYMBOL_GPL(q6afe_port_put); 1651 1652 int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 1653 uint32_t client_handle) 1654 { 1655 struct q6afe *afe = dev_get_drvdata(dev->parent); 1656 struct afe_cmd_remote_lpass_core_hw_devote_request *vote_cfg; 1657 struct apr_pkt *pkt; 1658 int ret = 0; 1659 int pkt_size; 1660 void *p; 1661 1662 pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); 1663 p = kzalloc(pkt_size, GFP_KERNEL); 1664 if (!p) 1665 return -ENOMEM; 1666 1667 pkt = p; 1668 vote_cfg = p + APR_HDR_SIZE; 1669 1670 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1671 APR_HDR_LEN(APR_HDR_SIZE), 1672 APR_PKT_VER); 1673 pkt->hdr.pkt_size = pkt_size; 1674 pkt->hdr.src_port = 0; 1675 pkt->hdr.dest_port = 0; 1676 pkt->hdr.token = hw_block_id; 1677 pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST; 1678 vote_cfg->hw_block_id = hw_block_id; 1679 vote_cfg->client_handle = client_handle; 1680 1681 ret = apr_send_pkt(afe->apr, pkt); 1682 if (ret < 0) 1683 dev_err(afe->dev, "AFE failed to unvote (%d)\n", hw_block_id); 1684 1685 kfree(pkt); 1686 return ret; 1687 } 1688 EXPORT_SYMBOL(q6afe_unvote_lpass_core_hw); 1689 1690 int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 1691 const char *client_name, uint32_t *client_handle) 1692 { 1693 struct q6afe *afe = dev_get_drvdata(dev->parent); 1694 struct afe_cmd_remote_lpass_core_hw_vote_request *vote_cfg; 1695 struct apr_pkt *pkt; 1696 int ret = 0; 1697 int pkt_size; 1698 void *p; 1699 1700 pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); 1701 p = kzalloc(pkt_size, GFP_KERNEL); 1702 if (!p) 1703 return -ENOMEM; 1704 1705 pkt = p; 1706 vote_cfg = p + APR_HDR_SIZE; 1707 1708 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1709 APR_HDR_LEN(APR_HDR_SIZE), 1710 APR_PKT_VER); 1711 pkt->hdr.pkt_size = pkt_size; 1712 pkt->hdr.src_port = 0; 1713 pkt->hdr.dest_port = 0; 1714 pkt->hdr.token = hw_block_id; 1715 pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST; 1716 vote_cfg->hw_block_id = hw_block_id; 1717 strscpy(vote_cfg->client_name, client_name, 1718 sizeof(vote_cfg->client_name)); 1719 1720 ret = afe_apr_send_pkt(afe, pkt, NULL, 1721 AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST); 1722 if (ret) 1723 dev_err(afe->dev, "AFE failed to vote (%d)\n", hw_block_id); 1724 1725 1726 kfree(pkt); 1727 return ret; 1728 } 1729 EXPORT_SYMBOL(q6afe_vote_lpass_core_hw); 1730 1731 static int q6afe_probe(struct apr_device *adev) 1732 { 1733 struct q6afe *afe; 1734 struct device *dev = &adev->dev; 1735 1736 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 1737 if (!afe) 1738 return -ENOMEM; 1739 1740 q6core_get_svc_api_info(adev->svc_id, &afe->ainfo); 1741 afe->apr = adev; 1742 mutex_init(&afe->lock); 1743 init_waitqueue_head(&afe->wait); 1744 afe->dev = dev; 1745 INIT_LIST_HEAD(&afe->port_list); 1746 spin_lock_init(&afe->port_list_lock); 1747 1748 dev_set_drvdata(dev, afe); 1749 1750 return devm_of_platform_populate(dev); 1751 } 1752 1753 #ifdef CONFIG_OF 1754 static const struct of_device_id q6afe_device_id[] = { 1755 { .compatible = "qcom,q6afe" }, 1756 {}, 1757 }; 1758 MODULE_DEVICE_TABLE(of, q6afe_device_id); 1759 #endif 1760 1761 static struct apr_driver qcom_q6afe_driver = { 1762 .probe = q6afe_probe, 1763 .callback = q6afe_callback, 1764 .driver = { 1765 .name = "qcom-q6afe", 1766 .of_match_table = of_match_ptr(q6afe_device_id), 1767 1768 }, 1769 }; 1770 1771 module_apr_driver(qcom_q6afe_driver); 1772 MODULE_DESCRIPTION("Q6 Audio Front End"); 1773 MODULE_LICENSE("GPL v2"); 1774