1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2018, Linaro Limited 4 5 #include <linux/slab.h> 6 #include <linux/kernel.h> 7 #include <linux/uaccess.h> 8 #include <linux/wait.h> 9 #include <linux/jiffies.h> 10 #include <linux/sched.h> 11 #include <linux/module.h> 12 #include <linux/kref.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/spinlock.h> 16 #include <linux/delay.h> 17 #include <linux/soc/qcom/apr.h> 18 #include <sound/soc.h> 19 #include <sound/soc-dai.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include "q6dsp-errno.h" 23 #include "q6core.h" 24 #include "q6afe.h" 25 26 /* AFE CMDs */ 27 #define AFE_PORT_CMD_DEVICE_START 0x000100E5 28 #define AFE_PORT_CMD_DEVICE_STOP 0x000100E6 29 #define AFE_PORT_CMD_SET_PARAM_V2 0x000100EF 30 #define AFE_SVC_CMD_SET_PARAM 0x000100f3 31 #define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106 32 #define AFE_PARAM_ID_HDMI_CONFIG 0x00010210 33 #define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C 34 #define AFE_MODULE_TDM 0x0001028A 35 36 #define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235 37 38 #define AFE_PARAM_ID_LPAIF_CLK_CONFIG 0x00010238 39 #define AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG 0x00010239 40 41 #define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212 42 #define AFE_PARAM_ID_I2S_CONFIG 0x0001020D 43 #define AFE_PARAM_ID_TDM_CONFIG 0x0001029D 44 #define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297 45 46 /* I2S config specific */ 47 #define AFE_API_VERSION_I2S_CONFIG 0x1 48 #define AFE_PORT_I2S_SD0 0x1 49 #define AFE_PORT_I2S_SD1 0x2 50 #define AFE_PORT_I2S_SD2 0x3 51 #define AFE_PORT_I2S_SD3 0x4 52 #define AFE_PORT_I2S_SD0_MASK BIT(0x0) 53 #define AFE_PORT_I2S_SD1_MASK BIT(0x1) 54 #define AFE_PORT_I2S_SD2_MASK BIT(0x2) 55 #define AFE_PORT_I2S_SD3_MASK BIT(0x3) 56 #define AFE_PORT_I2S_SD0_1_MASK GENMASK(1, 0) 57 #define AFE_PORT_I2S_SD2_3_MASK GENMASK(3, 2) 58 #define AFE_PORT_I2S_SD0_1_2_MASK GENMASK(2, 0) 59 #define AFE_PORT_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 60 #define AFE_PORT_I2S_QUAD01 0x5 61 #define AFE_PORT_I2S_QUAD23 0x6 62 #define AFE_PORT_I2S_6CHS 0x7 63 #define AFE_PORT_I2S_8CHS 0x8 64 #define AFE_PORT_I2S_MONO 0x0 65 #define AFE_PORT_I2S_STEREO 0x1 66 #define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL 0x0 67 #define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL 0x1 68 #define AFE_LINEAR_PCM_DATA 0x0 69 70 71 /* Port IDs */ 72 #define AFE_API_VERSION_HDMI_CONFIG 0x1 73 #define AFE_PORT_ID_MULTICHAN_HDMI_RX 0x100E 74 #define AFE_PORT_ID_HDMI_OVER_DP_RX 0x6020 75 76 #define AFE_API_VERSION_SLIMBUS_CONFIG 0x1 77 /* Clock set API version */ 78 #define AFE_API_VERSION_CLOCK_SET 1 79 #define Q6AFE_LPASS_CLK_CONFIG_API_VERSION 0x1 80 #define AFE_MODULE_CLOCK_SET 0x0001028F 81 #define AFE_PARAM_ID_CLOCK_SET 0x00010290 82 83 /* SLIMbus Rx port on channel 0. */ 84 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX 0x4000 85 /* SLIMbus Tx port on channel 0. */ 86 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX 0x4001 87 /* SLIMbus Rx port on channel 1. */ 88 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX 0x4002 89 /* SLIMbus Tx port on channel 1. */ 90 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX 0x4003 91 /* SLIMbus Rx port on channel 2. */ 92 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX 0x4004 93 /* SLIMbus Tx port on channel 2. */ 94 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX 0x4005 95 /* SLIMbus Rx port on channel 3. */ 96 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX 0x4006 97 /* SLIMbus Tx port on channel 3. */ 98 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX 0x4007 99 /* SLIMbus Rx port on channel 4. */ 100 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX 0x4008 101 /* SLIMbus Tx port on channel 4. */ 102 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX 0x4009 103 /* SLIMbus Rx port on channel 5. */ 104 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX 0x400a 105 /* SLIMbus Tx port on channel 5. */ 106 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX 0x400b 107 /* SLIMbus Rx port on channel 6. */ 108 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX 0x400c 109 /* SLIMbus Tx port on channel 6. */ 110 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX 0x400d 111 #define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000 112 #define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001 113 #define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002 114 #define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003 115 #define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004 116 #define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005 117 #define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006 118 #define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 119 120 /* Start of the range of port IDs for TDM devices. */ 121 #define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000 122 123 /* End of the range of port IDs for TDM devices. */ 124 #define AFE_PORT_ID_TDM_PORT_RANGE_END \ 125 (AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1) 126 127 /* Size of the range of port IDs for TDM ports. */ 128 #define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \ 129 (AFE_PORT_ID_TDM_PORT_RANGE_END - \ 130 AFE_PORT_ID_TDM_PORT_RANGE_START+1) 131 132 #define AFE_PORT_ID_PRIMARY_TDM_RX \ 133 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00) 134 #define AFE_PORT_ID_PRIMARY_TDM_RX_1 \ 135 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x02) 136 #define AFE_PORT_ID_PRIMARY_TDM_RX_2 \ 137 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x04) 138 #define AFE_PORT_ID_PRIMARY_TDM_RX_3 \ 139 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x06) 140 #define AFE_PORT_ID_PRIMARY_TDM_RX_4 \ 141 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x08) 142 #define AFE_PORT_ID_PRIMARY_TDM_RX_5 \ 143 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A) 144 #define AFE_PORT_ID_PRIMARY_TDM_RX_6 \ 145 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C) 146 #define AFE_PORT_ID_PRIMARY_TDM_RX_7 \ 147 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E) 148 149 #define AFE_PORT_ID_PRIMARY_TDM_TX \ 150 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01) 151 #define AFE_PORT_ID_PRIMARY_TDM_TX_1 \ 152 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x02) 153 #define AFE_PORT_ID_PRIMARY_TDM_TX_2 \ 154 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x04) 155 #define AFE_PORT_ID_PRIMARY_TDM_TX_3 \ 156 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x06) 157 #define AFE_PORT_ID_PRIMARY_TDM_TX_4 \ 158 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x08) 159 #define AFE_PORT_ID_PRIMARY_TDM_TX_5 \ 160 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A) 161 #define AFE_PORT_ID_PRIMARY_TDM_TX_6 \ 162 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C) 163 #define AFE_PORT_ID_PRIMARY_TDM_TX_7 \ 164 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E) 165 166 #define AFE_PORT_ID_SECONDARY_TDM_RX \ 167 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10) 168 #define AFE_PORT_ID_SECONDARY_TDM_RX_1 \ 169 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x02) 170 #define AFE_PORT_ID_SECONDARY_TDM_RX_2 \ 171 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x04) 172 #define AFE_PORT_ID_SECONDARY_TDM_RX_3 \ 173 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x06) 174 #define AFE_PORT_ID_SECONDARY_TDM_RX_4 \ 175 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x08) 176 #define AFE_PORT_ID_SECONDARY_TDM_RX_5 \ 177 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A) 178 #define AFE_PORT_ID_SECONDARY_TDM_RX_6 \ 179 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C) 180 #define AFE_PORT_ID_SECONDARY_TDM_RX_7 \ 181 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E) 182 183 #define AFE_PORT_ID_SECONDARY_TDM_TX \ 184 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11) 185 #define AFE_PORT_ID_SECONDARY_TDM_TX_1 \ 186 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x02) 187 #define AFE_PORT_ID_SECONDARY_TDM_TX_2 \ 188 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x04) 189 #define AFE_PORT_ID_SECONDARY_TDM_TX_3 \ 190 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x06) 191 #define AFE_PORT_ID_SECONDARY_TDM_TX_4 \ 192 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x08) 193 #define AFE_PORT_ID_SECONDARY_TDM_TX_5 \ 194 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A) 195 #define AFE_PORT_ID_SECONDARY_TDM_TX_6 \ 196 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C) 197 #define AFE_PORT_ID_SECONDARY_TDM_TX_7 \ 198 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E) 199 200 #define AFE_PORT_ID_TERTIARY_TDM_RX \ 201 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20) 202 #define AFE_PORT_ID_TERTIARY_TDM_RX_1 \ 203 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x02) 204 #define AFE_PORT_ID_TERTIARY_TDM_RX_2 \ 205 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x04) 206 #define AFE_PORT_ID_TERTIARY_TDM_RX_3 \ 207 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x06) 208 #define AFE_PORT_ID_TERTIARY_TDM_RX_4 \ 209 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x08) 210 #define AFE_PORT_ID_TERTIARY_TDM_RX_5 \ 211 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A) 212 #define AFE_PORT_ID_TERTIARY_TDM_RX_6 \ 213 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C) 214 #define AFE_PORT_ID_TERTIARY_TDM_RX_7 \ 215 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E) 216 217 #define AFE_PORT_ID_TERTIARY_TDM_TX \ 218 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21) 219 #define AFE_PORT_ID_TERTIARY_TDM_TX_1 \ 220 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x02) 221 #define AFE_PORT_ID_TERTIARY_TDM_TX_2 \ 222 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x04) 223 #define AFE_PORT_ID_TERTIARY_TDM_TX_3 \ 224 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x06) 225 #define AFE_PORT_ID_TERTIARY_TDM_TX_4 \ 226 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x08) 227 #define AFE_PORT_ID_TERTIARY_TDM_TX_5 \ 228 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A) 229 #define AFE_PORT_ID_TERTIARY_TDM_TX_6 \ 230 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C) 231 #define AFE_PORT_ID_TERTIARY_TDM_TX_7 \ 232 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E) 233 234 #define AFE_PORT_ID_QUATERNARY_TDM_RX \ 235 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30) 236 #define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \ 237 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02) 238 #define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \ 239 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04) 240 #define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \ 241 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06) 242 #define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \ 243 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08) 244 #define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \ 245 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A) 246 #define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \ 247 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C) 248 #define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \ 249 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E) 250 251 #define AFE_PORT_ID_QUATERNARY_TDM_TX \ 252 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31) 253 #define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \ 254 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02) 255 #define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \ 256 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04) 257 #define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \ 258 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06) 259 #define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \ 260 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08) 261 #define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \ 262 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A) 263 #define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \ 264 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C) 265 #define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \ 266 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E) 267 268 #define AFE_PORT_ID_QUINARY_TDM_RX \ 269 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40) 270 #define AFE_PORT_ID_QUINARY_TDM_RX_1 \ 271 (AFE_PORT_ID_QUINARY_TDM_RX + 0x02) 272 #define AFE_PORT_ID_QUINARY_TDM_RX_2 \ 273 (AFE_PORT_ID_QUINARY_TDM_RX + 0x04) 274 #define AFE_PORT_ID_QUINARY_TDM_RX_3 \ 275 (AFE_PORT_ID_QUINARY_TDM_RX + 0x06) 276 #define AFE_PORT_ID_QUINARY_TDM_RX_4 \ 277 (AFE_PORT_ID_QUINARY_TDM_RX + 0x08) 278 #define AFE_PORT_ID_QUINARY_TDM_RX_5 \ 279 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0A) 280 #define AFE_PORT_ID_QUINARY_TDM_RX_6 \ 281 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0C) 282 #define AFE_PORT_ID_QUINARY_TDM_RX_7 \ 283 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0E) 284 285 #define AFE_PORT_ID_QUINARY_TDM_TX \ 286 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41) 287 #define AFE_PORT_ID_QUINARY_TDM_TX_1 \ 288 (AFE_PORT_ID_QUINARY_TDM_TX + 0x02) 289 #define AFE_PORT_ID_QUINARY_TDM_TX_2 \ 290 (AFE_PORT_ID_QUINARY_TDM_TX + 0x04) 291 #define AFE_PORT_ID_QUINARY_TDM_TX_3 \ 292 (AFE_PORT_ID_QUINARY_TDM_TX + 0x06) 293 #define AFE_PORT_ID_QUINARY_TDM_TX_4 \ 294 (AFE_PORT_ID_QUINARY_TDM_TX + 0x08) 295 #define AFE_PORT_ID_QUINARY_TDM_TX_5 \ 296 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0A) 297 #define AFE_PORT_ID_QUINARY_TDM_TX_6 \ 298 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0C) 299 #define AFE_PORT_ID_QUINARY_TDM_TX_7 \ 300 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0E) 301 302 #define Q6AFE_LPASS_MODE_CLK1_VALID 1 303 #define Q6AFE_LPASS_MODE_CLK2_VALID 2 304 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 305 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 306 #define AFE_API_VERSION_TDM_CONFIG 1 307 #define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1 308 309 #define TIMEOUT_MS 1000 310 #define AFE_CMD_RESP_AVAIL 0 311 #define AFE_CMD_RESP_NONE 1 312 313 struct q6afe { 314 struct apr_device *apr; 315 struct device *dev; 316 struct q6core_svc_api_info ainfo; 317 struct mutex lock; 318 struct list_head port_list; 319 spinlock_t port_list_lock; 320 }; 321 322 struct afe_port_cmd_device_start { 323 u16 port_id; 324 u16 reserved; 325 } __packed; 326 327 struct afe_port_cmd_device_stop { 328 u16 port_id; 329 u16 reserved; 330 /* Reserved for 32-bit alignment. This field must be set to 0.*/ 331 } __packed; 332 333 struct afe_port_param_data_v2 { 334 u32 module_id; 335 u32 param_id; 336 u16 param_size; 337 u16 reserved; 338 } __packed; 339 340 struct afe_svc_cmd_set_param { 341 uint32_t payload_size; 342 uint32_t payload_address_lsw; 343 uint32_t payload_address_msw; 344 uint32_t mem_map_handle; 345 } __packed; 346 347 struct afe_port_cmd_set_param_v2 { 348 u16 port_id; 349 u16 payload_size; 350 u32 payload_address_lsw; 351 u32 payload_address_msw; 352 u32 mem_map_handle; 353 } __packed; 354 355 struct afe_param_id_hdmi_multi_chan_audio_cfg { 356 u32 hdmi_cfg_minor_version; 357 u16 datatype; 358 u16 channel_allocation; 359 u32 sample_rate; 360 u16 bit_width; 361 u16 reserved; 362 } __packed; 363 364 struct afe_param_id_slimbus_cfg { 365 u32 sb_cfg_minor_version; 366 /* Minor version used for tracking the version of the SLIMBUS 367 * configuration interface. 368 * Supported values: #AFE_API_VERSION_SLIMBUS_CONFIG 369 */ 370 371 u16 slimbus_dev_id; 372 /* SLIMbus hardware device ID, which is required to handle 373 * multiple SLIMbus hardware blocks. 374 * Supported values: - #AFE_SLIMBUS_DEVICE_1 - #AFE_SLIMBUS_DEVICE_2 375 */ 376 u16 bit_width; 377 /* Bit width of the sample. 378 * Supported values: 16, 24 379 */ 380 u16 data_format; 381 /* Data format supported by the SLIMbus hardware. The default is 382 * 0 (#AFE_SB_DATA_FORMAT_NOT_INDICATED), which indicates the 383 * hardware does not perform any format conversions before the data 384 * transfer. 385 */ 386 u16 num_channels; 387 /* Number of channels. 388 * Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT 389 */ 390 u8 shared_ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 391 /* Mapping of shared channel IDs (128 to 255) to which the 392 * master port is to be connected. 393 * Shared_channel_mapping[i] represents the shared channel assigned 394 * for audio channel i in multichannel audio data. 395 */ 396 u32 sample_rate; 397 /* Sampling rate of the port. 398 * Supported values: 399 * - #AFE_PORT_SAMPLE_RATE_8K 400 * - #AFE_PORT_SAMPLE_RATE_16K 401 * - #AFE_PORT_SAMPLE_RATE_48K 402 * - #AFE_PORT_SAMPLE_RATE_96K 403 * - #AFE_PORT_SAMPLE_RATE_192K 404 */ 405 } __packed; 406 407 struct afe_clk_cfg { 408 u32 i2s_cfg_minor_version; 409 u32 clk_val1; 410 u32 clk_val2; 411 u16 clk_src; 412 u16 clk_root; 413 u16 clk_set_mode; 414 u16 reserved; 415 } __packed; 416 417 struct afe_digital_clk_cfg { 418 u32 i2s_cfg_minor_version; 419 u32 clk_val; 420 u16 clk_root; 421 u16 reserved; 422 } __packed; 423 424 struct afe_param_id_i2s_cfg { 425 u32 i2s_cfg_minor_version; 426 u16 bit_width; 427 u16 channel_mode; 428 u16 mono_stereo; 429 u16 ws_src; 430 u32 sample_rate; 431 u16 data_format; 432 u16 reserved; 433 } __packed; 434 435 struct afe_param_id_tdm_cfg { 436 u32 tdm_cfg_minor_version; 437 u32 num_channels; 438 u32 sample_rate; 439 u32 bit_width; 440 u16 data_format; 441 u16 sync_mode; 442 u16 sync_src; 443 u16 nslots_per_frame; 444 u16 ctrl_data_out_enable; 445 u16 ctrl_invert_sync_pulse; 446 u16 ctrl_sync_data_delay; 447 u16 slot_width; 448 u32 slot_mask; 449 } __packed; 450 451 union afe_port_config { 452 struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch; 453 struct afe_param_id_slimbus_cfg slim_cfg; 454 struct afe_param_id_i2s_cfg i2s_cfg; 455 struct afe_param_id_tdm_cfg tdm_cfg; 456 } __packed; 457 458 459 struct afe_clk_set { 460 uint32_t clk_set_minor_version; 461 uint32_t clk_id; 462 uint32_t clk_freq_in_hz; 463 uint16_t clk_attri; 464 uint16_t clk_root; 465 uint32_t enable; 466 }; 467 468 struct afe_param_id_slot_mapping_cfg { 469 u32 minor_version; 470 u16 num_channels; 471 u16 bitwidth; 472 u32 data_align_type; 473 u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 474 } __packed; 475 476 struct q6afe_port { 477 wait_queue_head_t wait; 478 union afe_port_config port_cfg; 479 struct afe_param_id_slot_mapping_cfg *scfg; 480 struct aprv2_ibasic_rsp_result_t result; 481 int token; 482 int id; 483 int cfg_type; 484 struct q6afe *afe; 485 struct kref refcount; 486 struct list_head node; 487 }; 488 489 struct afe_port_map { 490 int port_id; 491 int token; 492 int is_rx; 493 int is_dig_pcm; 494 }; 495 496 /* 497 * Mapping between Virtual Port IDs to DSP AFE Port ID 498 * On B Family SoCs DSP Port IDs are consistent across multiple SoCs 499 * on A Family SoCs DSP port IDs are same as virtual Port IDs. 500 */ 501 502 static struct afe_port_map port_maps[AFE_PORT_MAX] = { 503 [HDMI_RX] = { AFE_PORT_ID_MULTICHAN_HDMI_RX, HDMI_RX, 1, 1}, 504 [SLIMBUS_0_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX, 505 SLIMBUS_0_RX, 1, 1}, 506 [SLIMBUS_1_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX, 507 SLIMBUS_1_RX, 1, 1}, 508 [SLIMBUS_2_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX, 509 SLIMBUS_2_RX, 1, 1}, 510 [SLIMBUS_3_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX, 511 SLIMBUS_3_RX, 1, 1}, 512 [SLIMBUS_4_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX, 513 SLIMBUS_4_RX, 1, 1}, 514 [SLIMBUS_5_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX, 515 SLIMBUS_5_RX, 1, 1}, 516 [SLIMBUS_6_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX, 517 SLIMBUS_6_RX, 1, 1}, 518 [SLIMBUS_0_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX, 519 SLIMBUS_0_TX, 0, 1}, 520 [SLIMBUS_1_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX, 521 SLIMBUS_1_TX, 0, 1}, 522 [SLIMBUS_2_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX, 523 SLIMBUS_2_TX, 0, 1}, 524 [SLIMBUS_3_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX, 525 SLIMBUS_3_TX, 0, 1}, 526 [SLIMBUS_4_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX, 527 SLIMBUS_4_TX, 0, 1}, 528 [SLIMBUS_5_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX, 529 SLIMBUS_5_TX, 0, 1}, 530 [SLIMBUS_6_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX, 531 SLIMBUS_6_TX, 0, 1}, 532 [PRIMARY_MI2S_RX] = { AFE_PORT_ID_PRIMARY_MI2S_RX, 533 PRIMARY_MI2S_RX, 1, 1}, 534 [PRIMARY_MI2S_TX] = { AFE_PORT_ID_PRIMARY_MI2S_TX, 535 PRIMARY_MI2S_RX, 0, 1}, 536 [SECONDARY_MI2S_RX] = { AFE_PORT_ID_SECONDARY_MI2S_RX, 537 SECONDARY_MI2S_RX, 1, 1}, 538 [SECONDARY_MI2S_TX] = { AFE_PORT_ID_SECONDARY_MI2S_TX, 539 SECONDARY_MI2S_TX, 0, 1}, 540 [TERTIARY_MI2S_RX] = { AFE_PORT_ID_TERTIARY_MI2S_RX, 541 TERTIARY_MI2S_RX, 1, 1}, 542 [TERTIARY_MI2S_TX] = { AFE_PORT_ID_TERTIARY_MI2S_TX, 543 TERTIARY_MI2S_TX, 0, 1}, 544 [QUATERNARY_MI2S_RX] = { AFE_PORT_ID_QUATERNARY_MI2S_RX, 545 QUATERNARY_MI2S_RX, 1, 1}, 546 [QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX, 547 QUATERNARY_MI2S_TX, 0, 1}, 548 [PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX, 549 PRIMARY_TDM_RX_0, 1, 1}, 550 [PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX, 551 PRIMARY_TDM_TX_0, 0, 1}, 552 [PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1, 553 PRIMARY_TDM_RX_1, 1, 1}, 554 [PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1, 555 PRIMARY_TDM_TX_1, 0, 1}, 556 [PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2, 557 PRIMARY_TDM_RX_2, 1, 1}, 558 [PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2, 559 PRIMARY_TDM_TX_2, 0, 1}, 560 [PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3, 561 PRIMARY_TDM_RX_3, 1, 1}, 562 [PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3, 563 PRIMARY_TDM_TX_3, 0, 1}, 564 [PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4, 565 PRIMARY_TDM_RX_4, 1, 1}, 566 [PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4, 567 PRIMARY_TDM_TX_4, 0, 1}, 568 [PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5, 569 PRIMARY_TDM_RX_5, 1, 1}, 570 [PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5, 571 PRIMARY_TDM_TX_5, 0, 1}, 572 [PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6, 573 PRIMARY_TDM_RX_6, 1, 1}, 574 [PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6, 575 PRIMARY_TDM_TX_6, 0, 1}, 576 [PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7, 577 PRIMARY_TDM_RX_7, 1, 1}, 578 [PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7, 579 PRIMARY_TDM_TX_7, 0, 1}, 580 [SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX, 581 SECONDARY_TDM_RX_0, 1, 1}, 582 [SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX, 583 SECONDARY_TDM_TX_0, 0, 1}, 584 [SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1, 585 SECONDARY_TDM_RX_1, 1, 1}, 586 [SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1, 587 SECONDARY_TDM_TX_1, 0, 1}, 588 [SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2, 589 SECONDARY_TDM_RX_2, 1, 1}, 590 [SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2, 591 SECONDARY_TDM_TX_2, 0, 1}, 592 [SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3, 593 SECONDARY_TDM_RX_3, 1, 1}, 594 [SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3, 595 SECONDARY_TDM_TX_3, 0, 1}, 596 [SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4, 597 SECONDARY_TDM_RX_4, 1, 1}, 598 [SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4, 599 SECONDARY_TDM_TX_4, 0, 1}, 600 [SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5, 601 SECONDARY_TDM_RX_5, 1, 1}, 602 [SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5, 603 SECONDARY_TDM_TX_5, 0, 1}, 604 [SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6, 605 SECONDARY_TDM_RX_6, 1, 1}, 606 [SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6, 607 SECONDARY_TDM_TX_6, 0, 1}, 608 [SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7, 609 SECONDARY_TDM_RX_7, 1, 1}, 610 [SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7, 611 SECONDARY_TDM_TX_7, 0, 1}, 612 [TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX, 613 TERTIARY_TDM_RX_0, 1, 1}, 614 [TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX, 615 TERTIARY_TDM_TX_0, 0, 1}, 616 [TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1, 617 TERTIARY_TDM_RX_1, 1, 1}, 618 [TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1, 619 TERTIARY_TDM_TX_1, 0, 1}, 620 [TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2, 621 TERTIARY_TDM_RX_2, 1, 1}, 622 [TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2, 623 TERTIARY_TDM_TX_2, 0, 1}, 624 [TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3, 625 TERTIARY_TDM_RX_3, 1, 1}, 626 [TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3, 627 TERTIARY_TDM_TX_3, 0, 1}, 628 [TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4, 629 TERTIARY_TDM_RX_4, 1, 1}, 630 [TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4, 631 TERTIARY_TDM_TX_4, 0, 1}, 632 [TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5, 633 TERTIARY_TDM_RX_5, 1, 1}, 634 [TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5, 635 TERTIARY_TDM_TX_5, 0, 1}, 636 [TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6, 637 TERTIARY_TDM_RX_6, 1, 1}, 638 [TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6, 639 TERTIARY_TDM_TX_6, 0, 1}, 640 [TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7, 641 TERTIARY_TDM_RX_7, 1, 1}, 642 [TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7, 643 TERTIARY_TDM_TX_7, 0, 1}, 644 [QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX, 645 QUATERNARY_TDM_RX_0, 1, 1}, 646 [QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX, 647 QUATERNARY_TDM_TX_0, 0, 1}, 648 [QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1, 649 QUATERNARY_TDM_RX_1, 1, 1}, 650 [QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1, 651 QUATERNARY_TDM_TX_1, 0, 1}, 652 [QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2, 653 QUATERNARY_TDM_RX_2, 1, 1}, 654 [QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2, 655 QUATERNARY_TDM_TX_2, 0, 1}, 656 [QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3, 657 QUATERNARY_TDM_RX_3, 1, 1}, 658 [QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3, 659 QUATERNARY_TDM_TX_3, 0, 1}, 660 [QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4, 661 QUATERNARY_TDM_RX_4, 1, 1}, 662 [QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4, 663 QUATERNARY_TDM_TX_4, 0, 1}, 664 [QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5, 665 QUATERNARY_TDM_RX_5, 1, 1}, 666 [QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5, 667 QUATERNARY_TDM_TX_5, 0, 1}, 668 [QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6, 669 QUATERNARY_TDM_RX_6, 1, 1}, 670 [QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6, 671 QUATERNARY_TDM_TX_6, 0, 1}, 672 [QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7, 673 QUATERNARY_TDM_RX_7, 1, 1}, 674 [QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7, 675 QUATERNARY_TDM_TX_7, 0, 1}, 676 [QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX, 677 QUINARY_TDM_RX_0, 1, 1}, 678 [QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX, 679 QUINARY_TDM_TX_0, 0, 1}, 680 [QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1, 681 QUINARY_TDM_RX_1, 1, 1}, 682 [QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1, 683 QUINARY_TDM_TX_1, 0, 1}, 684 [QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2, 685 QUINARY_TDM_RX_2, 1, 1}, 686 [QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2, 687 QUINARY_TDM_TX_2, 0, 1}, 688 [QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3, 689 QUINARY_TDM_RX_3, 1, 1}, 690 [QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3, 691 QUINARY_TDM_TX_3, 0, 1}, 692 [QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4, 693 QUINARY_TDM_RX_4, 1, 1}, 694 [QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4, 695 QUINARY_TDM_TX_4, 0, 1}, 696 [QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5, 697 QUINARY_TDM_RX_5, 1, 1}, 698 [QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5, 699 QUINARY_TDM_TX_5, 0, 1}, 700 [QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6, 701 QUINARY_TDM_RX_6, 1, 1}, 702 [QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6, 703 QUINARY_TDM_TX_6, 0, 1}, 704 [QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7, 705 QUINARY_TDM_RX_7, 1, 1}, 706 [QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7, 707 QUINARY_TDM_TX_7, 0, 1}, 708 [DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX, 709 DISPLAY_PORT_RX, 1, 1}, 710 }; 711 712 static void q6afe_port_free(struct kref *ref) 713 { 714 struct q6afe_port *port; 715 struct q6afe *afe; 716 unsigned long flags; 717 718 port = container_of(ref, struct q6afe_port, refcount); 719 afe = port->afe; 720 spin_lock_irqsave(&afe->port_list_lock, flags); 721 list_del(&port->node); 722 spin_unlock_irqrestore(&afe->port_list_lock, flags); 723 kfree(port->scfg); 724 kfree(port); 725 } 726 727 static struct q6afe_port *q6afe_find_port(struct q6afe *afe, int token) 728 { 729 struct q6afe_port *p = NULL; 730 struct q6afe_port *ret = NULL; 731 unsigned long flags; 732 733 spin_lock_irqsave(&afe->port_list_lock, flags); 734 list_for_each_entry(p, &afe->port_list, node) 735 if (p->token == token) { 736 ret = p; 737 kref_get(&p->refcount); 738 break; 739 } 740 741 spin_unlock_irqrestore(&afe->port_list_lock, flags); 742 return ret; 743 } 744 745 static int q6afe_callback(struct apr_device *adev, struct apr_resp_pkt *data) 746 { 747 struct q6afe *afe = dev_get_drvdata(&adev->dev); 748 struct aprv2_ibasic_rsp_result_t *res; 749 struct apr_hdr *hdr = &data->hdr; 750 struct q6afe_port *port; 751 752 if (!data->payload_size) 753 return 0; 754 755 res = data->payload; 756 switch (hdr->opcode) { 757 case APR_BASIC_RSP_RESULT: { 758 if (res->status) { 759 dev_err(afe->dev, "cmd = 0x%x returned error = 0x%x\n", 760 res->opcode, res->status); 761 } 762 switch (res->opcode) { 763 case AFE_PORT_CMD_SET_PARAM_V2: 764 case AFE_PORT_CMD_DEVICE_STOP: 765 case AFE_PORT_CMD_DEVICE_START: 766 case AFE_SVC_CMD_SET_PARAM: 767 port = q6afe_find_port(afe, hdr->token); 768 if (port) { 769 port->result = *res; 770 wake_up(&port->wait); 771 kref_put(&port->refcount, q6afe_port_free); 772 } 773 break; 774 default: 775 dev_err(afe->dev, "Unknown cmd 0x%x\n", res->opcode); 776 break; 777 } 778 } 779 break; 780 default: 781 break; 782 } 783 784 return 0; 785 } 786 787 /** 788 * q6afe_get_port_id() - Get port id from a given port index 789 * 790 * @index: port index 791 * 792 * Return: Will be an negative on error or valid port_id on success 793 */ 794 int q6afe_get_port_id(int index) 795 { 796 if (index < 0 || index >= AFE_PORT_MAX) 797 return -EINVAL; 798 799 return port_maps[index].port_id; 800 } 801 EXPORT_SYMBOL_GPL(q6afe_get_port_id); 802 803 int q6afe_is_rx_port(int index) 804 { 805 if (index < 0 || index >= AFE_PORT_MAX) 806 return -EINVAL; 807 808 return port_maps[index].is_rx; 809 } 810 EXPORT_SYMBOL_GPL(q6afe_is_rx_port); 811 static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt, 812 struct q6afe_port *port) 813 { 814 wait_queue_head_t *wait = &port->wait; 815 struct apr_hdr *hdr = &pkt->hdr; 816 int ret; 817 818 mutex_lock(&afe->lock); 819 port->result.opcode = 0; 820 port->result.status = 0; 821 822 ret = apr_send_pkt(afe->apr, pkt); 823 if (ret < 0) { 824 dev_err(afe->dev, "packet not transmitted (%d)\n", ret); 825 ret = -EINVAL; 826 goto err; 827 } 828 829 ret = wait_event_timeout(*wait, (port->result.opcode == hdr->opcode), 830 msecs_to_jiffies(TIMEOUT_MS)); 831 if (!ret) { 832 ret = -ETIMEDOUT; 833 } else if (port->result.status > 0) { 834 dev_err(afe->dev, "DSP returned error[%x]\n", 835 port->result.status); 836 ret = -EINVAL; 837 } else { 838 ret = 0; 839 } 840 841 err: 842 mutex_unlock(&afe->lock); 843 844 return ret; 845 } 846 847 static int q6afe_port_set_param(struct q6afe_port *port, void *data, 848 int param_id, int module_id, int psize) 849 { 850 struct afe_svc_cmd_set_param *param; 851 struct afe_port_param_data_v2 *pdata; 852 struct q6afe *afe = port->afe; 853 struct apr_pkt *pkt; 854 u16 port_id = port->id; 855 int ret, pkt_size; 856 void *p, *pl; 857 858 pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 859 p = kzalloc(pkt_size, GFP_KERNEL); 860 if (!p) 861 return -ENOMEM; 862 863 pkt = p; 864 param = p + APR_HDR_SIZE; 865 pdata = p + APR_HDR_SIZE + sizeof(*param); 866 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 867 memcpy(pl, data, psize); 868 869 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 870 APR_HDR_LEN(APR_HDR_SIZE), 871 APR_PKT_VER); 872 pkt->hdr.pkt_size = pkt_size; 873 pkt->hdr.src_port = 0; 874 pkt->hdr.dest_port = 0; 875 pkt->hdr.token = port->token; 876 pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM; 877 878 param->payload_size = sizeof(*pdata) + psize; 879 param->payload_address_lsw = 0x00; 880 param->payload_address_msw = 0x00; 881 param->mem_map_handle = 0x00; 882 pdata->module_id = module_id; 883 pdata->param_id = param_id; 884 pdata->param_size = psize; 885 886 ret = afe_apr_send_pkt(afe, pkt, port); 887 if (ret) 888 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 889 port_id, ret); 890 891 kfree(pkt); 892 return ret; 893 } 894 895 static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data, 896 int param_id, int module_id, int psize) 897 { 898 struct afe_port_cmd_set_param_v2 *param; 899 struct afe_port_param_data_v2 *pdata; 900 struct q6afe *afe = port->afe; 901 struct apr_pkt *pkt; 902 u16 port_id = port->id; 903 int ret, pkt_size; 904 void *p, *pl; 905 906 pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 907 p = kzalloc(pkt_size, GFP_KERNEL); 908 if (!p) 909 return -ENOMEM; 910 911 pkt = p; 912 param = p + APR_HDR_SIZE; 913 pdata = p + APR_HDR_SIZE + sizeof(*param); 914 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 915 memcpy(pl, data, psize); 916 917 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 918 APR_HDR_LEN(APR_HDR_SIZE), 919 APR_PKT_VER); 920 pkt->hdr.pkt_size = pkt_size; 921 pkt->hdr.src_port = 0; 922 pkt->hdr.dest_port = 0; 923 pkt->hdr.token = port->token; 924 pkt->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; 925 926 param->port_id = port_id; 927 param->payload_size = sizeof(*pdata) + psize; 928 param->payload_address_lsw = 0x00; 929 param->payload_address_msw = 0x00; 930 param->mem_map_handle = 0x00; 931 pdata->module_id = module_id; 932 pdata->param_id = param_id; 933 pdata->param_size = psize; 934 935 ret = afe_apr_send_pkt(afe, pkt, port); 936 if (ret) 937 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 938 port_id, ret); 939 940 kfree(pkt); 941 return ret; 942 } 943 944 static int q6afe_set_lpass_clock(struct q6afe_port *port, 945 struct afe_clk_cfg *cfg) 946 { 947 return q6afe_port_set_param_v2(port, cfg, 948 AFE_PARAM_ID_LPAIF_CLK_CONFIG, 949 AFE_MODULE_AUDIO_DEV_INTERFACE, 950 sizeof(*cfg)); 951 } 952 953 static int q6afe_set_lpass_clock_v2(struct q6afe_port *port, 954 struct afe_clk_set *cfg) 955 { 956 return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET, 957 AFE_MODULE_CLOCK_SET, sizeof(*cfg)); 958 } 959 960 static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port, 961 struct afe_digital_clk_cfg *cfg) 962 { 963 return q6afe_port_set_param_v2(port, cfg, 964 AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG, 965 AFE_MODULE_AUDIO_DEV_INTERFACE, 966 sizeof(*cfg)); 967 } 968 969 int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, 970 int clk_src, int clk_root, 971 unsigned int freq, int dir) 972 { 973 struct afe_clk_cfg ccfg = {0,}; 974 struct afe_clk_set cset = {0,}; 975 struct afe_digital_clk_cfg dcfg = {0,}; 976 int ret; 977 978 switch (clk_id) { 979 case LPAIF_DIG_CLK: 980 dcfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 981 dcfg.clk_val = freq; 982 dcfg.clk_root = clk_root; 983 ret = q6afe_set_digital_codec_core_clock(port, &dcfg); 984 break; 985 case LPAIF_BIT_CLK: 986 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 987 ccfg.clk_val1 = freq; 988 ccfg.clk_src = clk_src; 989 ccfg.clk_root = clk_root; 990 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID; 991 ret = q6afe_set_lpass_clock(port, &ccfg); 992 break; 993 994 case LPAIF_OSR_CLK: 995 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 996 ccfg.clk_val2 = freq; 997 ccfg.clk_src = clk_src; 998 ccfg.clk_root = clk_root; 999 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID; 1000 ret = q6afe_set_lpass_clock(port, &ccfg); 1001 break; 1002 case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR: 1003 case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1: 1004 case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT: 1005 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1006 cset.clk_id = clk_id; 1007 cset.clk_freq_in_hz = freq; 1008 cset.clk_attri = clk_src; 1009 cset.clk_root = clk_root; 1010 cset.enable = !!freq; 1011 ret = q6afe_set_lpass_clock_v2(port, &cset); 1012 break; 1013 default: 1014 ret = -EINVAL; 1015 break; 1016 } 1017 1018 return ret; 1019 } 1020 EXPORT_SYMBOL_GPL(q6afe_port_set_sysclk); 1021 1022 /** 1023 * q6afe_port_stop() - Stop a afe port 1024 * 1025 * @port: Instance of port to stop 1026 * 1027 * Return: Will be an negative on packet size on success. 1028 */ 1029 int q6afe_port_stop(struct q6afe_port *port) 1030 { 1031 struct afe_port_cmd_device_stop *stop; 1032 struct q6afe *afe = port->afe; 1033 struct apr_pkt *pkt; 1034 int port_id = port->id; 1035 int ret = 0; 1036 int index, pkt_size; 1037 void *p; 1038 1039 port_id = port->id; 1040 index = port->token; 1041 if (index < 0 || index >= AFE_PORT_MAX) { 1042 dev_err(afe->dev, "AFE port index[%d] invalid!\n", index); 1043 return -EINVAL; 1044 } 1045 1046 pkt_size = APR_HDR_SIZE + sizeof(*stop); 1047 p = kzalloc(pkt_size, GFP_KERNEL); 1048 if (!p) 1049 return -ENOMEM; 1050 1051 pkt = p; 1052 stop = p + APR_HDR_SIZE; 1053 1054 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1055 APR_HDR_LEN(APR_HDR_SIZE), 1056 APR_PKT_VER); 1057 pkt->hdr.pkt_size = pkt_size; 1058 pkt->hdr.src_port = 0; 1059 pkt->hdr.dest_port = 0; 1060 pkt->hdr.token = index; 1061 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_STOP; 1062 stop->port_id = port_id; 1063 stop->reserved = 0; 1064 1065 ret = afe_apr_send_pkt(afe, pkt, port); 1066 if (ret) 1067 dev_err(afe->dev, "AFE close failed %d\n", ret); 1068 1069 kfree(pkt); 1070 return ret; 1071 } 1072 EXPORT_SYMBOL_GPL(q6afe_port_stop); 1073 1074 /** 1075 * q6afe_slim_port_prepare() - Prepare slim afe port. 1076 * 1077 * @port: Instance of afe port 1078 * @cfg: SLIM configuration for the afe port 1079 * 1080 */ 1081 void q6afe_slim_port_prepare(struct q6afe_port *port, 1082 struct q6afe_slim_cfg *cfg) 1083 { 1084 union afe_port_config *pcfg = &port->port_cfg; 1085 1086 pcfg->slim_cfg.sb_cfg_minor_version = AFE_API_VERSION_SLIMBUS_CONFIG; 1087 pcfg->slim_cfg.sample_rate = cfg->sample_rate; 1088 pcfg->slim_cfg.bit_width = cfg->bit_width; 1089 pcfg->slim_cfg.num_channels = cfg->num_channels; 1090 pcfg->slim_cfg.data_format = cfg->data_format; 1091 pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0]; 1092 pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1]; 1093 pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2]; 1094 pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3]; 1095 1096 } 1097 EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare); 1098 1099 /** 1100 * q6afe_tdm_port_prepare() - Prepare tdm afe port. 1101 * 1102 * @port: Instance of afe port 1103 * @cfg: TDM configuration for the afe port 1104 * 1105 */ 1106 void q6afe_tdm_port_prepare(struct q6afe_port *port, 1107 struct q6afe_tdm_cfg *cfg) 1108 { 1109 union afe_port_config *pcfg = &port->port_cfg; 1110 1111 pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG; 1112 pcfg->tdm_cfg.num_channels = cfg->num_channels; 1113 pcfg->tdm_cfg.sample_rate = cfg->sample_rate; 1114 pcfg->tdm_cfg.bit_width = cfg->bit_width; 1115 pcfg->tdm_cfg.data_format = cfg->data_format; 1116 pcfg->tdm_cfg.sync_mode = cfg->sync_mode; 1117 pcfg->tdm_cfg.sync_src = cfg->sync_src; 1118 pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame; 1119 1120 pcfg->tdm_cfg.slot_width = cfg->slot_width; 1121 pcfg->tdm_cfg.slot_mask = cfg->slot_mask; 1122 port->scfg = kzalloc(sizeof(*port->scfg), GFP_KERNEL); 1123 if (!port->scfg) 1124 return; 1125 1126 port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG; 1127 port->scfg->num_channels = cfg->num_channels; 1128 port->scfg->bitwidth = cfg->bit_width; 1129 port->scfg->data_align_type = cfg->data_align_type; 1130 memcpy(port->scfg->ch_mapping, cfg->ch_mapping, 1131 sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT); 1132 } 1133 EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare); 1134 1135 /** 1136 * q6afe_hdmi_port_prepare() - Prepare hdmi afe port. 1137 * 1138 * @port: Instance of afe port 1139 * @cfg: HDMI configuration for the afe port 1140 * 1141 */ 1142 void q6afe_hdmi_port_prepare(struct q6afe_port *port, 1143 struct q6afe_hdmi_cfg *cfg) 1144 { 1145 union afe_port_config *pcfg = &port->port_cfg; 1146 1147 pcfg->hdmi_multi_ch.hdmi_cfg_minor_version = 1148 AFE_API_VERSION_HDMI_CONFIG; 1149 pcfg->hdmi_multi_ch.datatype = cfg->datatype; 1150 pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation; 1151 pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate; 1152 pcfg->hdmi_multi_ch.bit_width = cfg->bit_width; 1153 } 1154 EXPORT_SYMBOL_GPL(q6afe_hdmi_port_prepare); 1155 1156 /** 1157 * q6afe_i2s_port_prepare() - Prepare i2s afe port. 1158 * 1159 * @port: Instance of afe port 1160 * @cfg: I2S configuration for the afe port 1161 * Return: Will be an negative on error and zero on success. 1162 */ 1163 int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg) 1164 { 1165 union afe_port_config *pcfg = &port->port_cfg; 1166 struct device *dev = port->afe->dev; 1167 int num_sd_lines; 1168 1169 pcfg->i2s_cfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1170 pcfg->i2s_cfg.sample_rate = cfg->sample_rate; 1171 pcfg->i2s_cfg.bit_width = cfg->bit_width; 1172 pcfg->i2s_cfg.data_format = AFE_LINEAR_PCM_DATA; 1173 1174 switch (cfg->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1175 case SND_SOC_DAIFMT_CBS_CFS: 1176 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL; 1177 break; 1178 case SND_SOC_DAIFMT_CBM_CFM: 1179 /* CPU is slave */ 1180 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL; 1181 break; 1182 default: 1183 break; 1184 } 1185 1186 num_sd_lines = hweight_long(cfg->sd_line_mask); 1187 1188 switch (num_sd_lines) { 1189 case 0: 1190 dev_err(dev, "no line is assigned\n"); 1191 return -EINVAL; 1192 case 1: 1193 switch (cfg->sd_line_mask) { 1194 case AFE_PORT_I2S_SD0_MASK: 1195 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1196 break; 1197 case AFE_PORT_I2S_SD1_MASK: 1198 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD1; 1199 break; 1200 case AFE_PORT_I2S_SD2_MASK: 1201 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1202 break; 1203 case AFE_PORT_I2S_SD3_MASK: 1204 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD3; 1205 break; 1206 default: 1207 dev_err(dev, "Invalid SD lines\n"); 1208 return -EINVAL; 1209 } 1210 break; 1211 case 2: 1212 switch (cfg->sd_line_mask) { 1213 case AFE_PORT_I2S_SD0_1_MASK: 1214 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD01; 1215 break; 1216 case AFE_PORT_I2S_SD2_3_MASK: 1217 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD23; 1218 break; 1219 default: 1220 dev_err(dev, "Invalid SD lines\n"); 1221 return -EINVAL; 1222 } 1223 break; 1224 case 3: 1225 switch (cfg->sd_line_mask) { 1226 case AFE_PORT_I2S_SD0_1_2_MASK: 1227 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_6CHS; 1228 break; 1229 default: 1230 dev_err(dev, "Invalid SD lines\n"); 1231 return -EINVAL; 1232 } 1233 break; 1234 case 4: 1235 switch (cfg->sd_line_mask) { 1236 case AFE_PORT_I2S_SD0_1_2_3_MASK: 1237 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_8CHS; 1238 1239 break; 1240 default: 1241 dev_err(dev, "Invalid SD lines\n"); 1242 return -EINVAL; 1243 } 1244 break; 1245 default: 1246 dev_err(dev, "Invalid SD lines\n"); 1247 return -EINVAL; 1248 } 1249 1250 switch (cfg->num_channels) { 1251 case 1: 1252 case 2: 1253 switch (pcfg->i2s_cfg.channel_mode) { 1254 case AFE_PORT_I2S_QUAD01: 1255 case AFE_PORT_I2S_6CHS: 1256 case AFE_PORT_I2S_8CHS: 1257 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1258 break; 1259 case AFE_PORT_I2S_QUAD23: 1260 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1261 break; 1262 } 1263 1264 if (cfg->num_channels == 2) 1265 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_STEREO; 1266 else 1267 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_MONO; 1268 1269 break; 1270 case 3: 1271 case 4: 1272 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_QUAD01) { 1273 dev_err(dev, "Invalid Channel mode\n"); 1274 return -EINVAL; 1275 } 1276 break; 1277 case 5: 1278 case 6: 1279 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_6CHS) { 1280 dev_err(dev, "Invalid Channel mode\n"); 1281 return -EINVAL; 1282 } 1283 break; 1284 case 7: 1285 case 8: 1286 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_8CHS) { 1287 dev_err(dev, "Invalid Channel mode\n"); 1288 return -EINVAL; 1289 } 1290 break; 1291 default: 1292 break; 1293 } 1294 1295 return 0; 1296 } 1297 EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare); 1298 1299 /** 1300 * q6afe_port_start() - Start a afe port 1301 * 1302 * @port: Instance of port to start 1303 * 1304 * Return: Will be an negative on packet size on success. 1305 */ 1306 int q6afe_port_start(struct q6afe_port *port) 1307 { 1308 struct afe_port_cmd_device_start *start; 1309 struct q6afe *afe = port->afe; 1310 int port_id = port->id; 1311 int ret, param_id = port->cfg_type; 1312 struct apr_pkt *pkt; 1313 int pkt_size; 1314 void *p; 1315 1316 ret = q6afe_port_set_param_v2(port, &port->port_cfg, param_id, 1317 AFE_MODULE_AUDIO_DEV_INTERFACE, 1318 sizeof(port->port_cfg)); 1319 if (ret) { 1320 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1321 port_id, ret); 1322 return ret; 1323 } 1324 1325 if (port->scfg) { 1326 ret = q6afe_port_set_param_v2(port, port->scfg, 1327 AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG, 1328 AFE_MODULE_TDM, sizeof(*port->scfg)); 1329 if (ret) { 1330 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1331 port_id, ret); 1332 return ret; 1333 } 1334 } 1335 1336 pkt_size = APR_HDR_SIZE + sizeof(*start); 1337 p = kzalloc(pkt_size, GFP_KERNEL); 1338 if (!p) 1339 return -ENOMEM; 1340 1341 pkt = p; 1342 start = p + APR_HDR_SIZE; 1343 1344 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1345 APR_HDR_LEN(APR_HDR_SIZE), 1346 APR_PKT_VER); 1347 pkt->hdr.pkt_size = pkt_size; 1348 pkt->hdr.src_port = 0; 1349 pkt->hdr.dest_port = 0; 1350 pkt->hdr.token = port->token; 1351 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_START; 1352 1353 start->port_id = port_id; 1354 1355 ret = afe_apr_send_pkt(afe, pkt, port); 1356 if (ret) 1357 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1358 port_id, ret); 1359 1360 kfree(pkt); 1361 return ret; 1362 } 1363 EXPORT_SYMBOL_GPL(q6afe_port_start); 1364 1365 /** 1366 * q6afe_port_get_from_id() - Get port instance from a port id 1367 * 1368 * @dev: Pointer to afe child device. 1369 * @id: port id 1370 * 1371 * Return: Will be an error pointer on error or a valid afe port 1372 * on success. 1373 */ 1374 struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) 1375 { 1376 int port_id; 1377 struct q6afe *afe = dev_get_drvdata(dev->parent); 1378 struct q6afe_port *port; 1379 unsigned long flags; 1380 int cfg_type; 1381 1382 if (id < 0 || id >= AFE_PORT_MAX) { 1383 dev_err(dev, "AFE port token[%d] invalid!\n", id); 1384 return ERR_PTR(-EINVAL); 1385 } 1386 1387 /* if port is multiple times bind/unbind before callback finishes */ 1388 port = q6afe_find_port(afe, id); 1389 if (port) { 1390 dev_err(dev, "AFE Port already open\n"); 1391 return port; 1392 } 1393 1394 port_id = port_maps[id].port_id; 1395 1396 switch (port_id) { 1397 case AFE_PORT_ID_MULTICHAN_HDMI_RX: 1398 case AFE_PORT_ID_HDMI_OVER_DP_RX: 1399 cfg_type = AFE_PARAM_ID_HDMI_CONFIG; 1400 break; 1401 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX: 1402 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX: 1403 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX: 1404 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX: 1405 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX: 1406 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX: 1407 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX: 1408 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX: 1409 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX: 1410 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX: 1411 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX: 1412 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX: 1413 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX: 1414 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX: 1415 cfg_type = AFE_PARAM_ID_SLIMBUS_CONFIG; 1416 break; 1417 1418 case AFE_PORT_ID_PRIMARY_MI2S_RX: 1419 case AFE_PORT_ID_PRIMARY_MI2S_TX: 1420 case AFE_PORT_ID_SECONDARY_MI2S_RX: 1421 case AFE_PORT_ID_SECONDARY_MI2S_TX: 1422 case AFE_PORT_ID_TERTIARY_MI2S_RX: 1423 case AFE_PORT_ID_TERTIARY_MI2S_TX: 1424 case AFE_PORT_ID_QUATERNARY_MI2S_RX: 1425 case AFE_PORT_ID_QUATERNARY_MI2S_TX: 1426 cfg_type = AFE_PARAM_ID_I2S_CONFIG; 1427 break; 1428 case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: 1429 cfg_type = AFE_PARAM_ID_TDM_CONFIG; 1430 break; 1431 1432 default: 1433 dev_err(dev, "Invalid port id 0x%x\n", port_id); 1434 return ERR_PTR(-EINVAL); 1435 } 1436 1437 port = kzalloc(sizeof(*port), GFP_KERNEL); 1438 if (!port) 1439 return ERR_PTR(-ENOMEM); 1440 1441 init_waitqueue_head(&port->wait); 1442 1443 port->token = id; 1444 port->id = port_id; 1445 port->afe = afe; 1446 port->cfg_type = cfg_type; 1447 kref_init(&port->refcount); 1448 1449 spin_lock_irqsave(&afe->port_list_lock, flags); 1450 list_add_tail(&port->node, &afe->port_list); 1451 spin_unlock_irqrestore(&afe->port_list_lock, flags); 1452 1453 return port; 1454 1455 } 1456 EXPORT_SYMBOL_GPL(q6afe_port_get_from_id); 1457 1458 /** 1459 * q6afe_port_put() - Release port reference 1460 * 1461 * @port: Instance of port to put 1462 */ 1463 void q6afe_port_put(struct q6afe_port *port) 1464 { 1465 kref_put(&port->refcount, q6afe_port_free); 1466 } 1467 EXPORT_SYMBOL_GPL(q6afe_port_put); 1468 1469 static int q6afe_probe(struct apr_device *adev) 1470 { 1471 struct q6afe *afe; 1472 struct device *dev = &adev->dev; 1473 1474 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 1475 if (!afe) 1476 return -ENOMEM; 1477 1478 q6core_get_svc_api_info(adev->svc_id, &afe->ainfo); 1479 afe->apr = adev; 1480 mutex_init(&afe->lock); 1481 afe->dev = dev; 1482 INIT_LIST_HEAD(&afe->port_list); 1483 spin_lock_init(&afe->port_list_lock); 1484 1485 dev_set_drvdata(dev, afe); 1486 1487 return of_platform_populate(dev->of_node, NULL, NULL, dev); 1488 } 1489 1490 static int q6afe_remove(struct apr_device *adev) 1491 { 1492 of_platform_depopulate(&adev->dev); 1493 1494 return 0; 1495 } 1496 1497 static const struct of_device_id q6afe_device_id[] = { 1498 { .compatible = "qcom,q6afe" }, 1499 {}, 1500 }; 1501 MODULE_DEVICE_TABLE(of, q6afe_device_id); 1502 1503 static struct apr_driver qcom_q6afe_driver = { 1504 .probe = q6afe_probe, 1505 .remove = q6afe_remove, 1506 .callback = q6afe_callback, 1507 .driver = { 1508 .name = "qcom-q6afe", 1509 .of_match_table = of_match_ptr(q6afe_device_id), 1510 1511 }, 1512 }; 1513 1514 module_apr_driver(qcom_q6afe_driver); 1515 MODULE_DESCRIPTION("Q6 Audio Front End"); 1516 MODULE_LICENSE("GPL v2"); 1517