1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __AUDIOREACH_H__ 4 #define __AUDIOREACH_H__ 5 #include <linux/types.h> 6 #include <linux/soc/qcom/apr.h> 7 #include <sound/soc.h> 8 struct q6apm; 9 struct q6apm_graph; 10 11 /* Module IDs */ 12 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 13 #define MODULE_ID_RD_SHARED_MEM_EP 0x07001001 14 #define MODULE_ID_GAIN 0x07001002 15 #define MODULE_ID_PCM_CNV 0x07001003 16 #define MODULE_ID_PCM_ENC 0x07001004 17 #define MODULE_ID_PCM_DEC 0x07001005 18 #define MODULE_ID_SAL 0x07001010 19 #define MODULE_ID_MFC 0x07001015 20 #define MODULE_ID_CODEC_DMA_SINK 0x07001023 21 #define MODULE_ID_CODEC_DMA_SOURCE 0x07001024 22 #define MODULE_ID_I2S_SINK 0x0700100A 23 #define MODULE_ID_I2S_SOURCE 0x0700100B 24 #define MODULE_ID_DATA_LOGGING 0x0700101A 25 #define MODULE_ID_DISPLAY_PORT_SINK 0x07001069 26 27 #define APM_CMD_GET_SPF_STATE 0x01001021 28 #define APM_CMD_RSP_GET_SPF_STATE 0x02001007 29 30 #define APM_MODULE_INSTANCE_ID 0x00000001 31 #define PRM_MODULE_INSTANCE_ID 0x00000002 32 #define AMDB_MODULE_INSTANCE_ID 0x00000003 33 #define VCPM_MODULE_INSTANCE_ID 0x00000004 34 #define AR_MODULE_INSTANCE_ID_START 0x00006000 35 #define AR_MODULE_INSTANCE_ID_END 0x00007000 36 #define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000 37 #define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000 38 #define AR_CONT_INSTANCE_ID_START 0x00005000 39 #define AR_CONT_INSTANCE_ID_END 0x00006000 40 #define AR_SG_INSTANCE_ID_START 0x00004000 41 42 #define APM_CMD_GRAPH_OPEN 0x01001000 43 #define APM_CMD_GRAPH_PREPARE 0x01001001 44 #define APM_CMD_GRAPH_START 0x01001002 45 #define APM_CMD_GRAPH_STOP 0x01001003 46 #define APM_CMD_GRAPH_CLOSE 0x01001004 47 #define APM_CMD_GRAPH_FLUSH 0x01001005 48 #define APM_CMD_SET_CFG 0x01001006 49 #define APM_CMD_GET_CFG 0x01001007 50 #define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C 51 #define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D 52 #define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001 53 #define APM_CMD_RSP_GET_CFG 0x02001000 54 #define APM_CMD_CLOSE_ALL 0x01001013 55 #define APM_CMD_REGISTER_SHARED_CFG 0x0100100A 56 57 #define APM_MEMORY_MAP_SHMEM8_4K_POOL 3 58 59 struct apm_cmd_shared_mem_map_regions { 60 uint16_t mem_pool_id; 61 uint16_t num_regions; 62 uint32_t property_flag; 63 } __packed; 64 65 struct apm_shared_map_region_payload { 66 uint32_t shm_addr_lsw; 67 uint32_t shm_addr_msw; 68 uint32_t mem_size_bytes; 69 } __packed; 70 71 struct apm_cmd_shared_mem_unmap_regions { 72 uint32_t mem_map_handle; 73 } __packed; 74 75 struct apm_cmd_rsp_shared_mem_map_regions { 76 uint32_t mem_map_handle; 77 } __packed; 78 79 /* APM module */ 80 #define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005 81 82 #define APM_PARAM_ID_MODULE_LIST 0x08001002 83 84 struct apm_param_id_modules_list { 85 uint32_t num_modules_list; 86 } __packed; 87 88 #define APM_PARAM_ID_MODULE_PROP 0x08001003 89 90 struct apm_param_id_module_prop { 91 uint32_t num_modules_prop_cfg; 92 } __packed; 93 94 struct apm_module_prop_cfg { 95 uint32_t instance_id; 96 uint32_t num_props; 97 } __packed; 98 99 #define APM_PARAM_ID_MODULE_CONN 0x08001004 100 101 struct apm_param_id_module_conn { 102 uint32_t num_connections; 103 } __packed; 104 105 struct apm_module_conn_obj { 106 uint32_t src_mod_inst_id; 107 uint32_t src_mod_op_port_id; 108 uint32_t dst_mod_inst_id; 109 uint32_t dst_mod_ip_port_id; 110 } __packed; 111 112 #define APM_PARAM_ID_GAIN 0x08001006 113 114 struct param_id_gain_cfg { 115 uint16_t gain; 116 uint16_t reserved; 117 } __packed; 118 119 #define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008 120 121 struct param_id_pcm_output_format_cfg { 122 uint32_t data_format; 123 uint32_t fmt_id; 124 uint32_t payload_size; 125 } __packed; 126 127 struct payload_pcm_output_format_cfg { 128 uint16_t bit_width; 129 uint16_t alignment; 130 uint16_t bits_per_sample; 131 uint16_t q_factor; 132 uint16_t endianness; 133 uint16_t interleaved; 134 uint16_t reserved; 135 uint16_t num_channels; 136 uint8_t channel_mapping[]; 137 } __packed; 138 139 #define PARAM_ID_ENC_BITRATE 0x08001052 140 141 struct param_id_enc_bitrate_param { 142 uint32_t bitrate; 143 } __packed; 144 145 #define DATA_FORMAT_FIXED_POINT 1 146 #define PCM_LSB_ALIGNED 1 147 #define PCM_MSB_ALIGNED 2 148 #define PCM_LITTLE_ENDIAN 1 149 #define PCM_BIT_ENDIAN 2 150 151 #define MEDIA_FMT_ID_PCM 0x09001000 152 #define PCM_CHANNEL_L 1 153 #define PCM_CHANNEL_R 2 154 #define SAMPLE_RATE_48K 48000 155 #define BIT_WIDTH_16 16 156 157 #define APM_PARAM_ID_PROP_PORT_INFO 0x08001015 158 159 struct apm_modules_prop_info { 160 uint32_t max_ip_port; 161 uint32_t max_op_port; 162 } __packed; 163 164 /* Shared memory module */ 165 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000 166 #define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31) 167 #define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30) 168 #define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29) 169 #define WR_SH_MEM_EP_EOF_FLAG BIT(4) 170 171 struct apm_data_cmd_wr_sh_mem_ep_data_buffer { 172 uint32_t buf_addr_lsw; 173 uint32_t buf_addr_msw; 174 uint32_t mem_map_handle; 175 uint32_t buf_size; 176 uint32_t timestamp_lsw; 177 uint32_t timestamp_msw; 178 uint32_t flags; 179 } __packed; 180 181 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A 182 183 struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 { 184 uint32_t buf_addr_lsw; 185 uint32_t buf_addr_msw; 186 uint32_t mem_map_handle; 187 uint32_t buf_size; 188 uint32_t timestamp_lsw; 189 uint32_t timestamp_msw; 190 uint32_t flags; 191 uint32_t md_addr_lsw; 192 uint32_t md_addr_msw; 193 uint32_t md_map_handle; 194 uint32_t md_buf_size; 195 } __packed; 196 197 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000 198 199 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done { 200 uint32_t buf_addr_lsw; 201 uint32_t buf_addr_msw; 202 uint32_t mem_map_handle; 203 uint32_t status; 204 205 } __packed; 206 207 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004 208 209 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 { 210 uint32_t buf_addr_lsw; 211 uint32_t buf_addr_msw; 212 uint32_t mem_map_handle; 213 uint32_t status; 214 uint32_t md_buf_addr_lsw; 215 uint32_t md_buf_addr_msw; 216 uint32_t md_mem_map_handle; 217 uint32_t md_status; 218 } __packed; 219 220 #define PARAM_ID_MEDIA_FORMAT 0x0800100C 221 #define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001 222 223 struct apm_media_format { 224 uint32_t data_format; 225 uint32_t fmt_id; 226 uint32_t payload_size; 227 } __packed; 228 229 #define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002 230 #define WR_SH_MEM_EP_EOS_POLICY_LAST 1 231 #define WR_SH_MEM_EP_EOS_POLICY_EACH 2 232 233 struct data_cmd_wr_sh_mem_ep_eos { 234 uint32_t policy; 235 236 } __packed; 237 238 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003 239 240 struct data_cmd_rd_sh_mem_ep_data_buffer { 241 uint32_t buf_addr_lsw; 242 uint32_t buf_addr_msw; 243 uint32_t mem_map_handle; 244 uint32_t buf_size; 245 } __packed; 246 247 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002 248 249 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done { 250 uint32_t status; 251 uint32_t buf_addr_lsw; 252 uint32_t buf_addr_msw; 253 uint32_t mem_map_handle; 254 uint32_t data_size; 255 uint32_t offset; 256 uint32_t timestamp_lsw; 257 uint32_t timestamp_msw; 258 uint32_t flags; 259 uint32_t num_frames; 260 } __packed; 261 262 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B 263 264 struct data_cmd_rd_sh_mem_ep_data_buffer_v2 { 265 uint32_t buf_addr_lsw; 266 uint32_t buf_addr_msw; 267 uint32_t mem_map_handle; 268 uint32_t buf_size; 269 uint32_t md_buf_addr_lsw; 270 uint32_t md_buf_addr_msw; 271 uint32_t md_mem_map_handle; 272 uint32_t md_buf_size; 273 } __packed; 274 275 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005 276 277 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 { 278 uint32_t status; 279 uint32_t buf_addr_lsw; 280 uint32_t buf_addr_msw; 281 uint32_t mem_map_handle; 282 uint32_t data_size; 283 uint32_t offset; 284 uint32_t timestamp_lsw; 285 uint32_t timestamp_msw; 286 uint32_t flags; 287 uint32_t num_frames; 288 uint32_t md_status; 289 uint32_t md_buf_addr_lsw; 290 uint32_t md_buf_addr_msw; 291 uint32_t md_mem_map_handle; 292 uint32_t md_size; 293 } __packed; 294 295 #define PARAM_ID_RD_SH_MEM_CFG 0x08001007 296 297 struct param_id_rd_sh_mem_cfg { 298 uint32_t num_frames_per_buffer; 299 uint32_t metadata_control_flags; 300 301 } __packed; 302 303 #define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001 304 305 struct data_cmd_wr_sh_mem_ep_eos_rendered { 306 uint32_t module_instance_id; 307 uint32_t render_status; 308 } __packed; 309 310 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 311 312 struct apm_cmd_header { 313 uint32_t payload_address_lsw; 314 uint32_t payload_address_msw; 315 uint32_t mem_map_handle; 316 uint32_t payload_size; 317 } __packed; 318 319 #define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header) 320 321 struct apm_module_param_data { 322 uint32_t module_instance_id; 323 uint32_t param_id; 324 uint32_t param_size; 325 uint32_t error_code; 326 } __packed; 327 328 #define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data) 329 330 struct apm_module_param_shared_data { 331 uint32_t param_id; 332 uint32_t param_size; 333 } __packed; 334 335 struct apm_prop_data { 336 uint32_t prop_id; 337 uint32_t prop_size; 338 } __packed; 339 340 /* Sub-Graph Properties */ 341 #define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001 342 343 struct apm_param_id_sub_graph_cfg { 344 uint32_t num_sub_graphs; 345 } __packed; 346 347 struct apm_sub_graph_cfg { 348 uint32_t sub_graph_id; 349 uint32_t num_sub_graph_prop; 350 } __packed; 351 352 #define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E 353 354 struct apm_sg_prop_id_perf_mode { 355 uint32_t perf_mode; 356 } __packed; 357 358 #define APM_SG_PROP_ID_PERF_MODE_SIZE 4 359 360 #define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F 361 362 struct apm_sg_prop_id_direction { 363 uint32_t direction; 364 } __packed; 365 366 #define APM_SG_PROP_ID_DIR_SIZE 4 367 368 #define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010 369 #define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1 370 #define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2 371 #define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3 372 373 struct apm_sg_prop_id_scenario_id { 374 uint32_t scenario_id; 375 } __packed; 376 377 #define APM_SG_PROP_ID_SID_SIZE 4 378 /* container api */ 379 #define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000 380 381 struct apm_param_id_container_cfg { 382 uint32_t num_containers; 383 } __packed; 384 385 struct apm_container_cfg { 386 uint32_t container_id; 387 uint32_t num_prop; 388 } __packed; 389 390 struct apm_cont_capability { 391 uint32_t capability_id; 392 } __packed; 393 394 #define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011 395 #define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8 396 397 #define APM_PROP_ID_INVALID 0x0 398 #define APM_CONTAINER_CAP_ID_PP 0x1 399 #define APM_CONTAINER_CAP_ID_PP 0x1 400 401 struct apm_cont_prop_id_cap_list { 402 uint32_t num_capability_id; 403 } __packed; 404 405 #define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012 406 407 struct apm_cont_prop_id_graph_pos { 408 uint32_t graph_pos; 409 } __packed; 410 411 #define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013 412 413 struct apm_cont_prop_id_stack_size { 414 uint32_t stack_size; 415 } __packed; 416 417 #define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014 418 419 struct apm_cont_prop_id_domain { 420 uint32_t proc_domain; 421 } __packed; 422 423 #define CONFIG_I2S_WS_SRC_EXTERNAL 0x0 424 #define CONFIG_I2S_WS_SRC_INTERNAL 0x1 425 426 #define PARAM_ID_I2S_INTF_CFG 0x08001019 427 struct param_id_i2s_intf_cfg { 428 uint32_t lpaif_type; 429 uint32_t intf_idx; 430 uint16_t sd_line_idx; 431 uint16_t ws_src; 432 } __packed; 433 434 #define I2S_INTF_TYPE_PRIMARY 0 435 #define I2S_INTF_TYPE_SECOINDARY 1 436 #define I2S_INTF_TYPE_TERTINARY 2 437 #define I2S_INTF_TYPE_QUATERNARY 3 438 #define I2S_INTF_TYPE_QUINARY 4 439 #define I2S_SD0 1 440 #define I2S_SD1 2 441 #define I2S_SD2 3 442 #define I2S_SD3 4 443 444 #define PORT_ID_I2S_INPUT 2 445 #define PORT_ID_I2S_OUPUT 1 446 #define I2S_STACK_SIZE 2048 447 448 #define PARAM_ID_DISPLAY_PORT_INTF_CFG 0x08001154 449 450 struct param_id_display_port_intf_cfg { 451 uint32_t channel_allocation; 452 /* Multi-Steam Transport index */ 453 uint32_t mst_idx; 454 uint32_t dptx_idx; 455 } __packed; 456 457 #define PARAM_ID_HW_EP_MF_CFG 0x08001017 458 struct param_id_hw_ep_mf { 459 uint32_t sample_rate; 460 uint16_t bit_width; 461 uint16_t num_channels; 462 uint32_t data_format; 463 } __packed; 464 465 #define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018 466 467 struct param_id_fram_size_factor { 468 uint32_t frame_size_factor; 469 } __packed; 470 471 #define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB 472 473 struct apm_cont_prop_id_parent_container { 474 uint32_t parent_container_id; 475 } __packed; 476 477 #define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174 478 #define APM_CONT_HEAP_DEFAULT 0x1 479 #define APM_CONT_HEAP_LOW_POWER 0x2 480 481 struct apm_cont_prop_id_headp_id { 482 uint32_t heap_id; 483 } __packed; 484 485 struct apm_modules_list { 486 uint32_t sub_graph_id; 487 uint32_t container_id; 488 uint32_t num_modules; 489 } __packed; 490 491 struct apm_module_obj { 492 uint32_t module_id; 493 uint32_t instance_id; 494 } __packed; 495 496 #define APM_MODULE_PROP_ID_PORT_INFO 0x08001015 497 #define APM_MODULE_PROP_ID_PORT_INFO_SZ 8 498 struct apm_module_prop_id_port_info { 499 uint32_t max_ip_port; 500 uint32_t max_op_port; 501 } __packed; 502 503 #define DATA_LOGGING_MAX_INPUT_PORTS 0x1 504 #define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1 505 #define DATA_LOGGING_STACK_SIZE 2048 506 #define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031 507 508 struct data_logging_config { 509 uint32_t log_code; 510 uint32_t log_tap_point_id; 511 uint32_t mode; 512 } __packed; 513 514 #define PARAM_ID_SAL_OUTPUT_CFG 0x08001016 515 struct param_id_sal_output_config { 516 uint32_t bits_per_sample; 517 } __packed; 518 519 #define PARAM_ID_SAL_LIMITER_ENABLE 0x0800101E 520 struct param_id_sal_limiter_enable { 521 uint32_t enable_lim; 522 } __packed; 523 524 #define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024 525 526 struct param_id_mfc_media_format { 527 uint32_t sample_rate; 528 uint16_t bit_width; 529 uint16_t num_channels; 530 uint16_t channel_mapping[]; 531 } __packed; 532 533 struct media_format { 534 uint32_t data_format; 535 uint32_t fmt_id; 536 uint32_t payload_size; 537 } __packed; 538 539 struct payload_media_fmt_pcm { 540 uint32_t sample_rate; 541 uint16_t bit_width; 542 uint16_t alignment; 543 uint16_t bits_per_sample; 544 uint16_t q_factor; 545 uint16_t endianness; 546 uint16_t num_channels; 547 uint8_t channel_mapping[]; 548 } __packed; 549 550 #define PARAM_ID_MODULE_ENABLE 0x08001026 551 struct param_id_module_enable { 552 uint32_t enable; 553 } __packed; 554 555 #define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063 556 557 struct param_id_codec_dma_intf_cfg { 558 /* 1 - RXTX 559 * 2 - WSA 560 * 3 - VA 561 * 4 - AXI 562 */ 563 uint32_t lpaif_type; 564 /* 565 * RX0 | TX0 = 1 566 * RX1 | TX1 = 2 567 * RX2 | TX2 = 3... so on 568 */ 569 uint32_t intf_index; 570 uint32_t active_channels_mask; 571 } __packed; 572 573 struct audio_hw_clk_cfg { 574 uint32_t clock_id; 575 uint32_t clock_freq; 576 uint32_t clock_attri; 577 uint32_t clock_root; 578 } __packed; 579 580 struct audio_hw_clk_rel_cfg { 581 uint32_t clock_id; 582 } __packed; 583 584 #define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176 585 #define AR_HW_EP_POWER_MODE_0 0 /* default */ 586 #define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */ 587 #define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */ 588 589 struct param_id_hw_ep_power_mode_cfg { 590 uint32_t power_mode; 591 } __packed; 592 593 #define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233 594 #define AR_HW_EP_DMA_DATA_ALIGN_MSB 0 595 #define AR_HW_EP_DMA_DATA_ALIGN_LSB 1 596 #define AR_PCM_MAX_NUM_CHANNEL 8 597 598 struct param_id_hw_ep_dma_data_align { 599 uint32_t dma_data_align; 600 } __packed; 601 602 #define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035 603 #define VOL_CTRL_DEFAULT_GAIN 0x2000 604 605 struct param_id_vol_ctrl_master_gain { 606 uint16_t master_gain; 607 uint16_t reserved; 608 } __packed; 609 610 611 /* Graph */ 612 struct audioreach_connection { 613 /* Connections */ 614 uint32_t src_mod_inst_id; 615 uint32_t src_mod_op_port_id; 616 uint32_t dst_mod_inst_id; 617 uint32_t dst_mod_ip_port_id; 618 struct list_head node; 619 }; 620 621 struct audioreach_graph_info { 622 int id; 623 uint32_t num_sub_graphs; 624 struct list_head sg_list; 625 /* DPCM connection from FE Graph to BE graph */ 626 uint32_t src_mod_inst_id; 627 uint32_t src_mod_op_port_id; 628 uint32_t dst_mod_inst_id; 629 uint32_t dst_mod_ip_port_id; 630 }; 631 632 struct audioreach_sub_graph { 633 uint32_t sub_graph_id; 634 uint32_t perf_mode; 635 uint32_t direction; 636 uint32_t scenario_id; 637 struct list_head node; 638 639 struct audioreach_graph_info *info; 640 uint32_t num_containers; 641 struct list_head container_list; 642 }; 643 644 struct audioreach_container { 645 uint32_t container_id; 646 uint32_t capability_id; 647 uint32_t graph_pos; 648 uint32_t stack_size; 649 uint32_t proc_domain; 650 struct list_head node; 651 652 uint32_t num_modules; 653 struct list_head modules_list; 654 struct audioreach_sub_graph *sub_graph; 655 }; 656 657 #define AR_MAX_MOD_LINKS 8 658 659 struct audioreach_module { 660 uint32_t module_id; 661 uint32_t instance_id; 662 663 uint32_t max_ip_port; 664 uint32_t max_op_port; 665 666 uint32_t in_port; 667 uint32_t out_port; 668 669 uint32_t num_connections; 670 /* Connections */ 671 uint32_t src_mod_inst_id; 672 uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS]; 673 uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS]; 674 uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS]; 675 676 /* Format specifics */ 677 uint32_t ch_fmt; 678 uint32_t rate; 679 uint32_t bit_depth; 680 681 /* I2S module */ 682 uint32_t hw_interface_idx; 683 uint32_t sd_line_idx; 684 uint32_t ws_src; 685 uint32_t frame_size_factor; 686 uint32_t data_format; 687 uint32_t hw_interface_type; 688 689 /* PCM module specific */ 690 uint32_t interleave_type; 691 692 /* GAIN/Vol Control Module */ 693 uint16_t gain; 694 695 /* Logging */ 696 uint32_t log_code; 697 uint32_t log_tap_point_id; 698 uint32_t log_mode; 699 700 /* bookkeeping */ 701 struct list_head node; 702 struct audioreach_container *container; 703 struct snd_soc_dapm_widget *widget; 704 }; 705 706 struct audioreach_module_config { 707 int direction; 708 u32 sample_rate; 709 u16 bit_width; 710 u16 bits_per_sample; 711 712 u16 data_format; 713 u16 num_channels; 714 u16 active_channels_mask; 715 u16 dp_idx; 716 u32 channel_allocation; 717 u32 sd_line_mask; 718 int fmt; 719 u8 channel_map[AR_PCM_MAX_NUM_CHANNEL]; 720 }; 721 722 /* Packet Allocation routines */ 723 void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t 724 token); 725 void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode, 726 uint32_t token, uint32_t src_port, 727 uint32_t dest_port); 728 void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token, 729 uint32_t src_port); 730 void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, 731 uint32_t token, uint32_t src_port, 732 uint32_t dest_port); 733 void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct audioreach_graph_info 734 *info); 735 /* Topology specific */ 736 int audioreach_tplg_init(struct snd_soc_component *component); 737 738 /* Module specific */ 739 void audioreach_graph_free_buf(struct q6apm_graph *graph); 740 int audioreach_map_memory_regions(struct q6apm_graph *graph, 741 unsigned int dir, size_t period_sz, 742 unsigned int periods, 743 bool is_contiguous); 744 int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result, 745 struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait, 746 struct gpr_pkt *pkt, uint32_t rsp_opcode); 747 int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt, 748 uint32_t rsp_opcode); 749 int audioreach_set_media_format(struct q6apm_graph *graph, 750 struct audioreach_module *module, 751 struct audioreach_module_config *cfg); 752 int audioreach_shared_memory_send_eos(struct q6apm_graph *graph); 753 int audioreach_gain_set_vol_ctrl(struct q6apm *apm, 754 struct audioreach_module *module, int vol); 755 #endif /* __AUDIOREACH_H__ */ 756