1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __AUDIOREACH_H__ 4 #define __AUDIOREACH_H__ 5 #include <linux/types.h> 6 #include <linux/soc/qcom/apr.h> 7 #include <sound/soc.h> 8 struct q6apm; 9 struct q6apm_graph; 10 11 /* Module IDs */ 12 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 13 #define MODULE_ID_RD_SHARED_MEM_EP 0x07001001 14 #define MODULE_ID_GAIN 0x07001002 15 #define MODULE_ID_PCM_CNV 0x07001003 16 #define MODULE_ID_PCM_ENC 0x07001004 17 #define MODULE_ID_PCM_DEC 0x07001005 18 #define MODULE_ID_SAL 0x07001010 19 #define MODULE_ID_MFC 0x07001015 20 #define MODULE_ID_CODEC_DMA_SINK 0x07001023 21 #define MODULE_ID_CODEC_DMA_SOURCE 0x07001024 22 #define MODULE_ID_I2S_SINK 0x0700100A 23 #define MODULE_ID_I2S_SOURCE 0x0700100B 24 #define MODULE_ID_DATA_LOGGING 0x0700101A 25 26 #define APM_CMD_GET_SPF_STATE 0x01001021 27 #define APM_CMD_RSP_GET_SPF_STATE 0x02001007 28 29 #define APM_MODULE_INSTANCE_ID 0x00000001 30 #define PRM_MODULE_INSTANCE_ID 0x00000002 31 #define AMDB_MODULE_INSTANCE_ID 0x00000003 32 #define VCPM_MODULE_INSTANCE_ID 0x00000004 33 #define AR_MODULE_INSTANCE_ID_START 0x00006000 34 #define AR_MODULE_INSTANCE_ID_END 0x00007000 35 #define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000 36 #define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000 37 #define AR_CONT_INSTANCE_ID_START 0x00005000 38 #define AR_CONT_INSTANCE_ID_END 0x00006000 39 #define AR_SG_INSTANCE_ID_START 0x00004000 40 41 #define APM_CMD_GRAPH_OPEN 0x01001000 42 #define APM_CMD_GRAPH_PREPARE 0x01001001 43 #define APM_CMD_GRAPH_START 0x01001002 44 #define APM_CMD_GRAPH_STOP 0x01001003 45 #define APM_CMD_GRAPH_CLOSE 0x01001004 46 #define APM_CMD_GRAPH_FLUSH 0x01001005 47 #define APM_CMD_SET_CFG 0x01001006 48 #define APM_CMD_GET_CFG 0x01001007 49 #define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C 50 #define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D 51 #define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001 52 #define APM_CMD_RSP_GET_CFG 0x02001000 53 #define APM_CMD_CLOSE_ALL 0x01001013 54 #define APM_CMD_REGISTER_SHARED_CFG 0x0100100A 55 56 #define APM_MEMORY_MAP_SHMEM8_4K_POOL 3 57 58 struct apm_cmd_shared_mem_map_regions { 59 uint16_t mem_pool_id; 60 uint16_t num_regions; 61 uint32_t property_flag; 62 } __packed; 63 64 struct apm_shared_map_region_payload { 65 uint32_t shm_addr_lsw; 66 uint32_t shm_addr_msw; 67 uint32_t mem_size_bytes; 68 } __packed; 69 70 struct apm_cmd_shared_mem_unmap_regions { 71 uint32_t mem_map_handle; 72 } __packed; 73 74 struct apm_cmd_rsp_shared_mem_map_regions { 75 uint32_t mem_map_handle; 76 } __packed; 77 78 /* APM module */ 79 #define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005 80 81 #define APM_PARAM_ID_MODULE_LIST 0x08001002 82 83 struct apm_param_id_modules_list { 84 uint32_t num_modules_list; 85 } __packed; 86 87 #define APM_PARAM_ID_MODULE_PROP 0x08001003 88 89 struct apm_param_id_module_prop { 90 uint32_t num_modules_prop_cfg; 91 } __packed; 92 93 struct apm_module_prop_cfg { 94 uint32_t instance_id; 95 uint32_t num_props; 96 } __packed; 97 98 #define APM_PARAM_ID_MODULE_CONN 0x08001004 99 100 struct apm_param_id_module_conn { 101 uint32_t num_connections; 102 } __packed; 103 104 struct apm_module_conn_obj { 105 uint32_t src_mod_inst_id; 106 uint32_t src_mod_op_port_id; 107 uint32_t dst_mod_inst_id; 108 uint32_t dst_mod_ip_port_id; 109 } __packed; 110 111 #define APM_PARAM_ID_GAIN 0x08001006 112 113 struct param_id_gain_cfg { 114 uint16_t gain; 115 uint16_t reserved; 116 } __packed; 117 118 #define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008 119 120 struct param_id_pcm_output_format_cfg { 121 uint32_t data_format; 122 uint32_t fmt_id; 123 uint32_t payload_size; 124 } __packed; 125 126 struct payload_pcm_output_format_cfg { 127 uint16_t bit_width; 128 uint16_t alignment; 129 uint16_t bits_per_sample; 130 uint16_t q_factor; 131 uint16_t endianness; 132 uint16_t interleaved; 133 uint16_t reserved; 134 uint16_t num_channels; 135 uint8_t channel_mapping[]; 136 } __packed; 137 138 #define PARAM_ID_ENC_BITRATE 0x08001052 139 140 struct param_id_enc_bitrate_param { 141 uint32_t bitrate; 142 } __packed; 143 144 #define DATA_FORMAT_FIXED_POINT 1 145 #define PCM_LSB_ALIGNED 1 146 #define PCM_MSB_ALIGNED 2 147 #define PCM_LITTLE_ENDIAN 1 148 #define PCM_BIT_ENDIAN 2 149 150 #define MEDIA_FMT_ID_PCM 0x09001000 151 #define PCM_CHANNEL_L 1 152 #define PCM_CHANNEL_R 2 153 #define SAMPLE_RATE_48K 48000 154 #define BIT_WIDTH_16 16 155 156 #define APM_PARAM_ID_PROP_PORT_INFO 0x08001015 157 158 struct apm_modules_prop_info { 159 uint32_t max_ip_port; 160 uint32_t max_op_port; 161 } __packed; 162 163 /* Shared memory module */ 164 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000 165 #define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31) 166 #define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30) 167 #define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29) 168 #define WR_SH_MEM_EP_EOF_FLAG BIT(4) 169 170 struct apm_data_cmd_wr_sh_mem_ep_data_buffer { 171 uint32_t buf_addr_lsw; 172 uint32_t buf_addr_msw; 173 uint32_t mem_map_handle; 174 uint32_t buf_size; 175 uint32_t timestamp_lsw; 176 uint32_t timestamp_msw; 177 uint32_t flags; 178 } __packed; 179 180 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A 181 182 struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 { 183 uint32_t buf_addr_lsw; 184 uint32_t buf_addr_msw; 185 uint32_t mem_map_handle; 186 uint32_t buf_size; 187 uint32_t timestamp_lsw; 188 uint32_t timestamp_msw; 189 uint32_t flags; 190 uint32_t md_addr_lsw; 191 uint32_t md_addr_msw; 192 uint32_t md_map_handle; 193 uint32_t md_buf_size; 194 } __packed; 195 196 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000 197 198 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done { 199 uint32_t buf_addr_lsw; 200 uint32_t buf_addr_msw; 201 uint32_t mem_map_handle; 202 uint32_t status; 203 204 } __packed; 205 206 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004 207 208 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 { 209 uint32_t buf_addr_lsw; 210 uint32_t buf_addr_msw; 211 uint32_t mem_map_handle; 212 uint32_t status; 213 uint32_t md_buf_addr_lsw; 214 uint32_t md_buf_addr_msw; 215 uint32_t md_mem_map_handle; 216 uint32_t md_status; 217 } __packed; 218 219 #define PARAM_ID_MEDIA_FORMAT 0x0800100C 220 #define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001 221 222 struct apm_media_format { 223 uint32_t data_format; 224 uint32_t fmt_id; 225 uint32_t payload_size; 226 } __packed; 227 228 #define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002 229 #define WR_SH_MEM_EP_EOS_POLICY_LAST 1 230 #define WR_SH_MEM_EP_EOS_POLICY_EACH 2 231 232 struct data_cmd_wr_sh_mem_ep_eos { 233 uint32_t policy; 234 235 } __packed; 236 237 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003 238 239 struct data_cmd_rd_sh_mem_ep_data_buffer { 240 uint32_t buf_addr_lsw; 241 uint32_t buf_addr_msw; 242 uint32_t mem_map_handle; 243 uint32_t buf_size; 244 } __packed; 245 246 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002 247 248 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done { 249 uint32_t status; 250 uint32_t buf_addr_lsw; 251 uint32_t buf_addr_msw; 252 uint32_t mem_map_handle; 253 uint32_t data_size; 254 uint32_t offset; 255 uint32_t timestamp_lsw; 256 uint32_t timestamp_msw; 257 uint32_t flags; 258 uint32_t num_frames; 259 } __packed; 260 261 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B 262 263 struct data_cmd_rd_sh_mem_ep_data_buffer_v2 { 264 uint32_t buf_addr_lsw; 265 uint32_t buf_addr_msw; 266 uint32_t mem_map_handle; 267 uint32_t buf_size; 268 uint32_t md_buf_addr_lsw; 269 uint32_t md_buf_addr_msw; 270 uint32_t md_mem_map_handle; 271 uint32_t md_buf_size; 272 } __packed; 273 274 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005 275 276 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 { 277 uint32_t status; 278 uint32_t buf_addr_lsw; 279 uint32_t buf_addr_msw; 280 uint32_t mem_map_handle; 281 uint32_t data_size; 282 uint32_t offset; 283 uint32_t timestamp_lsw; 284 uint32_t timestamp_msw; 285 uint32_t flags; 286 uint32_t num_frames; 287 uint32_t md_status; 288 uint32_t md_buf_addr_lsw; 289 uint32_t md_buf_addr_msw; 290 uint32_t md_mem_map_handle; 291 uint32_t md_size; 292 } __packed; 293 294 #define PARAM_ID_RD_SH_MEM_CFG 0x08001007 295 296 struct param_id_rd_sh_mem_cfg { 297 uint32_t num_frames_per_buffer; 298 uint32_t metadata_control_flags; 299 300 } __packed; 301 302 #define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001 303 304 struct data_cmd_wr_sh_mem_ep_eos_rendered { 305 uint32_t module_instance_id; 306 uint32_t render_status; 307 } __packed; 308 309 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 310 311 struct apm_cmd_header { 312 uint32_t payload_address_lsw; 313 uint32_t payload_address_msw; 314 uint32_t mem_map_handle; 315 uint32_t payload_size; 316 } __packed; 317 318 #define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header) 319 320 struct apm_module_param_data { 321 uint32_t module_instance_id; 322 uint32_t param_id; 323 uint32_t param_size; 324 uint32_t error_code; 325 } __packed; 326 327 #define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data) 328 329 struct apm_module_param_shared_data { 330 uint32_t param_id; 331 uint32_t param_size; 332 } __packed; 333 334 struct apm_prop_data { 335 uint32_t prop_id; 336 uint32_t prop_size; 337 } __packed; 338 339 /* Sub-Graph Properties */ 340 #define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001 341 342 struct apm_param_id_sub_graph_cfg { 343 uint32_t num_sub_graphs; 344 } __packed; 345 346 struct apm_sub_graph_cfg { 347 uint32_t sub_graph_id; 348 uint32_t num_sub_graph_prop; 349 } __packed; 350 351 #define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E 352 353 struct apm_sg_prop_id_perf_mode { 354 uint32_t perf_mode; 355 } __packed; 356 357 #define APM_SG_PROP_ID_PERF_MODE_SIZE 4 358 359 #define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F 360 361 struct apm_sg_prop_id_direction { 362 uint32_t direction; 363 } __packed; 364 365 #define APM_SG_PROP_ID_DIR_SIZE 4 366 367 #define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010 368 #define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1 369 #define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2 370 #define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3 371 372 struct apm_sg_prop_id_scenario_id { 373 uint32_t scenario_id; 374 } __packed; 375 376 #define APM_SG_PROP_ID_SID_SIZE 4 377 /* container api */ 378 #define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000 379 380 struct apm_param_id_container_cfg { 381 uint32_t num_containers; 382 } __packed; 383 384 struct apm_container_cfg { 385 uint32_t container_id; 386 uint32_t num_prop; 387 } __packed; 388 389 struct apm_cont_capability { 390 uint32_t capability_id; 391 } __packed; 392 393 #define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011 394 #define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8 395 396 #define APM_PROP_ID_INVALID 0x0 397 #define APM_CONTAINER_CAP_ID_PP 0x1 398 #define APM_CONTAINER_CAP_ID_PP 0x1 399 400 struct apm_cont_prop_id_cap_list { 401 uint32_t num_capability_id; 402 } __packed; 403 404 #define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012 405 406 struct apm_cont_prop_id_graph_pos { 407 uint32_t graph_pos; 408 } __packed; 409 410 #define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013 411 412 struct apm_cont_prop_id_stack_size { 413 uint32_t stack_size; 414 } __packed; 415 416 #define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014 417 418 struct apm_cont_prop_id_domain { 419 uint32_t proc_domain; 420 } __packed; 421 422 #define CONFIG_I2S_WS_SRC_EXTERNAL 0x0 423 #define CONFIG_I2S_WS_SRC_INTERNAL 0x1 424 425 #define PARAM_ID_I2S_INTF_CFG 0x08001019 426 struct param_id_i2s_intf_cfg { 427 uint32_t lpaif_type; 428 uint32_t intf_idx; 429 uint16_t sd_line_idx; 430 uint16_t ws_src; 431 } __packed; 432 433 #define I2S_INTF_TYPE_PRIMARY 0 434 #define I2S_INTF_TYPE_SECOINDARY 1 435 #define I2S_INTF_TYPE_TERTINARY 2 436 #define I2S_INTF_TYPE_QUATERNARY 3 437 #define I2S_INTF_TYPE_QUINARY 4 438 #define I2S_SD0 1 439 #define I2S_SD1 2 440 #define I2S_SD2 3 441 #define I2S_SD3 4 442 443 #define PORT_ID_I2S_INPUT 2 444 #define PORT_ID_I2S_OUPUT 1 445 #define I2S_STACK_SIZE 2048 446 447 #define PARAM_ID_HW_EP_MF_CFG 0x08001017 448 struct param_id_hw_ep_mf { 449 uint32_t sample_rate; 450 uint16_t bit_width; 451 uint16_t num_channels; 452 uint32_t data_format; 453 } __packed; 454 455 #define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018 456 457 struct param_id_fram_size_factor { 458 uint32_t frame_size_factor; 459 } __packed; 460 461 #define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB 462 463 struct apm_cont_prop_id_parent_container { 464 uint32_t parent_container_id; 465 } __packed; 466 467 #define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174 468 #define APM_CONT_HEAP_DEFAULT 0x1 469 #define APM_CONT_HEAP_LOW_POWER 0x2 470 471 struct apm_cont_prop_id_headp_id { 472 uint32_t heap_id; 473 } __packed; 474 475 struct apm_modules_list { 476 uint32_t sub_graph_id; 477 uint32_t container_id; 478 uint32_t num_modules; 479 } __packed; 480 481 struct apm_module_obj { 482 uint32_t module_id; 483 uint32_t instance_id; 484 } __packed; 485 486 #define APM_MODULE_PROP_ID_PORT_INFO 0x08001015 487 #define APM_MODULE_PROP_ID_PORT_INFO_SZ 8 488 struct apm_module_prop_id_port_info { 489 uint32_t max_ip_port; 490 uint32_t max_op_port; 491 } __packed; 492 493 #define DATA_LOGGING_MAX_INPUT_PORTS 0x1 494 #define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1 495 #define DATA_LOGGING_STACK_SIZE 2048 496 #define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031 497 498 struct data_logging_config { 499 uint32_t log_code; 500 uint32_t log_tap_point_id; 501 uint32_t mode; 502 } __packed; 503 504 #define PARAM_ID_SAL_OUTPUT_CFG 0x08001016 505 struct param_id_sal_output_config { 506 uint32_t bits_per_sample; 507 } __packed; 508 509 #define PARAM_ID_SAL_LIMITER_ENABLE 0x0800101E 510 struct param_id_sal_limiter_enable { 511 uint32_t enable_lim; 512 } __packed; 513 514 #define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024 515 516 struct param_id_mfc_media_format { 517 uint32_t sample_rate; 518 uint16_t bit_width; 519 uint16_t num_channels; 520 uint16_t channel_mapping[]; 521 } __packed; 522 523 struct media_format { 524 uint32_t data_format; 525 uint32_t fmt_id; 526 uint32_t payload_size; 527 } __packed; 528 529 struct payload_media_fmt_pcm { 530 uint32_t sample_rate; 531 uint16_t bit_width; 532 uint16_t alignment; 533 uint16_t bits_per_sample; 534 uint16_t q_factor; 535 uint16_t endianness; 536 uint16_t num_channels; 537 uint8_t channel_mapping[]; 538 } __packed; 539 540 #define PARAM_ID_MODULE_ENABLE 0x08001026 541 struct param_id_module_enable { 542 uint32_t enable; 543 } __packed; 544 545 #define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063 546 547 struct param_id_codec_dma_intf_cfg { 548 /* 1 - RXTX 549 * 2 - WSA 550 * 3 - VA 551 * 4 - AXI 552 */ 553 uint32_t lpaif_type; 554 /* 555 * RX0 | TX0 = 1 556 * RX1 | TX1 = 2 557 * RX2 | TX2 = 3... so on 558 */ 559 uint32_t intf_index; 560 uint32_t active_channels_mask; 561 } __packed; 562 563 struct audio_hw_clk_cfg { 564 uint32_t clock_id; 565 uint32_t clock_freq; 566 uint32_t clock_attri; 567 uint32_t clock_root; 568 } __packed; 569 570 struct audio_hw_clk_rel_cfg { 571 uint32_t clock_id; 572 } __packed; 573 574 #define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176 575 #define AR_HW_EP_POWER_MODE_0 0 /* default */ 576 #define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */ 577 #define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */ 578 579 struct param_id_hw_ep_power_mode_cfg { 580 uint32_t power_mode; 581 } __packed; 582 583 #define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233 584 #define AR_HW_EP_DMA_DATA_ALIGN_MSB 0 585 #define AR_HW_EP_DMA_DATA_ALIGN_LSB 1 586 #define AR_PCM_MAX_NUM_CHANNEL 8 587 588 struct param_id_hw_ep_dma_data_align { 589 uint32_t dma_data_align; 590 } __packed; 591 592 #define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035 593 #define VOL_CTRL_DEFAULT_GAIN 0x2000 594 595 struct param_id_vol_ctrl_master_gain { 596 uint16_t master_gain; 597 uint16_t reserved; 598 } __packed; 599 600 601 /* Graph */ 602 struct audioreach_connection { 603 /* Connections */ 604 uint32_t src_mod_inst_id; 605 uint32_t src_mod_op_port_id; 606 uint32_t dst_mod_inst_id; 607 uint32_t dst_mod_ip_port_id; 608 struct list_head node; 609 }; 610 611 struct audioreach_graph_info { 612 int id; 613 uint32_t num_sub_graphs; 614 struct list_head sg_list; 615 /* DPCM connection from FE Graph to BE graph */ 616 uint32_t src_mod_inst_id; 617 uint32_t src_mod_op_port_id; 618 uint32_t dst_mod_inst_id; 619 uint32_t dst_mod_ip_port_id; 620 }; 621 622 struct audioreach_sub_graph { 623 uint32_t sub_graph_id; 624 uint32_t perf_mode; 625 uint32_t direction; 626 uint32_t scenario_id; 627 struct list_head node; 628 629 struct audioreach_graph_info *info; 630 uint32_t num_containers; 631 struct list_head container_list; 632 }; 633 634 struct audioreach_container { 635 uint32_t container_id; 636 uint32_t capability_id; 637 uint32_t graph_pos; 638 uint32_t stack_size; 639 uint32_t proc_domain; 640 struct list_head node; 641 642 uint32_t num_modules; 643 struct list_head modules_list; 644 struct audioreach_sub_graph *sub_graph; 645 }; 646 647 #define AR_MAX_MOD_LINKS 8 648 649 struct audioreach_module { 650 uint32_t module_id; 651 uint32_t instance_id; 652 653 uint32_t max_ip_port; 654 uint32_t max_op_port; 655 656 uint32_t in_port; 657 uint32_t out_port; 658 659 uint32_t num_connections; 660 /* Connections */ 661 uint32_t src_mod_inst_id; 662 uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS]; 663 uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS]; 664 uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS]; 665 666 /* Format specifics */ 667 uint32_t ch_fmt; 668 uint32_t rate; 669 uint32_t bit_depth; 670 671 /* I2S module */ 672 uint32_t hw_interface_idx; 673 uint32_t sd_line_idx; 674 uint32_t ws_src; 675 uint32_t frame_size_factor; 676 uint32_t data_format; 677 uint32_t hw_interface_type; 678 679 /* PCM module specific */ 680 uint32_t interleave_type; 681 682 /* GAIN/Vol Control Module */ 683 uint16_t gain; 684 685 /* Logging */ 686 uint32_t log_code; 687 uint32_t log_tap_point_id; 688 uint32_t log_mode; 689 690 /* bookkeeping */ 691 struct list_head node; 692 struct audioreach_container *container; 693 struct snd_soc_dapm_widget *widget; 694 }; 695 696 struct audioreach_module_config { 697 int direction; 698 u32 sample_rate; 699 u16 bit_width; 700 u16 bits_per_sample; 701 702 u16 data_format; 703 u16 num_channels; 704 u16 active_channels_mask; 705 u32 sd_line_mask; 706 int fmt; 707 u8 channel_map[AR_PCM_MAX_NUM_CHANNEL]; 708 }; 709 710 /* Packet Allocation routines */ 711 void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t 712 token); 713 void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode, 714 uint32_t token, uint32_t src_port, 715 uint32_t dest_port); 716 void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token, 717 uint32_t src_port); 718 void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, 719 uint32_t token, uint32_t src_port, 720 uint32_t dest_port); 721 void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct audioreach_graph_info 722 *info); 723 /* Topology specific */ 724 int audioreach_tplg_init(struct snd_soc_component *component); 725 726 /* Module specific */ 727 void audioreach_graph_free_buf(struct q6apm_graph *graph); 728 int audioreach_map_memory_regions(struct q6apm_graph *graph, 729 unsigned int dir, size_t period_sz, 730 unsigned int periods, 731 bool is_contiguous); 732 int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result, 733 struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait, 734 struct gpr_pkt *pkt, uint32_t rsp_opcode); 735 int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt, 736 uint32_t rsp_opcode); 737 int audioreach_set_media_format(struct q6apm_graph *graph, 738 struct audioreach_module *module, 739 struct audioreach_module_config *cfg); 740 int audioreach_shared_memory_send_eos(struct q6apm_graph *graph); 741 int audioreach_gain_set_vol_ctrl(struct q6apm *apm, 742 struct audioreach_module *module, int vol); 743 #endif /* __AUDIOREACH_H__ */ 744