1cd59f138SKenneth Westfield /* 2cd59f138SKenneth Westfield * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 3cd59f138SKenneth Westfield * 4cd59f138SKenneth Westfield * This program is free software; you can redistribute it and/or modify 5cd59f138SKenneth Westfield * it under the terms of the GNU General Public License version 2 and 6cd59f138SKenneth Westfield * only version 2 as published by the Free Software Foundation. 7cd59f138SKenneth Westfield * 8cd59f138SKenneth Westfield * This program is distributed in the hope that it will be useful, 9cd59f138SKenneth Westfield * but WITHOUT ANY WARRANTY; without even the implied warranty of 10cd59f138SKenneth Westfield * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11cd59f138SKenneth Westfield * GNU General Public License for more details. 12cd59f138SKenneth Westfield * 13cd59f138SKenneth Westfield * lpass.h - Definitions for the QTi LPASS 14cd59f138SKenneth Westfield */ 15cd59f138SKenneth Westfield 16cd59f138SKenneth Westfield #ifndef __LPASS_H__ 17cd59f138SKenneth Westfield #define __LPASS_H__ 18cd59f138SKenneth Westfield 19cd59f138SKenneth Westfield #include <linux/clk.h> 20cd59f138SKenneth Westfield #include <linux/compiler.h> 21cd59f138SKenneth Westfield #include <linux/platform_device.h> 22cd59f138SKenneth Westfield #include <linux/regmap.h> 23cd59f138SKenneth Westfield 24cd59f138SKenneth Westfield #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 259a127cffSSrinivas Kandagatla #define LPASS_MAX_MI2S_PORTS (8) 264f629e4bSSrinivas Kandagatla #define LPASS_MAX_DMA_CHANNELS (8) 27cd59f138SKenneth Westfield 28cd59f138SKenneth Westfield /* Both the CPU DAI and platform drivers will access this data */ 29cd59f138SKenneth Westfield struct lpass_data { 30cd59f138SKenneth Westfield 31cd59f138SKenneth Westfield /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */ 32cd59f138SKenneth Westfield struct clk *ahbix_clk; 33cd59f138SKenneth Westfield 34cd59f138SKenneth Westfield /* MI2S system clock */ 359a127cffSSrinivas Kandagatla struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS]; 36cd59f138SKenneth Westfield 37cd59f138SKenneth Westfield /* MI2S bit clock (derived from system clock by a divider */ 389a127cffSSrinivas Kandagatla struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS]; 39cd59f138SKenneth Westfield 40cd59f138SKenneth Westfield /* low-power audio interface (LPAIF) registers */ 41cd59f138SKenneth Westfield void __iomem *lpaif; 42cd59f138SKenneth Westfield 43cd59f138SKenneth Westfield /* regmap backed by the low-power audio interface (LPAIF) registers */ 44cd59f138SKenneth Westfield struct regmap *lpaif_map; 45cd59f138SKenneth Westfield 46cd59f138SKenneth Westfield /* interrupts from the low-power audio interface (LPAIF) */ 47cd59f138SKenneth Westfield int lpaif_irq; 489bae4880SSrinivas Kandagatla 499bae4880SSrinivas Kandagatla /* SOC specific variations in the LPASS IP integration */ 509bae4880SSrinivas Kandagatla struct lpass_variant *variant; 514f629e4bSSrinivas Kandagatla 5289cdfa06SSrinivas Kandagatla /* bit map to keep track of static channel allocations */ 5389cdfa06SSrinivas Kandagatla unsigned long rdma_ch_bit_map; 5489cdfa06SSrinivas Kandagatla 554f629e4bSSrinivas Kandagatla /* used it for handling interrupt per dma channel */ 564f629e4bSSrinivas Kandagatla struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS]; 57dc1ebd18SSrinivas Kandagatla 58dc1ebd18SSrinivas Kandagatla /* 8016 specific */ 59dc1ebd18SSrinivas Kandagatla struct clk *pcnoc_mport_clk; 60dc1ebd18SSrinivas Kandagatla struct clk *pcnoc_sway_clk; 619bae4880SSrinivas Kandagatla }; 629bae4880SSrinivas Kandagatla 639bae4880SSrinivas Kandagatla /* Vairant data per each SOC */ 649bae4880SSrinivas Kandagatla struct lpass_variant { 659bae4880SSrinivas Kandagatla u32 i2sctrl_reg_base; 669bae4880SSrinivas Kandagatla u32 i2sctrl_reg_stride; 679bae4880SSrinivas Kandagatla u32 i2s_ports; 689bae4880SSrinivas Kandagatla u32 irq_reg_base; 699bae4880SSrinivas Kandagatla u32 irq_reg_stride; 709bae4880SSrinivas Kandagatla u32 irq_ports; 719bae4880SSrinivas Kandagatla u32 rdma_reg_base; 729bae4880SSrinivas Kandagatla u32 rdma_reg_stride; 739bae4880SSrinivas Kandagatla u32 rdma_channels; 74ffc1325eSSrinivas Kandagatla u32 wrdma_reg_base; 75ffc1325eSSrinivas Kandagatla u32 wrdma_reg_stride; 76ffc1325eSSrinivas Kandagatla u32 wrdma_channels; 779bae4880SSrinivas Kandagatla 780054055cSSrinivas Kandagatla /** 790054055cSSrinivas Kandagatla * on SOCs like APQ8016 the channel control bits start 800054055cSSrinivas Kandagatla * at different offset to ipq806x 810054055cSSrinivas Kandagatla **/ 82ec5b8287SSrinivas Kandagatla u32 dmactl_audif_start; 83ffc1325eSSrinivas Kandagatla u32 wrdma_channel_start; 849bae4880SSrinivas Kandagatla /* SOC specific intialization like clocks */ 859bae4880SSrinivas Kandagatla int (*init)(struct platform_device *pdev); 869bae4880SSrinivas Kandagatla int (*exit)(struct platform_device *pdev); 8773c847b6SSrinivas Kandagatla int (*alloc_dma_channel)(struct lpass_data *data, int direction); 886db1c6baSSrinivas Kandagatla int (*free_dma_channel)(struct lpass_data *data, int ch); 899bae4880SSrinivas Kandagatla 909bae4880SSrinivas Kandagatla /* SOC specific dais */ 919bae4880SSrinivas Kandagatla struct snd_soc_dai_driver *dai_driver; 929bae4880SSrinivas Kandagatla int num_dai; 93cd59f138SKenneth Westfield }; 94cd59f138SKenneth Westfield 95cd59f138SKenneth Westfield /* register the platform driver from the CPU DAI driver */ 96cd59f138SKenneth Westfield int asoc_qcom_lpass_platform_register(struct platform_device *); 979bae4880SSrinivas Kandagatla int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev); 989bae4880SSrinivas Kandagatla int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev); 999bae4880SSrinivas Kandagatla int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai); 100618718dcSAxel Lin extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops; 101cd59f138SKenneth Westfield 102cd59f138SKenneth Westfield #endif /* __LPASS_H__ */ 103