197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2cd59f138SKenneth Westfield /* 3cd59f138SKenneth Westfield * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 4cd59f138SKenneth Westfield * 5cd59f138SKenneth Westfield * lpass.h - Definitions for the QTi LPASS 6cd59f138SKenneth Westfield */ 7cd59f138SKenneth Westfield 8cd59f138SKenneth Westfield #ifndef __LPASS_H__ 9cd59f138SKenneth Westfield #define __LPASS_H__ 10cd59f138SKenneth Westfield 11cd59f138SKenneth Westfield #include <linux/clk.h> 12cd59f138SKenneth Westfield #include <linux/compiler.h> 13cd59f138SKenneth Westfield #include <linux/platform_device.h> 14cd59f138SKenneth Westfield #include <linux/regmap.h> 15cd59f138SKenneth Westfield 16cd59f138SKenneth Westfield #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 179a127cffSSrinivas Kandagatla #define LPASS_MAX_MI2S_PORTS (8) 184f629e4bSSrinivas Kandagatla #define LPASS_MAX_DMA_CHANNELS (8) 19cd59f138SKenneth Westfield 20cd59f138SKenneth Westfield /* Both the CPU DAI and platform drivers will access this data */ 21cd59f138SKenneth Westfield struct lpass_data { 22cd59f138SKenneth Westfield 23cd59f138SKenneth Westfield /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */ 24cd59f138SKenneth Westfield struct clk *ahbix_clk; 25cd59f138SKenneth Westfield 26cd59f138SKenneth Westfield /* MI2S system clock */ 279a127cffSSrinivas Kandagatla struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS]; 28cd59f138SKenneth Westfield 29cd59f138SKenneth Westfield /* MI2S bit clock (derived from system clock by a divider */ 309a127cffSSrinivas Kandagatla struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS]; 31cd59f138SKenneth Westfield 324ff028f6SStephan Gerhold /* MI2S SD lines to use for playback/capture */ 334ff028f6SStephan Gerhold unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS]; 344ff028f6SStephan Gerhold unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS]; 354ff028f6SStephan Gerhold 36cd59f138SKenneth Westfield /* low-power audio interface (LPAIF) registers */ 37cd59f138SKenneth Westfield void __iomem *lpaif; 38cd59f138SKenneth Westfield 39cd59f138SKenneth Westfield /* regmap backed by the low-power audio interface (LPAIF) registers */ 40cd59f138SKenneth Westfield struct regmap *lpaif_map; 41cd59f138SKenneth Westfield 42cd59f138SKenneth Westfield /* interrupts from the low-power audio interface (LPAIF) */ 43cd59f138SKenneth Westfield int lpaif_irq; 449bae4880SSrinivas Kandagatla 459bae4880SSrinivas Kandagatla /* SOC specific variations in the LPASS IP integration */ 469bae4880SSrinivas Kandagatla struct lpass_variant *variant; 474f629e4bSSrinivas Kandagatla 4889cdfa06SSrinivas Kandagatla /* bit map to keep track of static channel allocations */ 494d809fb1SSrinivas Kandagatla unsigned long dma_ch_bit_map; 5089cdfa06SSrinivas Kandagatla 514f629e4bSSrinivas Kandagatla /* used it for handling interrupt per dma channel */ 524f629e4bSSrinivas Kandagatla struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS]; 53dc1ebd18SSrinivas Kandagatla 541220f6a7SAjit Pandey /* SOC specific clock list */ 551220f6a7SAjit Pandey struct clk_bulk_data *clks; 561220f6a7SAjit Pandey int num_clks; 576adcbdcdSKuninori Morimoto 589bae4880SSrinivas Kandagatla }; 599bae4880SSrinivas Kandagatla 609bae4880SSrinivas Kandagatla /* Vairant data per each SOC */ 619bae4880SSrinivas Kandagatla struct lpass_variant { 629bae4880SSrinivas Kandagatla u32 i2sctrl_reg_base; 639bae4880SSrinivas Kandagatla u32 i2sctrl_reg_stride; 649bae4880SSrinivas Kandagatla u32 i2s_ports; 659bae4880SSrinivas Kandagatla u32 irq_reg_base; 669bae4880SSrinivas Kandagatla u32 irq_reg_stride; 679bae4880SSrinivas Kandagatla u32 irq_ports; 689bae4880SSrinivas Kandagatla u32 rdma_reg_base; 699bae4880SSrinivas Kandagatla u32 rdma_reg_stride; 709bae4880SSrinivas Kandagatla u32 rdma_channels; 71ffc1325eSSrinivas Kandagatla u32 wrdma_reg_base; 72ffc1325eSSrinivas Kandagatla u32 wrdma_reg_stride; 73ffc1325eSSrinivas Kandagatla u32 wrdma_channels; 749bae4880SSrinivas Kandagatla 750054055cSSrinivas Kandagatla /** 760054055cSSrinivas Kandagatla * on SOCs like APQ8016 the channel control bits start 770054055cSSrinivas Kandagatla * at different offset to ipq806x 780054055cSSrinivas Kandagatla **/ 79ec5b8287SSrinivas Kandagatla u32 dmactl_audif_start; 80ffc1325eSSrinivas Kandagatla u32 wrdma_channel_start; 81183b8021SMasahiro Yamada /* SOC specific initialization like clocks */ 829bae4880SSrinivas Kandagatla int (*init)(struct platform_device *pdev); 839bae4880SSrinivas Kandagatla int (*exit)(struct platform_device *pdev); 8473c847b6SSrinivas Kandagatla int (*alloc_dma_channel)(struct lpass_data *data, int direction); 856db1c6baSSrinivas Kandagatla int (*free_dma_channel)(struct lpass_data *data, int ch); 869bae4880SSrinivas Kandagatla 879bae4880SSrinivas Kandagatla /* SOC specific dais */ 889bae4880SSrinivas Kandagatla struct snd_soc_dai_driver *dai_driver; 899bae4880SSrinivas Kandagatla int num_dai; 9097c52eb9SLinus Walleij const char * const *dai_osr_clk_names; 9197c52eb9SLinus Walleij const char * const *dai_bit_clk_names; 921220f6a7SAjit Pandey 931220f6a7SAjit Pandey /* SOC specific clocks configuration */ 941220f6a7SAjit Pandey const char **clk_name; 951220f6a7SAjit Pandey int num_clks; 96cd59f138SKenneth Westfield }; 97cd59f138SKenneth Westfield 98cd59f138SKenneth Westfield /* register the platform driver from the CPU DAI driver */ 99cd59f138SKenneth Westfield int asoc_qcom_lpass_platform_register(struct platform_device *); 1009bae4880SSrinivas Kandagatla int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev); 1019bae4880SSrinivas Kandagatla int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev); 1029bae4880SSrinivas Kandagatla int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai); 103618718dcSAxel Lin extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops; 104cd59f138SKenneth Westfield 105cd59f138SKenneth Westfield #endif /* __LPASS_H__ */ 106