1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * 5 * lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <dt-bindings/sound/sc7180-lpass.h> 17 #include <sound/pcm.h> 18 #include <sound/soc.h> 19 20 #include "lpass-lpaif-reg.h" 21 #include "lpass.h" 22 23 static struct snd_soc_dai_driver sc7180_lpass_cpu_dai_driver[] = { 24 { 25 .id = MI2S_PRIMARY, 26 .name = "Primary MI2S", 27 .playback = { 28 .stream_name = "Primary Playback", 29 .formats = SNDRV_PCM_FMTBIT_S16, 30 .rates = SNDRV_PCM_RATE_48000, 31 .rate_min = 48000, 32 .rate_max = 48000, 33 .channels_min = 2, 34 .channels_max = 2, 35 }, 36 .capture = { 37 .stream_name = "Primary Capture", 38 .formats = SNDRV_PCM_FMTBIT_S16 | 39 SNDRV_PCM_FMTBIT_S32, 40 .rates = SNDRV_PCM_RATE_48000, 41 .rate_min = 48000, 42 .rate_max = 48000, 43 .channels_min = 2, 44 .channels_max = 2, 45 }, 46 .probe = &asoc_qcom_lpass_cpu_dai_probe, 47 .ops = &asoc_qcom_lpass_cpu_dai_ops, 48 }, { 49 .id = MI2S_SECONDARY, 50 .name = "Secondary MI2S", 51 .playback = { 52 .stream_name = "Secondary Playback", 53 .formats = SNDRV_PCM_FMTBIT_S16, 54 .rates = SNDRV_PCM_RATE_48000, 55 .rate_min = 48000, 56 .rate_max = 48000, 57 .channels_min = 2, 58 .channels_max = 2, 59 }, 60 .probe = &asoc_qcom_lpass_cpu_dai_probe, 61 .ops = &asoc_qcom_lpass_cpu_dai_ops, 62 .pcm_new = lpass_cpu_pcm_new, 63 }, { 64 .id = LPASS_DP_RX, 65 .name = "Hdmi", 66 .playback = { 67 .stream_name = "Hdmi Playback", 68 .formats = SNDRV_PCM_FMTBIT_S24, 69 .rates = SNDRV_PCM_RATE_48000, 70 .rate_min = 48000, 71 .rate_max = 48000, 72 .channels_min = 2, 73 .channels_max = 2, 74 }, 75 .ops = &asoc_qcom_lpass_hdmi_dai_ops, 76 }, 77 }; 78 79 static int sc7180_lpass_alloc_dma_channel(struct lpass_data *drvdata, 80 int direction, unsigned int dai_id) 81 { 82 struct lpass_variant *v = drvdata->variant; 83 int chan = 0; 84 85 if (dai_id == LPASS_DP_RX) { 86 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 87 chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map, 88 v->hdmi_rdma_channels); 89 90 if (chan >= v->hdmi_rdma_channels) 91 return -EBUSY; 92 } 93 set_bit(chan, &drvdata->hdmi_dma_ch_bit_map); 94 } else { 95 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 96 chan = find_first_zero_bit(&drvdata->dma_ch_bit_map, 97 v->rdma_channels); 98 99 if (chan >= v->rdma_channels) 100 return -EBUSY; 101 } else { 102 chan = find_next_zero_bit(&drvdata->dma_ch_bit_map, 103 v->wrdma_channel_start + 104 v->wrdma_channels, 105 v->wrdma_channel_start); 106 107 if (chan >= v->wrdma_channel_start + v->wrdma_channels) 108 return -EBUSY; 109 } 110 111 set_bit(chan, &drvdata->dma_ch_bit_map); 112 } 113 return chan; 114 } 115 116 static int sc7180_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id) 117 { 118 if (dai_id == LPASS_DP_RX) 119 clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map); 120 else 121 clear_bit(chan, &drvdata->dma_ch_bit_map); 122 123 return 0; 124 } 125 126 static int sc7180_lpass_init(struct platform_device *pdev) 127 { 128 struct lpass_data *drvdata = platform_get_drvdata(pdev); 129 struct lpass_variant *variant = drvdata->variant; 130 struct device *dev = &pdev->dev; 131 int ret, i; 132 133 drvdata->clks = devm_kcalloc(dev, variant->num_clks, 134 sizeof(*drvdata->clks), GFP_KERNEL); 135 if (!drvdata->clks) 136 return -ENOMEM; 137 138 drvdata->num_clks = variant->num_clks; 139 140 for (i = 0; i < drvdata->num_clks; i++) 141 drvdata->clks[i].id = variant->clk_name[i]; 142 143 ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks); 144 if (ret) { 145 dev_err(dev, "Failed to get clocks %d\n", ret); 146 return ret; 147 } 148 149 ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks); 150 if (ret) { 151 dev_err(dev, "sc7180 clk_enable failed\n"); 152 return ret; 153 } 154 155 return 0; 156 } 157 158 static int sc7180_lpass_exit(struct platform_device *pdev) 159 { 160 struct lpass_data *drvdata = platform_get_drvdata(pdev); 161 162 clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks); 163 return 0; 164 } 165 166 static int __maybe_unused sc7180_lpass_dev_resume(struct device *dev) 167 { 168 struct lpass_data *drvdata = dev_get_drvdata(dev); 169 170 return clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks); 171 } 172 173 static int __maybe_unused sc7180_lpass_dev_suspend(struct device *dev) 174 { 175 struct lpass_data *drvdata = dev_get_drvdata(dev); 176 177 clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks); 178 return 0; 179 } 180 181 static const struct dev_pm_ops sc7180_lpass_pm_ops = { 182 SET_SYSTEM_SLEEP_PM_OPS(sc7180_lpass_dev_suspend, sc7180_lpass_dev_resume) 183 }; 184 185 static struct lpass_variant sc7180_data = { 186 .i2sctrl_reg_base = 0x1000, 187 .i2sctrl_reg_stride = 0x1000, 188 .i2s_ports = 3, 189 .irq_reg_base = 0x9000, 190 .irq_reg_stride = 0x1000, 191 .irq_ports = 3, 192 .rdma_reg_base = 0xC000, 193 .rdma_reg_stride = 0x1000, 194 .rdma_channels = 5, 195 .hdmi_rdma_reg_base = 0x64000, 196 .hdmi_rdma_reg_stride = 0x1000, 197 .hdmi_rdma_channels = 4, 198 .dmactl_audif_start = 1, 199 .wrdma_reg_base = 0x18000, 200 .wrdma_reg_stride = 0x1000, 201 .wrdma_channel_start = 5, 202 .wrdma_channels = 4, 203 204 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000), 205 .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000), 206 .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000), 207 .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000), 208 .micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000), 209 .micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000), 210 .micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000), 211 .wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000), 212 .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000), 213 214 .rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000), 215 .rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000), 216 .rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000), 217 .rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000), 218 .rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000), 219 .rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000), 220 221 .wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000), 222 .wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000), 223 .wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000), 224 .wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000), 225 .wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000), 226 .wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000), 227 228 .hdmi_tx_ctl_addr = 0x1000, 229 .hdmi_legacy_addr = 0x1008, 230 .hdmi_vbit_addr = 0x610c0, 231 .hdmi_ch_lsb_addr = 0x61048, 232 .hdmi_ch_msb_addr = 0x6104c, 233 .ch_stride = 0x8, 234 .hdmi_parity_addr = 0x61034, 235 .hdmi_dmactl_addr = 0x61038, 236 .hdmi_dma_stride = 0x4, 237 .hdmi_DP_addr = 0x610c8, 238 .hdmi_sstream_addr = 0x6101c, 239 .hdmi_irq_reg_base = 0x63000, 240 .hdmi_irq_ports = 1, 241 242 .hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000), 243 .hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000), 244 .hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000), 245 .hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000), 246 .hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000), 247 .hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000), 248 .hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000), 249 .hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000), 250 251 .sstream_en = REG_FIELD(0x6101c, 0, 0), 252 .dma_sel = REG_FIELD(0x6101c, 1, 2), 253 .auto_bbit_en = REG_FIELD(0x6101c, 3, 3), 254 .layout = REG_FIELD(0x6101c, 4, 4), 255 .layout_sp = REG_FIELD(0x6101c, 5, 8), 256 .set_sp_on_en = REG_FIELD(0x6101c, 10, 10), 257 .dp_audio = REG_FIELD(0x6101c, 11, 11), 258 .dp_staffing_en = REG_FIELD(0x6101c, 12, 12), 259 .dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13), 260 261 .mute = REG_FIELD(0x610c8, 0, 0), 262 .as_sdp_cc = REG_FIELD(0x610c8, 1, 3), 263 .as_sdp_ct = REG_FIELD(0x610c8, 4, 7), 264 .aif_db4 = REG_FIELD(0x610c8, 8, 15), 265 .frequency = REG_FIELD(0x610c8, 16, 21), 266 .mst_index = REG_FIELD(0x610c8, 28, 29), 267 .dptx_index = REG_FIELD(0x610c8, 30, 31), 268 269 .soft_reset = REG_FIELD(0x1000, 31, 31), 270 .force_reset = REG_FIELD(0x1000, 30, 30), 271 272 .use_hw_chs = REG_FIELD(0x61038, 0, 0), 273 .use_hw_usr = REG_FIELD(0x61038, 1, 1), 274 .hw_chs_sel = REG_FIELD(0x61038, 2, 4), 275 .hw_usr_sel = REG_FIELD(0x61038, 5, 6), 276 277 .replace_vbit = REG_FIELD(0x610c0, 0, 0), 278 .vbit_stream = REG_FIELD(0x610c0, 1, 1), 279 280 .legacy_en = REG_FIELD(0x1008, 0, 0), 281 .calc_en = REG_FIELD(0x61034, 0, 0), 282 .lsb_bits = REG_FIELD(0x61048, 0, 31), 283 .msb_bits = REG_FIELD(0x6104c, 0, 31), 284 285 286 .clk_name = (const char*[]) { 287 "pcnoc-sway-clk", 288 "audio-core", 289 "pcnoc-mport-clk", 290 }, 291 .num_clks = 3, 292 .dai_driver = sc7180_lpass_cpu_dai_driver, 293 .num_dai = ARRAY_SIZE(sc7180_lpass_cpu_dai_driver), 294 .dai_osr_clk_names = (const char *[]) { 295 "mclk0", 296 "null", 297 }, 298 .dai_bit_clk_names = (const char *[]) { 299 "mi2s-bit-clk0", 300 "mi2s-bit-clk1", 301 }, 302 .init = sc7180_lpass_init, 303 .exit = sc7180_lpass_exit, 304 .alloc_dma_channel = sc7180_lpass_alloc_dma_channel, 305 .free_dma_channel = sc7180_lpass_free_dma_channel, 306 }; 307 308 static const struct of_device_id sc7180_lpass_cpu_device_id[] __maybe_unused = { 309 {.compatible = "qcom,sc7180-lpass-cpu", .data = &sc7180_data}, 310 {} 311 }; 312 MODULE_DEVICE_TABLE(of, sc7180_lpass_cpu_device_id); 313 314 static struct platform_driver sc7180_lpass_cpu_platform_driver = { 315 .driver = { 316 .name = "sc7180-lpass-cpu", 317 .of_match_table = of_match_ptr(sc7180_lpass_cpu_device_id), 318 .pm = &sc7180_lpass_pm_ops, 319 }, 320 .probe = asoc_qcom_lpass_cpu_platform_probe, 321 .remove = asoc_qcom_lpass_cpu_platform_remove, 322 .shutdown = asoc_qcom_lpass_cpu_platform_shutdown, 323 }; 324 325 module_platform_driver(sc7180_lpass_cpu_platform_driver); 326 327 MODULE_DESCRIPTION("SC7180 LPASS CPU DRIVER"); 328 MODULE_LICENSE("GPL v2"); 329