1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __LPASS_LPAIF_REG_H__ 7 #define __LPASS_LPAIF_REG_H__ 8 9 /* LPAIF I2S */ 10 11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ 12 (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port)) 13 14 #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) 15 #define LPAIF_I2SCTL_LOOPBACK_MASK 0x8000 16 #define LPAIF_I2SCTL_LOOPBACK_SHIFT 15 17 #define LPAIF_I2SCTL_LOOPBACK_DISABLE (0 << LPAIF_I2SCTL_LOOPBACK_SHIFT) 18 #define LPAIF_I2SCTL_LOOPBACK_ENABLE (1 << LPAIF_I2SCTL_LOOPBACK_SHIFT) 19 20 #define LPAIF_I2SCTL_SPKEN_MASK 0x4000 21 #define LPAIF_I2SCTL_SPKEN_SHIFT 14 22 #define LPAIF_I2SCTL_SPKEN_DISABLE (0 << LPAIF_I2SCTL_SPKEN_SHIFT) 23 #define LPAIF_I2SCTL_SPKEN_ENABLE (1 << LPAIF_I2SCTL_SPKEN_SHIFT) 24 25 #define LPAIF_I2SCTL_MODE_NONE 0 26 #define LPAIF_I2SCTL_MODE_SD0 1 27 #define LPAIF_I2SCTL_MODE_SD1 2 28 #define LPAIF_I2SCTL_MODE_SD2 3 29 #define LPAIF_I2SCTL_MODE_SD3 4 30 #define LPAIF_I2SCTL_MODE_QUAD01 5 31 #define LPAIF_I2SCTL_MODE_QUAD23 6 32 #define LPAIF_I2SCTL_MODE_6CH 7 33 #define LPAIF_I2SCTL_MODE_8CH 8 34 35 #define LPAIF_I2SCTL_SPKMODE_MASK 0x3C00 36 #define LPAIF_I2SCTL_SPKMODE_SHIFT 10 37 #define LPAIF_I2SCTL_SPKMODE(mode) ((mode) << LPAIF_I2SCTL_SPKMODE_SHIFT) 38 39 #define LPAIF_I2SCTL_SPKMONO_MASK 0x0200 40 #define LPAIF_I2SCTL_SPKMONO_SHIFT 9 41 #define LPAIF_I2SCTL_SPKMONO_STEREO (0 << LPAIF_I2SCTL_SPKMONO_SHIFT) 42 #define LPAIF_I2SCTL_SPKMONO_MONO (1 << LPAIF_I2SCTL_SPKMONO_SHIFT) 43 44 #define LPAIF_I2SCTL_MICEN_MASK GENMASK(8, 8) 45 #define LPAIF_I2SCTL_MICEN_SHIFT 8 46 #define LPAIF_I2SCTL_MICEN_DISABLE (0 << LPAIF_I2SCTL_MICEN_SHIFT) 47 #define LPAIF_I2SCTL_MICEN_ENABLE (1 << LPAIF_I2SCTL_MICEN_SHIFT) 48 49 #define LPAIF_I2SCTL_MICMODE_MASK GENMASK(7, 4) 50 #define LPAIF_I2SCTL_MICMODE_SHIFT 4 51 #define LPAIF_I2SCTL_MICMODE(mode) ((mode) << LPAIF_I2SCTL_MICMODE_SHIFT) 52 53 #define LPAIF_I2SCTL_MIMONO_MASK GENMASK(3, 3) 54 #define LPAIF_I2SCTL_MICMONO_SHIFT 3 55 #define LPAIF_I2SCTL_MICMONO_STEREO (0 << LPAIF_I2SCTL_MICMONO_SHIFT) 56 #define LPAIF_I2SCTL_MICMONO_MONO (1 << LPAIF_I2SCTL_MICMONO_SHIFT) 57 58 #define LPAIF_I2SCTL_WSSRC_MASK 0x0004 59 #define LPAIF_I2SCTL_WSSRC_SHIFT 2 60 #define LPAIF_I2SCTL_WSSRC_INTERNAL (0 << LPAIF_I2SCTL_WSSRC_SHIFT) 61 #define LPAIF_I2SCTL_WSSRC_EXTERNAL (1 << LPAIF_I2SCTL_WSSRC_SHIFT) 62 63 #define LPAIF_I2SCTL_BITWIDTH_MASK 0x0003 64 #define LPAIF_I2SCTL_BITWIDTH_SHIFT 0 65 #define LPAIF_I2SCTL_BITWIDTH_16 (0 << LPAIF_I2SCTL_BITWIDTH_SHIFT) 66 #define LPAIF_I2SCTL_BITWIDTH_24 (1 << LPAIF_I2SCTL_BITWIDTH_SHIFT) 67 #define LPAIF_I2SCTL_BITWIDTH_32 (2 << LPAIF_I2SCTL_BITWIDTH_SHIFT) 68 69 /* LPAIF IRQ */ 70 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \ 71 (v->irq_reg_base + (addr) + v->irq_reg_stride * (port)) 72 73 #define LPAIF_IRQ_PORT_HOST 0 74 75 #define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port)) 76 #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port)) 77 #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port)) 78 79 #define LPAIF_IRQ_BITSTRIDE 3 80 81 #define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan))) 82 #define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan))) 83 #define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan))) 84 85 #define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan))) 86 87 /* LPAIF DMA */ 88 89 #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \ 90 (v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan)) 91 92 #define LPAIF_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT) 93 94 #define LPAIF_RDMACTL_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x00, (chan)) 95 #define LPAIF_RDMABASE_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x04, (chan)) 96 #define LPAIF_RDMABUFF_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x08, (chan)) 97 #define LPAIF_RDMACURR_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan)) 98 #define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan)) 99 #define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x14, (chan)) 100 101 #define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \ 102 (v->wrdma_reg_base + (addr) + \ 103 v->wrdma_reg_stride * (chan - v->wrdma_channel_start)) 104 105 #define LPAIF_WRDMACTL_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan)) 106 #define LPAIF_WRDMABASE_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan)) 107 #define LPAIF_WRDMABUFF_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan)) 108 #define LPAIF_WRDMACURR_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan)) 109 #define LPAIF_WRDMAPER_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan)) 110 #define LPAIF_WRDMAPERCNT_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan)) 111 112 #define __LPAIF_DMA_REG(v, chan, dir, reg) \ 113 (dir == SNDRV_PCM_STREAM_PLAYBACK) ? \ 114 LPAIF_RDMA##reg##_REG(v, chan) : \ 115 LPAIF_WRDMA##reg##_REG(v, chan) 116 117 #define LPAIF_DMACTL_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, CTL) 118 #define LPAIF_DMABASE_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, BASE) 119 #define LPAIF_DMABUFF_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, BUFF) 120 #define LPAIF_DMACURR_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, CURR) 121 #define LPAIF_DMAPER_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, PER) 122 #define LPAIF_DMAPERCNT_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, PERCNT) 123 124 #define LPAIF_DMACTL_BURSTEN_MASK 0x800 125 #define LPAIF_DMACTL_BURSTEN_SHIFT 11 126 #define LPAIF_DMACTL_BURSTEN_SINGLE (0 << LPAIF_DMACTL_BURSTEN_SHIFT) 127 #define LPAIF_DMACTL_BURSTEN_INCR4 (1 << LPAIF_DMACTL_BURSTEN_SHIFT) 128 129 #define LPAIF_DMACTL_WPSCNT_MASK 0x700 130 #define LPAIF_DMACTL_WPSCNT_SHIFT 8 131 #define LPAIF_DMACTL_WPSCNT_ONE (0 << LPAIF_DMACTL_WPSCNT_SHIFT) 132 #define LPAIF_DMACTL_WPSCNT_TWO (1 << LPAIF_DMACTL_WPSCNT_SHIFT) 133 #define LPAIF_DMACTL_WPSCNT_THREE (2 << LPAIF_DMACTL_WPSCNT_SHIFT) 134 #define LPAIF_DMACTL_WPSCNT_FOUR (3 << LPAIF_DMACTL_WPSCNT_SHIFT) 135 #define LPAIF_DMACTL_WPSCNT_SIX (5 << LPAIF_DMACTL_WPSCNT_SHIFT) 136 #define LPAIF_DMACTL_WPSCNT_EIGHT (7 << LPAIF_DMACTL_WPSCNT_SHIFT) 137 138 #define LPAIF_DMACTL_AUDINTF_MASK 0x0F0 139 #define LPAIF_DMACTL_AUDINTF_SHIFT 4 140 #define LPAIF_DMACTL_AUDINTF(id) (id << LPAIF_DMACTL_AUDINTF_SHIFT) 141 142 #define LPAIF_DMACTL_FIFOWM_MASK 0x00E 143 #define LPAIF_DMACTL_FIFOWM_SHIFT 1 144 #define LPAIF_DMACTL_FIFOWM_1 (0 << LPAIF_DMACTL_FIFOWM_SHIFT) 145 #define LPAIF_DMACTL_FIFOWM_2 (1 << LPAIF_DMACTL_FIFOWM_SHIFT) 146 #define LPAIF_DMACTL_FIFOWM_3 (2 << LPAIF_DMACTL_FIFOWM_SHIFT) 147 #define LPAIF_DMACTL_FIFOWM_4 (3 << LPAIF_DMACTL_FIFOWM_SHIFT) 148 #define LPAIF_DMACTL_FIFOWM_5 (4 << LPAIF_DMACTL_FIFOWM_SHIFT) 149 #define LPAIF_DMACTL_FIFOWM_6 (5 << LPAIF_DMACTL_FIFOWM_SHIFT) 150 #define LPAIF_DMACTL_FIFOWM_7 (6 << LPAIF_DMACTL_FIFOWM_SHIFT) 151 #define LPAIF_DMACTL_FIFOWM_8 (7 << LPAIF_DMACTL_FIFOWM_SHIFT) 152 153 #define LPAIF_DMACTL_ENABLE_MASK 0x1 154 #define LPAIF_DMACTL_ENABLE_SHIFT 0 155 #define LPAIF_DMACTL_ENABLE_OFF (0 << LPAIF_DMACTL_ENABLE_SHIFT) 156 #define LPAIF_DMACTL_ENABLE_ON (1 << LPAIF_DMACTL_ENABLE_SHIFT) 157 158 #define LPAIF_DMACTL_DYNCLK_MASK BIT(12) 159 #define LPAIF_DMACTL_DYNCLK_SHIFT 12 160 #define LPAIF_DMACTL_DYNCLK_OFF (0 << LPAIF_DMACTL_DYNCLK_SHIFT) 161 #define LPAIF_DMACTL_DYNCLK_ON (1 << LPAIF_DMACTL_DYNCLK_SHIFT) 162 #endif /* __LPASS_LPAIF_REG_H__ */ 163