1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 4 * 5 * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <sound/pcm.h> 15 #include <sound/pcm_params.h> 16 #include <linux/regmap.h> 17 #include <sound/soc.h> 18 #include <sound/soc-dai.h> 19 #include "lpass-lpaif-reg.h" 20 #include "lpass.h" 21 22 #define LPASS_CPU_MAX_MI2S_LINES 4 23 #define LPASS_CPU_I2S_SD0_MASK BIT(0) 24 #define LPASS_CPU_I2S_SD1_MASK BIT(1) 25 #define LPASS_CPU_I2S_SD2_MASK BIT(2) 26 #define LPASS_CPU_I2S_SD3_MASK BIT(3) 27 #define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0) 28 #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2) 29 #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0) 30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 31 32 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev, 33 struct lpaif_i2sctl *i2sctl, struct regmap *map) 34 { 35 struct lpass_data *drvdata = dev_get_drvdata(dev); 36 struct lpass_variant *v = drvdata->variant; 37 38 i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback); 39 i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken); 40 i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode); 41 i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono); 42 i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen); 43 i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode); 44 i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono); 45 i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc); 46 i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth); 47 48 if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) || 49 IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) || 50 IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) || 51 IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) || 52 IS_ERR(i2sctl->bitwidth)) 53 return -EINVAL; 54 55 return 0; 56 } 57 58 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, 59 unsigned int freq, int dir) 60 { 61 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 62 int ret; 63 64 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); 65 if (ret) 66 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n", 67 freq, ret); 68 69 return ret; 70 } 71 72 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, 73 struct snd_soc_dai *dai) 74 { 75 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 76 int ret; 77 78 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]); 79 if (ret) { 80 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret); 81 return ret; 82 } 83 ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]); 84 if (ret) { 85 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 86 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 87 return ret; 88 } 89 return 0; 90 } 91 92 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, 93 struct snd_soc_dai *dai) 94 { 95 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 96 97 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 98 clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); 99 } 100 101 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, 102 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 103 { 104 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 105 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 106 unsigned int id = dai->driver->id; 107 snd_pcm_format_t format = params_format(params); 108 unsigned int channels = params_channels(params); 109 unsigned int rate = params_rate(params); 110 unsigned int mode; 111 unsigned int regval; 112 int bitwidth, ret; 113 114 bitwidth = snd_pcm_format_width(format); 115 if (bitwidth < 0) { 116 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth); 117 return bitwidth; 118 } 119 120 ret = regmap_fields_write(i2sctl->loopback, id, 121 LPAIF_I2SCTL_LOOPBACK_DISABLE); 122 if (ret) { 123 dev_err(dai->dev, "error updating loopback field: %d\n", ret); 124 return ret; 125 } 126 127 ret = regmap_fields_write(i2sctl->wssrc, id, 128 LPAIF_I2SCTL_WSSRC_INTERNAL); 129 if (ret) { 130 dev_err(dai->dev, "error updating wssrc field: %d\n", ret); 131 return ret; 132 } 133 134 switch (bitwidth) { 135 case 16: 136 regval = LPAIF_I2SCTL_BITWIDTH_16; 137 break; 138 case 24: 139 regval = LPAIF_I2SCTL_BITWIDTH_24; 140 break; 141 case 32: 142 regval = LPAIF_I2SCTL_BITWIDTH_32; 143 break; 144 default: 145 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth); 146 return -EINVAL; 147 } 148 149 ret = regmap_fields_write(i2sctl->bitwidth, id, regval); 150 if (ret) { 151 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret); 152 return ret; 153 } 154 155 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 156 mode = drvdata->mi2s_playback_sd_mode[id]; 157 else 158 mode = drvdata->mi2s_capture_sd_mode[id]; 159 160 if (!mode) { 161 dev_err(dai->dev, "no line is assigned\n"); 162 return -EINVAL; 163 } 164 165 switch (channels) { 166 case 1: 167 case 2: 168 switch (mode) { 169 case LPAIF_I2SCTL_MODE_QUAD01: 170 case LPAIF_I2SCTL_MODE_6CH: 171 case LPAIF_I2SCTL_MODE_8CH: 172 mode = LPAIF_I2SCTL_MODE_SD0; 173 break; 174 case LPAIF_I2SCTL_MODE_QUAD23: 175 mode = LPAIF_I2SCTL_MODE_SD2; 176 break; 177 } 178 179 break; 180 case 4: 181 if (mode < LPAIF_I2SCTL_MODE_QUAD01) { 182 dev_err(dai->dev, "cannot configure 4 channels with mode %d\n", 183 mode); 184 return -EINVAL; 185 } 186 187 switch (mode) { 188 case LPAIF_I2SCTL_MODE_6CH: 189 case LPAIF_I2SCTL_MODE_8CH: 190 mode = LPAIF_I2SCTL_MODE_QUAD01; 191 break; 192 } 193 break; 194 case 6: 195 if (mode < LPAIF_I2SCTL_MODE_6CH) { 196 dev_err(dai->dev, "cannot configure 6 channels with mode %d\n", 197 mode); 198 return -EINVAL; 199 } 200 201 switch (mode) { 202 case LPAIF_I2SCTL_MODE_8CH: 203 mode = LPAIF_I2SCTL_MODE_6CH; 204 break; 205 } 206 break; 207 case 8: 208 if (mode < LPAIF_I2SCTL_MODE_8CH) { 209 dev_err(dai->dev, "cannot configure 8 channels with mode %d\n", 210 mode); 211 return -EINVAL; 212 } 213 break; 214 default: 215 dev_err(dai->dev, "invalid channels given: %u\n", channels); 216 return -EINVAL; 217 } 218 219 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 220 ret = regmap_fields_write(i2sctl->spkmode, id, 221 LPAIF_I2SCTL_SPKMODE(mode)); 222 if (ret) { 223 dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n", 224 ret); 225 return ret; 226 } 227 if (channels >= 2) 228 ret = regmap_fields_write(i2sctl->spkmono, id, 229 LPAIF_I2SCTL_SPKMONO_STEREO); 230 else 231 ret = regmap_fields_write(i2sctl->spkmono, id, 232 LPAIF_I2SCTL_SPKMONO_MONO); 233 } else { 234 ret = regmap_fields_write(i2sctl->micmode, id, 235 LPAIF_I2SCTL_MICMODE(mode)); 236 if (ret) { 237 dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n", 238 ret); 239 return ret; 240 } 241 if (channels >= 2) 242 ret = regmap_fields_write(i2sctl->micmono, id, 243 LPAIF_I2SCTL_MICMONO_STEREO); 244 else 245 ret = regmap_fields_write(i2sctl->micmono, id, 246 LPAIF_I2SCTL_MICMONO_MONO); 247 } 248 249 if (ret) { 250 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n", 251 ret); 252 return ret; 253 } 254 255 ret = clk_set_rate(drvdata->mi2s_bit_clk[id], 256 rate * bitwidth * 2); 257 if (ret) { 258 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n", 259 rate * bitwidth * 2, ret); 260 return ret; 261 } 262 263 return 0; 264 } 265 266 static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream, 267 struct snd_soc_dai *dai) 268 { 269 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 270 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 271 unsigned int id = dai->driver->id; 272 int ret; 273 274 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 275 ret = regmap_fields_write(i2sctl->spken, id, 276 LPAIF_I2SCTL_SPKEN_ENABLE); 277 } else { 278 ret = regmap_fields_write(i2sctl->micen, id, 279 LPAIF_I2SCTL_MICEN_ENABLE); 280 } 281 282 if (ret) 283 dev_err(dai->dev, "error writing to i2sctl enable: %d\n", ret); 284 285 return ret; 286 } 287 288 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream, 289 int cmd, struct snd_soc_dai *dai) 290 { 291 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 292 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 293 unsigned int id = dai->driver->id; 294 int ret = -EINVAL; 295 296 switch (cmd) { 297 case SNDRV_PCM_TRIGGER_START: 298 case SNDRV_PCM_TRIGGER_RESUME: 299 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 300 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 301 ret = regmap_fields_write(i2sctl->spken, id, 302 LPAIF_I2SCTL_SPKEN_ENABLE); 303 } else { 304 ret = regmap_fields_write(i2sctl->micen, id, 305 LPAIF_I2SCTL_MICEN_ENABLE); 306 } 307 if (ret) 308 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 309 ret); 310 311 ret = clk_enable(drvdata->mi2s_bit_clk[id]); 312 if (ret) { 313 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 314 clk_disable(drvdata->mi2s_osr_clk[id]); 315 return ret; 316 } 317 318 break; 319 case SNDRV_PCM_TRIGGER_STOP: 320 case SNDRV_PCM_TRIGGER_SUSPEND: 321 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 322 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 323 ret = regmap_fields_write(i2sctl->spken, id, 324 LPAIF_I2SCTL_SPKEN_DISABLE); 325 } else { 326 ret = regmap_fields_write(i2sctl->micen, id, 327 LPAIF_I2SCTL_MICEN_DISABLE); 328 } 329 if (ret) 330 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 331 ret); 332 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]); 333 break; 334 } 335 336 return ret; 337 } 338 339 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = { 340 .set_sysclk = lpass_cpu_daiops_set_sysclk, 341 .startup = lpass_cpu_daiops_startup, 342 .shutdown = lpass_cpu_daiops_shutdown, 343 .hw_params = lpass_cpu_daiops_hw_params, 344 .prepare = lpass_cpu_daiops_prepare, 345 .trigger = lpass_cpu_daiops_trigger, 346 }; 347 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops); 348 349 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai) 350 { 351 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 352 int ret; 353 354 /* ensure audio hardware is disabled */ 355 ret = regmap_write(drvdata->lpaif_map, 356 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0); 357 if (ret) 358 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret); 359 360 return ret; 361 } 362 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe); 363 364 static const struct snd_soc_component_driver lpass_cpu_comp_driver = { 365 .name = "lpass-cpu", 366 }; 367 368 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg) 369 { 370 struct lpass_data *drvdata = dev_get_drvdata(dev); 371 struct lpass_variant *v = drvdata->variant; 372 int i; 373 374 for (i = 0; i < v->i2s_ports; ++i) 375 if (reg == LPAIF_I2SCTL_REG(v, i)) 376 return true; 377 378 for (i = 0; i < v->irq_ports; ++i) { 379 if (reg == LPAIF_IRQEN_REG(v, i)) 380 return true; 381 if (reg == LPAIF_IRQCLEAR_REG(v, i)) 382 return true; 383 } 384 385 for (i = 0; i < v->rdma_channels; ++i) { 386 if (reg == LPAIF_RDMACTL_REG(v, i)) 387 return true; 388 if (reg == LPAIF_RDMABASE_REG(v, i)) 389 return true; 390 if (reg == LPAIF_RDMABUFF_REG(v, i)) 391 return true; 392 if (reg == LPAIF_RDMAPER_REG(v, i)) 393 return true; 394 } 395 396 for (i = 0; i < v->wrdma_channels; ++i) { 397 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 398 return true; 399 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 400 return true; 401 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 402 return true; 403 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 404 return true; 405 } 406 407 return false; 408 } 409 410 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg) 411 { 412 struct lpass_data *drvdata = dev_get_drvdata(dev); 413 struct lpass_variant *v = drvdata->variant; 414 int i; 415 416 for (i = 0; i < v->i2s_ports; ++i) 417 if (reg == LPAIF_I2SCTL_REG(v, i)) 418 return true; 419 420 for (i = 0; i < v->irq_ports; ++i) { 421 if (reg == LPAIF_IRQEN_REG(v, i)) 422 return true; 423 if (reg == LPAIF_IRQSTAT_REG(v, i)) 424 return true; 425 } 426 427 for (i = 0; i < v->rdma_channels; ++i) { 428 if (reg == LPAIF_RDMACTL_REG(v, i)) 429 return true; 430 if (reg == LPAIF_RDMABASE_REG(v, i)) 431 return true; 432 if (reg == LPAIF_RDMABUFF_REG(v, i)) 433 return true; 434 if (reg == LPAIF_RDMACURR_REG(v, i)) 435 return true; 436 if (reg == LPAIF_RDMAPER_REG(v, i)) 437 return true; 438 } 439 440 for (i = 0; i < v->wrdma_channels; ++i) { 441 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 442 return true; 443 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 444 return true; 445 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 446 return true; 447 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 448 return true; 449 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 450 return true; 451 } 452 453 return false; 454 } 455 456 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg) 457 { 458 struct lpass_data *drvdata = dev_get_drvdata(dev); 459 struct lpass_variant *v = drvdata->variant; 460 int i; 461 462 for (i = 0; i < v->irq_ports; ++i) 463 if (reg == LPAIF_IRQSTAT_REG(v, i)) 464 return true; 465 466 for (i = 0; i < v->rdma_channels; ++i) 467 if (reg == LPAIF_RDMACURR_REG(v, i)) 468 return true; 469 470 for (i = 0; i < v->wrdma_channels; ++i) 471 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 472 return true; 473 474 return false; 475 } 476 477 static struct regmap_config lpass_cpu_regmap_config = { 478 .reg_bits = 32, 479 .reg_stride = 4, 480 .val_bits = 32, 481 .writeable_reg = lpass_cpu_regmap_writeable, 482 .readable_reg = lpass_cpu_regmap_readable, 483 .volatile_reg = lpass_cpu_regmap_volatile, 484 .cache_type = REGCACHE_FLAT, 485 }; 486 487 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map) 488 { 489 struct lpass_data *drvdata = dev_get_drvdata(dev); 490 struct lpass_variant *v = drvdata->variant; 491 unsigned int i; 492 struct lpass_hdmi_tx_ctl *tx_ctl; 493 struct regmap_field *legacy_en; 494 struct lpass_vbit_ctrl *vbit_ctl; 495 struct regmap_field *tx_parity; 496 struct lpass_dp_metadata_ctl *meta_ctl; 497 struct lpass_sstream_ctl *sstream_ctl; 498 struct regmap_field *ch_msb; 499 struct regmap_field *ch_lsb; 500 struct lpass_hdmitx_dmactl *tx_dmactl; 501 int rval; 502 503 tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL); 504 if (!tx_ctl) 505 return -ENOMEM; 506 507 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset); 508 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset); 509 drvdata->tx_ctl = tx_ctl; 510 511 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en); 512 drvdata->hdmitx_legacy_en = legacy_en; 513 514 vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL); 515 if (!vbit_ctl) 516 return -ENOMEM; 517 518 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit); 519 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream); 520 drvdata->vbit_ctl = vbit_ctl; 521 522 523 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity); 524 drvdata->hdmitx_parity_calc_en = tx_parity; 525 526 meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL); 527 if (!meta_ctl) 528 return -ENOMEM; 529 530 rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7); 531 if (rval) 532 return rval; 533 drvdata->meta_ctl = meta_ctl; 534 535 sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL); 536 if (!sstream_ctl) 537 return -ENOMEM; 538 539 rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9); 540 if (rval) 541 return rval; 542 543 drvdata->sstream_ctl = sstream_ctl; 544 545 for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) { 546 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb); 547 drvdata->hdmitx_ch_msb[i] = ch_msb; 548 549 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb); 550 drvdata->hdmitx_ch_lsb[i] = ch_lsb; 551 552 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL); 553 if (!tx_dmactl) 554 return -ENOMEM; 555 556 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs); 557 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr); 558 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel); 559 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel); 560 drvdata->hdmi_tx_dmactl[i] = tx_dmactl; 561 } 562 return 0; 563 } 564 565 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg) 566 { 567 struct lpass_data *drvdata = dev_get_drvdata(dev); 568 struct lpass_variant *v = drvdata->variant; 569 int i; 570 571 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 572 return true; 573 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 574 return true; 575 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 576 return true; 577 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 578 return true; 579 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 580 return true; 581 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 582 return true; 583 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 584 return true; 585 if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v)) 586 return true; 587 588 for (i = 0; i < v->hdmi_rdma_channels; i++) { 589 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 590 return true; 591 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 592 return true; 593 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 594 return true; 595 } 596 597 for (i = 0; i < v->rdma_channels; ++i) { 598 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 599 return true; 600 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 601 return true; 602 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 603 return true; 604 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 605 return true; 606 } 607 return false; 608 } 609 610 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg) 611 { 612 struct lpass_data *drvdata = dev_get_drvdata(dev); 613 struct lpass_variant *v = drvdata->variant; 614 int i; 615 616 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 617 return true; 618 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 619 return true; 620 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 621 return true; 622 623 for (i = 0; i < v->hdmi_rdma_channels; i++) { 624 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 625 return true; 626 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 627 return true; 628 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 629 return true; 630 } 631 632 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 633 return true; 634 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 635 return true; 636 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 637 return true; 638 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 639 return true; 640 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 641 return true; 642 643 for (i = 0; i < v->rdma_channels; ++i) { 644 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 645 return true; 646 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 647 return true; 648 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 649 return true; 650 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 651 return true; 652 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 653 return true; 654 } 655 656 return false; 657 } 658 659 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg) 660 { 661 struct lpass_data *drvdata = dev_get_drvdata(dev); 662 struct lpass_variant *v = drvdata->variant; 663 int i; 664 665 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 666 return true; 667 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 668 return true; 669 670 for (i = 0; i < v->rdma_channels; ++i) { 671 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 672 return true; 673 } 674 return false; 675 } 676 677 struct regmap_config lpass_hdmi_regmap_config = { 678 .reg_bits = 32, 679 .reg_stride = 4, 680 .val_bits = 32, 681 .writeable_reg = lpass_hdmi_regmap_writeable, 682 .readable_reg = lpass_hdmi_regmap_readable, 683 .volatile_reg = lpass_hdmi_regmap_volatile, 684 .cache_type = REGCACHE_FLAT, 685 }; 686 687 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev, 688 struct device_node *node, 689 const char *name) 690 { 691 unsigned int lines[LPASS_CPU_MAX_MI2S_LINES]; 692 unsigned int sd_line_mask = 0; 693 int num_lines, i; 694 695 num_lines = of_property_read_variable_u32_array(node, name, lines, 0, 696 LPASS_CPU_MAX_MI2S_LINES); 697 if (num_lines < 0) 698 return LPAIF_I2SCTL_MODE_NONE; 699 700 for (i = 0; i < num_lines; i++) 701 sd_line_mask |= BIT(lines[i]); 702 703 switch (sd_line_mask) { 704 case LPASS_CPU_I2S_SD0_MASK: 705 return LPAIF_I2SCTL_MODE_SD0; 706 case LPASS_CPU_I2S_SD1_MASK: 707 return LPAIF_I2SCTL_MODE_SD1; 708 case LPASS_CPU_I2S_SD2_MASK: 709 return LPAIF_I2SCTL_MODE_SD2; 710 case LPASS_CPU_I2S_SD3_MASK: 711 return LPAIF_I2SCTL_MODE_SD3; 712 case LPASS_CPU_I2S_SD0_1_MASK: 713 return LPAIF_I2SCTL_MODE_QUAD01; 714 case LPASS_CPU_I2S_SD2_3_MASK: 715 return LPAIF_I2SCTL_MODE_QUAD23; 716 case LPASS_CPU_I2S_SD0_1_2_MASK: 717 return LPAIF_I2SCTL_MODE_6CH; 718 case LPASS_CPU_I2S_SD0_1_2_3_MASK: 719 return LPAIF_I2SCTL_MODE_8CH; 720 default: 721 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask); 722 return LPAIF_I2SCTL_MODE_NONE; 723 } 724 } 725 726 static void of_lpass_cpu_parse_dai_data(struct device *dev, 727 struct lpass_data *data) 728 { 729 struct device_node *node; 730 int ret, id; 731 732 /* Allow all channels by default for backwards compatibility */ 733 for (id = 0; id < data->variant->num_dai; id++) { 734 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 735 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 736 } 737 738 for_each_child_of_node(dev->of_node, node) { 739 ret = of_property_read_u32(node, "reg", &id); 740 if (ret || id < 0 || id >= data->variant->num_dai) { 741 dev_err(dev, "valid dai id not found: %d\n", ret); 742 continue; 743 } 744 if (id == LPASS_DP_RX) { 745 data->hdmi_port_enable = 1; 746 dev_err(dev, "HDMI Port is enabled: %d\n", id); 747 } else { 748 data->mi2s_playback_sd_mode[id] = 749 of_lpass_cpu_parse_sd_lines(dev, node, 750 "qcom,playback-sd-lines"); 751 data->mi2s_capture_sd_mode[id] = 752 of_lpass_cpu_parse_sd_lines(dev, node, 753 "qcom,capture-sd-lines"); 754 } 755 } 756 } 757 758 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) 759 { 760 struct lpass_data *drvdata; 761 struct device_node *dsp_of_node; 762 struct resource *res; 763 struct lpass_variant *variant; 764 struct device *dev = &pdev->dev; 765 const struct of_device_id *match; 766 int ret, i, dai_id; 767 768 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); 769 if (dsp_of_node) { 770 dev_err(dev, "DSP exists and holds audio resources\n"); 771 return -EBUSY; 772 } 773 774 drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL); 775 if (!drvdata) 776 return -ENOMEM; 777 platform_set_drvdata(pdev, drvdata); 778 779 match = of_match_device(dev->driver->of_match_table, dev); 780 if (!match || !match->data) 781 return -EINVAL; 782 783 drvdata->variant = (struct lpass_variant *)match->data; 784 variant = drvdata->variant; 785 786 of_lpass_cpu_parse_dai_data(dev, drvdata); 787 788 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif"); 789 790 drvdata->lpaif = devm_ioremap_resource(dev, res); 791 if (IS_ERR((void const __force *)drvdata->lpaif)) { 792 dev_err(dev, "error mapping reg resource: %ld\n", 793 PTR_ERR((void const __force *)drvdata->lpaif)); 794 return PTR_ERR((void const __force *)drvdata->lpaif); 795 } 796 797 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant, 798 variant->wrdma_channels + 799 variant->wrdma_channel_start); 800 801 drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif, 802 &lpass_cpu_regmap_config); 803 if (IS_ERR(drvdata->lpaif_map)) { 804 dev_err(dev, "error initializing regmap: %ld\n", 805 PTR_ERR(drvdata->lpaif_map)); 806 return PTR_ERR(drvdata->lpaif_map); 807 } 808 809 if (drvdata->hdmi_port_enable) { 810 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif"); 811 812 drvdata->hdmiif = devm_ioremap_resource(dev, res); 813 if (IS_ERR((void const __force *)drvdata->hdmiif)) { 814 dev_err(dev, "error mapping reg resource: %ld\n", 815 PTR_ERR((void const __force *)drvdata->hdmiif)); 816 return PTR_ERR((void const __force *)drvdata->hdmiif); 817 } 818 819 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant, 820 variant->hdmi_rdma_channels); 821 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif, 822 &lpass_hdmi_regmap_config); 823 if (IS_ERR(drvdata->hdmiif_map)) { 824 dev_err(dev, "error initializing regmap: %ld\n", 825 PTR_ERR(drvdata->hdmiif_map)); 826 return PTR_ERR(drvdata->hdmiif_map); 827 } 828 } 829 830 if (variant->init) { 831 ret = variant->init(pdev); 832 if (ret) { 833 dev_err(dev, "error initializing variant: %d\n", ret); 834 return ret; 835 } 836 } 837 838 for (i = 0; i < variant->num_dai; i++) { 839 dai_id = variant->dai_driver[i].id; 840 if (dai_id == LPASS_DP_RX) 841 continue; 842 843 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(dev, 844 variant->dai_osr_clk_names[i]); 845 if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) { 846 dev_warn(dev, 847 "%s() error getting optional %s: %ld\n", 848 __func__, 849 variant->dai_osr_clk_names[i], 850 PTR_ERR(drvdata->mi2s_osr_clk[dai_id])); 851 852 drvdata->mi2s_osr_clk[dai_id] = NULL; 853 } 854 855 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev, 856 variant->dai_bit_clk_names[i]); 857 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) { 858 dev_err(dev, 859 "error getting %s: %ld\n", 860 variant->dai_bit_clk_names[i], 861 PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); 862 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); 863 } 864 } 865 866 /* Allocation for i2sctl regmap fields */ 867 drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl), 868 GFP_KERNEL); 869 870 /* Initialize bitfields for dai I2SCTL register */ 871 ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl, 872 drvdata->lpaif_map); 873 if (ret) { 874 dev_err(dev, "error init i2sctl field: %d\n", ret); 875 return ret; 876 } 877 878 if (drvdata->hdmi_port_enable) { 879 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map); 880 if (ret) { 881 dev_err(dev, "%s error hdmi init failed\n", __func__); 882 return ret; 883 } 884 } 885 ret = devm_snd_soc_register_component(dev, 886 &lpass_cpu_comp_driver, 887 variant->dai_driver, 888 variant->num_dai); 889 if (ret) { 890 dev_err(dev, "error registering cpu driver: %d\n", ret); 891 goto err; 892 } 893 894 ret = asoc_qcom_lpass_platform_register(pdev); 895 if (ret) { 896 dev_err(dev, "error registering platform driver: %d\n", ret); 897 goto err; 898 } 899 900 err: 901 return ret; 902 } 903 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe); 904 905 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev) 906 { 907 struct lpass_data *drvdata = platform_get_drvdata(pdev); 908 909 if (drvdata->variant->exit) 910 drvdata->variant->exit(pdev); 911 912 913 return 0; 914 } 915 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove); 916 917 MODULE_DESCRIPTION("QTi LPASS CPU Driver"); 918 MODULE_LICENSE("GPL v2"); 919