1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 4 * 5 * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <sound/pcm.h> 15 #include <sound/pcm_params.h> 16 #include <linux/regmap.h> 17 #include <sound/soc.h> 18 #include <sound/soc-dai.h> 19 #include "lpass-lpaif-reg.h" 20 #include "lpass.h" 21 22 #define LPASS_CPU_MAX_MI2S_LINES 4 23 #define LPASS_CPU_I2S_SD0_MASK BIT(0) 24 #define LPASS_CPU_I2S_SD1_MASK BIT(1) 25 #define LPASS_CPU_I2S_SD2_MASK BIT(2) 26 #define LPASS_CPU_I2S_SD3_MASK BIT(3) 27 #define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0) 28 #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2) 29 #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0) 30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 31 32 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev, 33 struct lpaif_i2sctl *i2sctl, struct regmap *map) 34 { 35 struct lpass_data *drvdata = dev_get_drvdata(dev); 36 struct lpass_variant *v = drvdata->variant; 37 38 i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback); 39 i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken); 40 i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode); 41 i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono); 42 i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen); 43 i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode); 44 i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono); 45 i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc); 46 i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth); 47 48 if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) || 49 IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) || 50 IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) || 51 IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) || 52 IS_ERR(i2sctl->bitwidth)) 53 return -EINVAL; 54 55 return 0; 56 } 57 58 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, 59 unsigned int freq, int dir) 60 { 61 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 62 int ret; 63 64 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); 65 if (ret) 66 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n", 67 freq, ret); 68 69 return ret; 70 } 71 72 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, 73 struct snd_soc_dai *dai) 74 { 75 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 76 int ret; 77 78 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]); 79 if (ret) { 80 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret); 81 return ret; 82 } 83 return 0; 84 } 85 86 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, 87 struct snd_soc_dai *dai) 88 { 89 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 90 91 clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); 92 93 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 94 } 95 96 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, 97 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 98 { 99 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 100 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 101 unsigned int id = dai->driver->id; 102 snd_pcm_format_t format = params_format(params); 103 unsigned int channels = params_channels(params); 104 unsigned int rate = params_rate(params); 105 unsigned int mode; 106 unsigned int regval; 107 int bitwidth, ret; 108 109 bitwidth = snd_pcm_format_width(format); 110 if (bitwidth < 0) { 111 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth); 112 return bitwidth; 113 } 114 115 ret = regmap_fields_write(i2sctl->loopback, id, 116 LPAIF_I2SCTL_LOOPBACK_DISABLE); 117 if (ret) { 118 dev_err(dai->dev, "error updating loopback field: %d\n", ret); 119 return ret; 120 } 121 122 ret = regmap_fields_write(i2sctl->wssrc, id, 123 LPAIF_I2SCTL_WSSRC_INTERNAL); 124 if (ret) { 125 dev_err(dai->dev, "error updating wssrc field: %d\n", ret); 126 return ret; 127 } 128 129 switch (bitwidth) { 130 case 16: 131 regval = LPAIF_I2SCTL_BITWIDTH_16; 132 break; 133 case 24: 134 regval = LPAIF_I2SCTL_BITWIDTH_24; 135 break; 136 case 32: 137 regval = LPAIF_I2SCTL_BITWIDTH_32; 138 break; 139 default: 140 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth); 141 return -EINVAL; 142 } 143 144 ret = regmap_fields_write(i2sctl->bitwidth, id, regval); 145 if (ret) { 146 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret); 147 return ret; 148 } 149 150 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 151 mode = drvdata->mi2s_playback_sd_mode[id]; 152 else 153 mode = drvdata->mi2s_capture_sd_mode[id]; 154 155 if (!mode) { 156 dev_err(dai->dev, "no line is assigned\n"); 157 return -EINVAL; 158 } 159 160 switch (channels) { 161 case 1: 162 case 2: 163 switch (mode) { 164 case LPAIF_I2SCTL_MODE_QUAD01: 165 case LPAIF_I2SCTL_MODE_6CH: 166 case LPAIF_I2SCTL_MODE_8CH: 167 mode = LPAIF_I2SCTL_MODE_SD0; 168 break; 169 case LPAIF_I2SCTL_MODE_QUAD23: 170 mode = LPAIF_I2SCTL_MODE_SD2; 171 break; 172 } 173 174 break; 175 case 4: 176 if (mode < LPAIF_I2SCTL_MODE_QUAD01) { 177 dev_err(dai->dev, "cannot configure 4 channels with mode %d\n", 178 mode); 179 return -EINVAL; 180 } 181 182 switch (mode) { 183 case LPAIF_I2SCTL_MODE_6CH: 184 case LPAIF_I2SCTL_MODE_8CH: 185 mode = LPAIF_I2SCTL_MODE_QUAD01; 186 break; 187 } 188 break; 189 case 6: 190 if (mode < LPAIF_I2SCTL_MODE_6CH) { 191 dev_err(dai->dev, "cannot configure 6 channels with mode %d\n", 192 mode); 193 return -EINVAL; 194 } 195 196 switch (mode) { 197 case LPAIF_I2SCTL_MODE_8CH: 198 mode = LPAIF_I2SCTL_MODE_6CH; 199 break; 200 } 201 break; 202 case 8: 203 if (mode < LPAIF_I2SCTL_MODE_8CH) { 204 dev_err(dai->dev, "cannot configure 8 channels with mode %d\n", 205 mode); 206 return -EINVAL; 207 } 208 break; 209 default: 210 dev_err(dai->dev, "invalid channels given: %u\n", channels); 211 return -EINVAL; 212 } 213 214 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 215 ret = regmap_fields_write(i2sctl->spkmode, id, 216 LPAIF_I2SCTL_SPKMODE(mode)); 217 if (ret) { 218 dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n", 219 ret); 220 return ret; 221 } 222 if (channels >= 2) 223 ret = regmap_fields_write(i2sctl->spkmono, id, 224 LPAIF_I2SCTL_SPKMONO_STEREO); 225 else 226 ret = regmap_fields_write(i2sctl->spkmono, id, 227 LPAIF_I2SCTL_SPKMONO_MONO); 228 } else { 229 ret = regmap_fields_write(i2sctl->micmode, id, 230 LPAIF_I2SCTL_MICMODE(mode)); 231 if (ret) { 232 dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n", 233 ret); 234 return ret; 235 } 236 if (channels >= 2) 237 ret = regmap_fields_write(i2sctl->micmono, id, 238 LPAIF_I2SCTL_MICMONO_STEREO); 239 else 240 ret = regmap_fields_write(i2sctl->micmono, id, 241 LPAIF_I2SCTL_MICMONO_MONO); 242 } 243 244 if (ret) { 245 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n", 246 ret); 247 return ret; 248 } 249 250 ret = clk_set_rate(drvdata->mi2s_bit_clk[id], 251 rate * bitwidth * 2); 252 if (ret) { 253 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n", 254 rate * bitwidth * 2, ret); 255 return ret; 256 } 257 258 return 0; 259 } 260 261 static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream, 262 struct snd_soc_dai *dai) 263 { 264 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 265 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 266 unsigned int id = dai->driver->id; 267 int ret; 268 269 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 270 ret = regmap_fields_write(i2sctl->spken, id, 271 LPAIF_I2SCTL_SPKEN_ENABLE); 272 } else { 273 ret = regmap_fields_write(i2sctl->micen, id, 274 LPAIF_I2SCTL_MICEN_ENABLE); 275 } 276 277 if (ret) 278 dev_err(dai->dev, "error writing to i2sctl enable: %d\n", ret); 279 280 return ret; 281 } 282 283 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream, 284 int cmd, struct snd_soc_dai *dai) 285 { 286 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 287 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 288 unsigned int id = dai->driver->id; 289 int ret = -EINVAL; 290 291 switch (cmd) { 292 case SNDRV_PCM_TRIGGER_START: 293 case SNDRV_PCM_TRIGGER_RESUME: 294 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 295 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 296 ret = regmap_fields_write(i2sctl->spken, id, 297 LPAIF_I2SCTL_SPKEN_ENABLE); 298 } else { 299 ret = regmap_fields_write(i2sctl->micen, id, 300 LPAIF_I2SCTL_MICEN_ENABLE); 301 } 302 if (ret) 303 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 304 ret); 305 306 ret = clk_prepare_enable(drvdata->mi2s_bit_clk[id]); 307 if (ret) { 308 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 309 clk_disable_unprepare(drvdata->mi2s_osr_clk[id]); 310 return ret; 311 } 312 313 break; 314 case SNDRV_PCM_TRIGGER_STOP: 315 case SNDRV_PCM_TRIGGER_SUSPEND: 316 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 317 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 318 ret = regmap_fields_write(i2sctl->spken, id, 319 LPAIF_I2SCTL_SPKEN_DISABLE); 320 } else { 321 ret = regmap_fields_write(i2sctl->micen, id, 322 LPAIF_I2SCTL_MICEN_DISABLE); 323 } 324 if (ret) 325 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 326 ret); 327 break; 328 } 329 330 return ret; 331 } 332 333 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = { 334 .set_sysclk = lpass_cpu_daiops_set_sysclk, 335 .startup = lpass_cpu_daiops_startup, 336 .shutdown = lpass_cpu_daiops_shutdown, 337 .hw_params = lpass_cpu_daiops_hw_params, 338 .prepare = lpass_cpu_daiops_prepare, 339 .trigger = lpass_cpu_daiops_trigger, 340 }; 341 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops); 342 343 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai) 344 { 345 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 346 int ret; 347 348 /* ensure audio hardware is disabled */ 349 ret = regmap_write(drvdata->lpaif_map, 350 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0); 351 if (ret) 352 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret); 353 354 return ret; 355 } 356 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe); 357 358 static const struct snd_soc_component_driver lpass_cpu_comp_driver = { 359 .name = "lpass-cpu", 360 }; 361 362 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg) 363 { 364 struct lpass_data *drvdata = dev_get_drvdata(dev); 365 struct lpass_variant *v = drvdata->variant; 366 int i; 367 368 for (i = 0; i < v->i2s_ports; ++i) 369 if (reg == LPAIF_I2SCTL_REG(v, i)) 370 return true; 371 372 for (i = 0; i < v->irq_ports; ++i) { 373 if (reg == LPAIF_IRQEN_REG(v, i)) 374 return true; 375 if (reg == LPAIF_IRQCLEAR_REG(v, i)) 376 return true; 377 } 378 379 for (i = 0; i < v->rdma_channels; ++i) { 380 if (reg == LPAIF_RDMACTL_REG(v, i)) 381 return true; 382 if (reg == LPAIF_RDMABASE_REG(v, i)) 383 return true; 384 if (reg == LPAIF_RDMABUFF_REG(v, i)) 385 return true; 386 if (reg == LPAIF_RDMAPER_REG(v, i)) 387 return true; 388 } 389 390 for (i = 0; i < v->wrdma_channels; ++i) { 391 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 392 return true; 393 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 394 return true; 395 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 396 return true; 397 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 398 return true; 399 } 400 401 return false; 402 } 403 404 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg) 405 { 406 struct lpass_data *drvdata = dev_get_drvdata(dev); 407 struct lpass_variant *v = drvdata->variant; 408 int i; 409 410 for (i = 0; i < v->i2s_ports; ++i) 411 if (reg == LPAIF_I2SCTL_REG(v, i)) 412 return true; 413 414 for (i = 0; i < v->irq_ports; ++i) { 415 if (reg == LPAIF_IRQEN_REG(v, i)) 416 return true; 417 if (reg == LPAIF_IRQSTAT_REG(v, i)) 418 return true; 419 } 420 421 for (i = 0; i < v->rdma_channels; ++i) { 422 if (reg == LPAIF_RDMACTL_REG(v, i)) 423 return true; 424 if (reg == LPAIF_RDMABASE_REG(v, i)) 425 return true; 426 if (reg == LPAIF_RDMABUFF_REG(v, i)) 427 return true; 428 if (reg == LPAIF_RDMACURR_REG(v, i)) 429 return true; 430 if (reg == LPAIF_RDMAPER_REG(v, i)) 431 return true; 432 } 433 434 for (i = 0; i < v->wrdma_channels; ++i) { 435 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 436 return true; 437 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 438 return true; 439 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 440 return true; 441 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 442 return true; 443 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 444 return true; 445 } 446 447 return false; 448 } 449 450 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg) 451 { 452 struct lpass_data *drvdata = dev_get_drvdata(dev); 453 struct lpass_variant *v = drvdata->variant; 454 int i; 455 456 for (i = 0; i < v->irq_ports; ++i) 457 if (reg == LPAIF_IRQSTAT_REG(v, i)) 458 return true; 459 460 for (i = 0; i < v->rdma_channels; ++i) 461 if (reg == LPAIF_RDMACURR_REG(v, i)) 462 return true; 463 464 for (i = 0; i < v->wrdma_channels; ++i) 465 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 466 return true; 467 468 return false; 469 } 470 471 static struct regmap_config lpass_cpu_regmap_config = { 472 .reg_bits = 32, 473 .reg_stride = 4, 474 .val_bits = 32, 475 .writeable_reg = lpass_cpu_regmap_writeable, 476 .readable_reg = lpass_cpu_regmap_readable, 477 .volatile_reg = lpass_cpu_regmap_volatile, 478 .cache_type = REGCACHE_FLAT, 479 }; 480 481 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map) 482 { 483 struct lpass_data *drvdata = dev_get_drvdata(dev); 484 struct lpass_variant *v = drvdata->variant; 485 unsigned int i; 486 struct lpass_hdmi_tx_ctl *tx_ctl; 487 struct regmap_field *legacy_en; 488 struct lpass_vbit_ctrl *vbit_ctl; 489 struct regmap_field *tx_parity; 490 struct lpass_dp_metadata_ctl *meta_ctl; 491 struct lpass_sstream_ctl *sstream_ctl; 492 struct regmap_field *ch_msb; 493 struct regmap_field *ch_lsb; 494 struct lpass_hdmitx_dmactl *tx_dmactl; 495 int rval; 496 497 tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL); 498 if (!tx_ctl) 499 return -ENOMEM; 500 501 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset); 502 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset); 503 drvdata->tx_ctl = tx_ctl; 504 505 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en); 506 drvdata->hdmitx_legacy_en = legacy_en; 507 508 vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL); 509 if (!vbit_ctl) 510 return -ENOMEM; 511 512 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit); 513 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream); 514 drvdata->vbit_ctl = vbit_ctl; 515 516 517 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity); 518 drvdata->hdmitx_parity_calc_en = tx_parity; 519 520 meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL); 521 if (!meta_ctl) 522 return -ENOMEM; 523 524 rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7); 525 if (rval) 526 return rval; 527 drvdata->meta_ctl = meta_ctl; 528 529 sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL); 530 if (!sstream_ctl) 531 return -ENOMEM; 532 533 rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9); 534 if (rval) 535 return rval; 536 537 drvdata->sstream_ctl = sstream_ctl; 538 539 for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) { 540 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb); 541 drvdata->hdmitx_ch_msb[i] = ch_msb; 542 543 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb); 544 drvdata->hdmitx_ch_lsb[i] = ch_lsb; 545 546 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL); 547 if (!tx_dmactl) 548 return -ENOMEM; 549 550 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs); 551 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr); 552 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel); 553 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel); 554 drvdata->hdmi_tx_dmactl[i] = tx_dmactl; 555 } 556 return 0; 557 } 558 559 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg) 560 { 561 struct lpass_data *drvdata = dev_get_drvdata(dev); 562 struct lpass_variant *v = drvdata->variant; 563 int i; 564 565 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 566 return true; 567 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 568 return true; 569 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 570 return true; 571 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 572 return true; 573 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 574 return true; 575 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 576 return true; 577 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 578 return true; 579 if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v)) 580 return true; 581 582 for (i = 0; i < v->hdmi_rdma_channels; i++) { 583 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 584 return true; 585 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 586 return true; 587 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 588 return true; 589 } 590 591 for (i = 0; i < v->rdma_channels; ++i) { 592 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 593 return true; 594 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 595 return true; 596 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 597 return true; 598 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 599 return true; 600 } 601 return false; 602 } 603 604 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg) 605 { 606 struct lpass_data *drvdata = dev_get_drvdata(dev); 607 struct lpass_variant *v = drvdata->variant; 608 int i; 609 610 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 611 return true; 612 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 613 return true; 614 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 615 return true; 616 617 for (i = 0; i < v->hdmi_rdma_channels; i++) { 618 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 619 return true; 620 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 621 return true; 622 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 623 return true; 624 } 625 626 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 627 return true; 628 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 629 return true; 630 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 631 return true; 632 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 633 return true; 634 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 635 return true; 636 637 for (i = 0; i < v->rdma_channels; ++i) { 638 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 639 return true; 640 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 641 return true; 642 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 643 return true; 644 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 645 return true; 646 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 647 return true; 648 } 649 650 return false; 651 } 652 653 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg) 654 { 655 struct lpass_data *drvdata = dev_get_drvdata(dev); 656 struct lpass_variant *v = drvdata->variant; 657 int i; 658 659 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 660 return true; 661 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 662 return true; 663 664 for (i = 0; i < v->rdma_channels; ++i) { 665 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 666 return true; 667 } 668 return false; 669 } 670 671 struct regmap_config lpass_hdmi_regmap_config = { 672 .reg_bits = 32, 673 .reg_stride = 4, 674 .val_bits = 32, 675 .writeable_reg = lpass_hdmi_regmap_writeable, 676 .readable_reg = lpass_hdmi_regmap_readable, 677 .volatile_reg = lpass_hdmi_regmap_volatile, 678 .cache_type = REGCACHE_FLAT, 679 }; 680 681 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev, 682 struct device_node *node, 683 const char *name) 684 { 685 unsigned int lines[LPASS_CPU_MAX_MI2S_LINES]; 686 unsigned int sd_line_mask = 0; 687 int num_lines, i; 688 689 num_lines = of_property_read_variable_u32_array(node, name, lines, 0, 690 LPASS_CPU_MAX_MI2S_LINES); 691 if (num_lines < 0) 692 return LPAIF_I2SCTL_MODE_NONE; 693 694 for (i = 0; i < num_lines; i++) 695 sd_line_mask |= BIT(lines[i]); 696 697 switch (sd_line_mask) { 698 case LPASS_CPU_I2S_SD0_MASK: 699 return LPAIF_I2SCTL_MODE_SD0; 700 case LPASS_CPU_I2S_SD1_MASK: 701 return LPAIF_I2SCTL_MODE_SD1; 702 case LPASS_CPU_I2S_SD2_MASK: 703 return LPAIF_I2SCTL_MODE_SD2; 704 case LPASS_CPU_I2S_SD3_MASK: 705 return LPAIF_I2SCTL_MODE_SD3; 706 case LPASS_CPU_I2S_SD0_1_MASK: 707 return LPAIF_I2SCTL_MODE_QUAD01; 708 case LPASS_CPU_I2S_SD2_3_MASK: 709 return LPAIF_I2SCTL_MODE_QUAD23; 710 case LPASS_CPU_I2S_SD0_1_2_MASK: 711 return LPAIF_I2SCTL_MODE_6CH; 712 case LPASS_CPU_I2S_SD0_1_2_3_MASK: 713 return LPAIF_I2SCTL_MODE_8CH; 714 default: 715 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask); 716 return LPAIF_I2SCTL_MODE_NONE; 717 } 718 } 719 720 static void of_lpass_cpu_parse_dai_data(struct device *dev, 721 struct lpass_data *data) 722 { 723 struct device_node *node; 724 int ret, id; 725 726 /* Allow all channels by default for backwards compatibility */ 727 for (id = 0; id < data->variant->num_dai; id++) { 728 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 729 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 730 } 731 732 for_each_child_of_node(dev->of_node, node) { 733 ret = of_property_read_u32(node, "reg", &id); 734 if (ret || id < 0 || id >= data->variant->num_dai) { 735 dev_err(dev, "valid dai id not found: %d\n", ret); 736 continue; 737 } 738 if (id == LPASS_DP_RX) { 739 data->hdmi_port_enable = 1; 740 dev_err(dev, "HDMI Port is enabled: %d\n", id); 741 } else { 742 data->mi2s_playback_sd_mode[id] = 743 of_lpass_cpu_parse_sd_lines(dev, node, 744 "qcom,playback-sd-lines"); 745 data->mi2s_capture_sd_mode[id] = 746 of_lpass_cpu_parse_sd_lines(dev, node, 747 "qcom,capture-sd-lines"); 748 } 749 } 750 } 751 752 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) 753 { 754 struct lpass_data *drvdata; 755 struct device_node *dsp_of_node; 756 struct resource *res; 757 struct lpass_variant *variant; 758 struct device *dev = &pdev->dev; 759 const struct of_device_id *match; 760 int ret, i, dai_id; 761 762 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); 763 if (dsp_of_node) { 764 dev_err(dev, "DSP exists and holds audio resources\n"); 765 return -EBUSY; 766 } 767 768 drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL); 769 if (!drvdata) 770 return -ENOMEM; 771 platform_set_drvdata(pdev, drvdata); 772 773 match = of_match_device(dev->driver->of_match_table, dev); 774 if (!match || !match->data) 775 return -EINVAL; 776 777 drvdata->variant = (struct lpass_variant *)match->data; 778 variant = drvdata->variant; 779 780 of_lpass_cpu_parse_dai_data(dev, drvdata); 781 782 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif"); 783 784 drvdata->lpaif = devm_ioremap_resource(dev, res); 785 if (IS_ERR((void const __force *)drvdata->lpaif)) { 786 dev_err(dev, "error mapping reg resource: %ld\n", 787 PTR_ERR((void const __force *)drvdata->lpaif)); 788 return PTR_ERR((void const __force *)drvdata->lpaif); 789 } 790 791 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant, 792 variant->wrdma_channels + 793 variant->wrdma_channel_start); 794 795 drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif, 796 &lpass_cpu_regmap_config); 797 if (IS_ERR(drvdata->lpaif_map)) { 798 dev_err(dev, "error initializing regmap: %ld\n", 799 PTR_ERR(drvdata->lpaif_map)); 800 return PTR_ERR(drvdata->lpaif_map); 801 } 802 803 if (drvdata->hdmi_port_enable) { 804 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif"); 805 806 drvdata->hdmiif = devm_ioremap_resource(dev, res); 807 if (IS_ERR((void const __force *)drvdata->hdmiif)) { 808 dev_err(dev, "error mapping reg resource: %ld\n", 809 PTR_ERR((void const __force *)drvdata->hdmiif)); 810 return PTR_ERR((void const __force *)drvdata->hdmiif); 811 } 812 813 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant, 814 variant->hdmi_rdma_channels); 815 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif, 816 &lpass_hdmi_regmap_config); 817 if (IS_ERR(drvdata->hdmiif_map)) { 818 dev_err(dev, "error initializing regmap: %ld\n", 819 PTR_ERR(drvdata->hdmiif_map)); 820 return PTR_ERR(drvdata->hdmiif_map); 821 } 822 } 823 824 if (variant->init) { 825 ret = variant->init(pdev); 826 if (ret) { 827 dev_err(dev, "error initializing variant: %d\n", ret); 828 return ret; 829 } 830 } 831 832 for (i = 0; i < variant->num_dai; i++) { 833 dai_id = variant->dai_driver[i].id; 834 if (dai_id == LPASS_DP_RX) 835 continue; 836 837 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(dev, 838 variant->dai_osr_clk_names[i]); 839 if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) { 840 dev_warn(dev, 841 "%s() error getting optional %s: %ld\n", 842 __func__, 843 variant->dai_osr_clk_names[i], 844 PTR_ERR(drvdata->mi2s_osr_clk[dai_id])); 845 846 drvdata->mi2s_osr_clk[dai_id] = NULL; 847 } 848 849 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev, 850 variant->dai_bit_clk_names[i]); 851 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) { 852 dev_err(dev, 853 "error getting %s: %ld\n", 854 variant->dai_bit_clk_names[i], 855 PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); 856 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); 857 } 858 } 859 860 /* Allocation for i2sctl regmap fields */ 861 drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl), 862 GFP_KERNEL); 863 864 /* Initialize bitfields for dai I2SCTL register */ 865 ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl, 866 drvdata->lpaif_map); 867 if (ret) { 868 dev_err(dev, "error init i2sctl field: %d\n", ret); 869 return ret; 870 } 871 872 if (drvdata->hdmi_port_enable) { 873 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map); 874 if (ret) { 875 dev_err(dev, "%s error hdmi init failed\n", __func__); 876 return ret; 877 } 878 } 879 ret = devm_snd_soc_register_component(dev, 880 &lpass_cpu_comp_driver, 881 variant->dai_driver, 882 variant->num_dai); 883 if (ret) { 884 dev_err(dev, "error registering cpu driver: %d\n", ret); 885 goto err; 886 } 887 888 ret = asoc_qcom_lpass_platform_register(pdev); 889 if (ret) { 890 dev_err(dev, "error registering platform driver: %d\n", ret); 891 goto err; 892 } 893 894 err: 895 return ret; 896 } 897 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe); 898 899 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev) 900 { 901 struct lpass_data *drvdata = platform_get_drvdata(pdev); 902 903 if (drvdata->variant->exit) 904 drvdata->variant->exit(pdev); 905 906 907 return 0; 908 } 909 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove); 910 911 MODULE_DESCRIPTION("QTi LPASS CPU Driver"); 912 MODULE_LICENSE("GPL v2"); 913