1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 4 * 5 * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <sound/pcm.h> 15 #include <sound/pcm_params.h> 16 #include <linux/regmap.h> 17 #include <sound/soc.h> 18 #include <sound/soc-dai.h> 19 #include "lpass-lpaif-reg.h" 20 #include "lpass.h" 21 22 #define LPASS_CPU_MAX_MI2S_LINES 4 23 #define LPASS_CPU_I2S_SD0_MASK BIT(0) 24 #define LPASS_CPU_I2S_SD1_MASK BIT(1) 25 #define LPASS_CPU_I2S_SD2_MASK BIT(2) 26 #define LPASS_CPU_I2S_SD3_MASK BIT(3) 27 #define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0) 28 #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2) 29 #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0) 30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 31 32 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev, 33 struct lpaif_i2sctl *i2sctl, struct regmap *map) 34 { 35 struct lpass_data *drvdata = dev_get_drvdata(dev); 36 struct lpass_variant *v = drvdata->variant; 37 38 i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback); 39 i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken); 40 i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode); 41 i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono); 42 i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen); 43 i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode); 44 i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono); 45 i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc); 46 i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth); 47 48 if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) || 49 IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) || 50 IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) || 51 IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) || 52 IS_ERR(i2sctl->bitwidth)) 53 return -EINVAL; 54 55 return 0; 56 } 57 58 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, 59 unsigned int freq, int dir) 60 { 61 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 62 int ret; 63 64 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); 65 if (ret) 66 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n", 67 freq, ret); 68 69 return ret; 70 } 71 72 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, 73 struct snd_soc_dai *dai) 74 { 75 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 76 int ret; 77 78 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]); 79 if (ret) { 80 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret); 81 return ret; 82 } 83 ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]); 84 if (ret) { 85 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 86 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 87 return ret; 88 } 89 return 0; 90 } 91 92 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, 93 struct snd_soc_dai *dai) 94 { 95 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 96 97 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 98 clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); 99 } 100 101 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, 102 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 103 { 104 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 105 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 106 unsigned int id = dai->driver->id; 107 snd_pcm_format_t format = params_format(params); 108 unsigned int channels = params_channels(params); 109 unsigned int rate = params_rate(params); 110 unsigned int mode; 111 unsigned int regval; 112 int bitwidth, ret; 113 114 bitwidth = snd_pcm_format_width(format); 115 if (bitwidth < 0) { 116 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth); 117 return bitwidth; 118 } 119 120 ret = regmap_fields_write(i2sctl->loopback, id, 121 LPAIF_I2SCTL_LOOPBACK_DISABLE); 122 if (ret) { 123 dev_err(dai->dev, "error updating loopback field: %d\n", ret); 124 return ret; 125 } 126 127 ret = regmap_fields_write(i2sctl->wssrc, id, 128 LPAIF_I2SCTL_WSSRC_INTERNAL); 129 if (ret) { 130 dev_err(dai->dev, "error updating wssrc field: %d\n", ret); 131 return ret; 132 } 133 134 switch (bitwidth) { 135 case 16: 136 regval = LPAIF_I2SCTL_BITWIDTH_16; 137 break; 138 case 24: 139 regval = LPAIF_I2SCTL_BITWIDTH_24; 140 break; 141 case 32: 142 regval = LPAIF_I2SCTL_BITWIDTH_32; 143 break; 144 default: 145 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth); 146 return -EINVAL; 147 } 148 149 ret = regmap_fields_write(i2sctl->bitwidth, id, regval); 150 if (ret) { 151 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret); 152 return ret; 153 } 154 155 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 156 mode = drvdata->mi2s_playback_sd_mode[id]; 157 else 158 mode = drvdata->mi2s_capture_sd_mode[id]; 159 160 if (!mode) { 161 dev_err(dai->dev, "no line is assigned\n"); 162 return -EINVAL; 163 } 164 165 switch (channels) { 166 case 1: 167 case 2: 168 switch (mode) { 169 case LPAIF_I2SCTL_MODE_QUAD01: 170 case LPAIF_I2SCTL_MODE_6CH: 171 case LPAIF_I2SCTL_MODE_8CH: 172 mode = LPAIF_I2SCTL_MODE_SD0; 173 break; 174 case LPAIF_I2SCTL_MODE_QUAD23: 175 mode = LPAIF_I2SCTL_MODE_SD2; 176 break; 177 } 178 179 break; 180 case 4: 181 if (mode < LPAIF_I2SCTL_MODE_QUAD01) { 182 dev_err(dai->dev, "cannot configure 4 channels with mode %d\n", 183 mode); 184 return -EINVAL; 185 } 186 187 switch (mode) { 188 case LPAIF_I2SCTL_MODE_6CH: 189 case LPAIF_I2SCTL_MODE_8CH: 190 mode = LPAIF_I2SCTL_MODE_QUAD01; 191 break; 192 } 193 break; 194 case 6: 195 if (mode < LPAIF_I2SCTL_MODE_6CH) { 196 dev_err(dai->dev, "cannot configure 6 channels with mode %d\n", 197 mode); 198 return -EINVAL; 199 } 200 201 switch (mode) { 202 case LPAIF_I2SCTL_MODE_8CH: 203 mode = LPAIF_I2SCTL_MODE_6CH; 204 break; 205 } 206 break; 207 case 8: 208 if (mode < LPAIF_I2SCTL_MODE_8CH) { 209 dev_err(dai->dev, "cannot configure 8 channels with mode %d\n", 210 mode); 211 return -EINVAL; 212 } 213 break; 214 default: 215 dev_err(dai->dev, "invalid channels given: %u\n", channels); 216 return -EINVAL; 217 } 218 219 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 220 ret = regmap_fields_write(i2sctl->spkmode, id, 221 LPAIF_I2SCTL_SPKMODE(mode)); 222 if (ret) { 223 dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n", 224 ret); 225 return ret; 226 } 227 if (channels >= 2) 228 ret = regmap_fields_write(i2sctl->spkmono, id, 229 LPAIF_I2SCTL_SPKMONO_STEREO); 230 else 231 ret = regmap_fields_write(i2sctl->spkmono, id, 232 LPAIF_I2SCTL_SPKMONO_MONO); 233 } else { 234 ret = regmap_fields_write(i2sctl->micmode, id, 235 LPAIF_I2SCTL_MICMODE(mode)); 236 if (ret) { 237 dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n", 238 ret); 239 return ret; 240 } 241 if (channels >= 2) 242 ret = regmap_fields_write(i2sctl->micmono, id, 243 LPAIF_I2SCTL_MICMONO_STEREO); 244 else 245 ret = regmap_fields_write(i2sctl->micmono, id, 246 LPAIF_I2SCTL_MICMONO_MONO); 247 } 248 249 if (ret) { 250 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n", 251 ret); 252 return ret; 253 } 254 255 ret = clk_set_rate(drvdata->mi2s_bit_clk[id], 256 rate * bitwidth * 2); 257 if (ret) { 258 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n", 259 rate * bitwidth * 2, ret); 260 return ret; 261 } 262 263 return 0; 264 } 265 266 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream, 267 int cmd, struct snd_soc_dai *dai) 268 { 269 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 270 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 271 unsigned int id = dai->driver->id; 272 int ret = -EINVAL; 273 274 switch (cmd) { 275 case SNDRV_PCM_TRIGGER_START: 276 case SNDRV_PCM_TRIGGER_RESUME: 277 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 278 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 279 ret = regmap_fields_write(i2sctl->spken, id, 280 LPAIF_I2SCTL_SPKEN_ENABLE); 281 } else { 282 ret = regmap_fields_write(i2sctl->micen, id, 283 LPAIF_I2SCTL_MICEN_ENABLE); 284 } 285 if (ret) 286 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 287 ret); 288 289 if (drvdata->bit_clk_state[id] == LPAIF_BIT_CLK_DISABLE) { 290 ret = clk_enable(drvdata->mi2s_bit_clk[id]); 291 if (ret) { 292 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 293 clk_disable(drvdata->mi2s_osr_clk[id]); 294 return ret; 295 } 296 drvdata->bit_clk_state[id] = LPAIF_BIT_CLK_ENABLE; 297 } 298 299 break; 300 case SNDRV_PCM_TRIGGER_STOP: 301 case SNDRV_PCM_TRIGGER_SUSPEND: 302 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 303 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 304 ret = regmap_fields_write(i2sctl->spken, id, 305 LPAIF_I2SCTL_SPKEN_DISABLE); 306 } else { 307 ret = regmap_fields_write(i2sctl->micen, id, 308 LPAIF_I2SCTL_MICEN_DISABLE); 309 } 310 if (ret) 311 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 312 ret); 313 if (drvdata->bit_clk_state[id] == LPAIF_BIT_CLK_ENABLE) { 314 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]); 315 drvdata->bit_clk_state[id] = LPAIF_BIT_CLK_DISABLE; 316 } 317 break; 318 } 319 320 return ret; 321 } 322 323 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = { 324 .set_sysclk = lpass_cpu_daiops_set_sysclk, 325 .startup = lpass_cpu_daiops_startup, 326 .shutdown = lpass_cpu_daiops_shutdown, 327 .hw_params = lpass_cpu_daiops_hw_params, 328 .trigger = lpass_cpu_daiops_trigger, 329 }; 330 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops); 331 332 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai) 333 { 334 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 335 int ret; 336 337 /* ensure audio hardware is disabled */ 338 ret = regmap_write(drvdata->lpaif_map, 339 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0); 340 if (ret) 341 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret); 342 343 return ret; 344 } 345 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe); 346 347 static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component, 348 struct of_phandle_args *args, 349 const char **dai_name) 350 { 351 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component); 352 struct lpass_variant *variant = drvdata->variant; 353 int id = args->args[0]; 354 int ret = -EINVAL; 355 int i; 356 357 for (i = 0; i < variant->num_dai; i++) { 358 if (variant->dai_driver[i].id == id) { 359 *dai_name = variant->dai_driver[i].name; 360 ret = 0; 361 break; 362 } 363 } 364 365 return ret; 366 } 367 368 static const struct snd_soc_component_driver lpass_cpu_comp_driver = { 369 .name = "lpass-cpu", 370 .of_xlate_dai_name = asoc_qcom_of_xlate_dai_name, 371 }; 372 373 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg) 374 { 375 struct lpass_data *drvdata = dev_get_drvdata(dev); 376 struct lpass_variant *v = drvdata->variant; 377 int i; 378 379 for (i = 0; i < v->i2s_ports; ++i) 380 if (reg == LPAIF_I2SCTL_REG(v, i)) 381 return true; 382 383 for (i = 0; i < v->irq_ports; ++i) { 384 if (reg == LPAIF_IRQEN_REG(v, i)) 385 return true; 386 if (reg == LPAIF_IRQCLEAR_REG(v, i)) 387 return true; 388 } 389 390 for (i = 0; i < v->rdma_channels; ++i) { 391 if (reg == LPAIF_RDMACTL_REG(v, i)) 392 return true; 393 if (reg == LPAIF_RDMABASE_REG(v, i)) 394 return true; 395 if (reg == LPAIF_RDMABUFF_REG(v, i)) 396 return true; 397 if (reg == LPAIF_RDMAPER_REG(v, i)) 398 return true; 399 } 400 401 for (i = 0; i < v->wrdma_channels; ++i) { 402 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 403 return true; 404 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 405 return true; 406 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 407 return true; 408 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 409 return true; 410 } 411 412 return false; 413 } 414 415 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg) 416 { 417 struct lpass_data *drvdata = dev_get_drvdata(dev); 418 struct lpass_variant *v = drvdata->variant; 419 int i; 420 421 for (i = 0; i < v->i2s_ports; ++i) 422 if (reg == LPAIF_I2SCTL_REG(v, i)) 423 return true; 424 425 for (i = 0; i < v->irq_ports; ++i) { 426 if (reg == LPAIF_IRQEN_REG(v, i)) 427 return true; 428 if (reg == LPAIF_IRQSTAT_REG(v, i)) 429 return true; 430 } 431 432 for (i = 0; i < v->rdma_channels; ++i) { 433 if (reg == LPAIF_RDMACTL_REG(v, i)) 434 return true; 435 if (reg == LPAIF_RDMABASE_REG(v, i)) 436 return true; 437 if (reg == LPAIF_RDMABUFF_REG(v, i)) 438 return true; 439 if (reg == LPAIF_RDMACURR_REG(v, i)) 440 return true; 441 if (reg == LPAIF_RDMAPER_REG(v, i)) 442 return true; 443 } 444 445 for (i = 0; i < v->wrdma_channels; ++i) { 446 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 447 return true; 448 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 449 return true; 450 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 451 return true; 452 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 453 return true; 454 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 455 return true; 456 } 457 458 return false; 459 } 460 461 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg) 462 { 463 struct lpass_data *drvdata = dev_get_drvdata(dev); 464 struct lpass_variant *v = drvdata->variant; 465 int i; 466 467 for (i = 0; i < v->irq_ports; ++i) 468 if (reg == LPAIF_IRQSTAT_REG(v, i)) 469 return true; 470 471 for (i = 0; i < v->rdma_channels; ++i) 472 if (reg == LPAIF_RDMACURR_REG(v, i)) 473 return true; 474 475 for (i = 0; i < v->wrdma_channels; ++i) 476 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 477 return true; 478 479 return false; 480 } 481 482 static struct regmap_config lpass_cpu_regmap_config = { 483 .reg_bits = 32, 484 .reg_stride = 4, 485 .val_bits = 32, 486 .writeable_reg = lpass_cpu_regmap_writeable, 487 .readable_reg = lpass_cpu_regmap_readable, 488 .volatile_reg = lpass_cpu_regmap_volatile, 489 .cache_type = REGCACHE_FLAT, 490 }; 491 492 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map) 493 { 494 struct lpass_data *drvdata = dev_get_drvdata(dev); 495 struct lpass_variant *v = drvdata->variant; 496 unsigned int i; 497 struct lpass_hdmi_tx_ctl *tx_ctl; 498 struct regmap_field *legacy_en; 499 struct lpass_vbit_ctrl *vbit_ctl; 500 struct regmap_field *tx_parity; 501 struct lpass_dp_metadata_ctl *meta_ctl; 502 struct lpass_sstream_ctl *sstream_ctl; 503 struct regmap_field *ch_msb; 504 struct regmap_field *ch_lsb; 505 struct lpass_hdmitx_dmactl *tx_dmactl; 506 int rval; 507 508 tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL); 509 if (!tx_ctl) 510 return -ENOMEM; 511 512 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset); 513 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset); 514 drvdata->tx_ctl = tx_ctl; 515 516 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en); 517 drvdata->hdmitx_legacy_en = legacy_en; 518 519 vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL); 520 if (!vbit_ctl) 521 return -ENOMEM; 522 523 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit); 524 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream); 525 drvdata->vbit_ctl = vbit_ctl; 526 527 528 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity); 529 drvdata->hdmitx_parity_calc_en = tx_parity; 530 531 meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL); 532 if (!meta_ctl) 533 return -ENOMEM; 534 535 rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7); 536 if (rval) 537 return rval; 538 drvdata->meta_ctl = meta_ctl; 539 540 sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL); 541 if (!sstream_ctl) 542 return -ENOMEM; 543 544 rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9); 545 if (rval) 546 return rval; 547 548 drvdata->sstream_ctl = sstream_ctl; 549 550 for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) { 551 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb); 552 drvdata->hdmitx_ch_msb[i] = ch_msb; 553 554 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb); 555 drvdata->hdmitx_ch_lsb[i] = ch_lsb; 556 557 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL); 558 if (!tx_dmactl) 559 return -ENOMEM; 560 561 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs); 562 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr); 563 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel); 564 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel); 565 drvdata->hdmi_tx_dmactl[i] = tx_dmactl; 566 } 567 return 0; 568 } 569 570 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg) 571 { 572 struct lpass_data *drvdata = dev_get_drvdata(dev); 573 struct lpass_variant *v = drvdata->variant; 574 int i; 575 576 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 577 return true; 578 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 579 return true; 580 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 581 return true; 582 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 583 return true; 584 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 585 return true; 586 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 587 return true; 588 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 589 return true; 590 if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v)) 591 return true; 592 593 for (i = 0; i < v->hdmi_rdma_channels; i++) { 594 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 595 return true; 596 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 597 return true; 598 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 599 return true; 600 } 601 602 for (i = 0; i < v->rdma_channels; ++i) { 603 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 604 return true; 605 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 606 return true; 607 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 608 return true; 609 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 610 return true; 611 } 612 return false; 613 } 614 615 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg) 616 { 617 struct lpass_data *drvdata = dev_get_drvdata(dev); 618 struct lpass_variant *v = drvdata->variant; 619 int i; 620 621 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 622 return true; 623 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 624 return true; 625 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 626 return true; 627 628 for (i = 0; i < v->hdmi_rdma_channels; i++) { 629 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 630 return true; 631 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 632 return true; 633 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 634 return true; 635 } 636 637 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 638 return true; 639 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 640 return true; 641 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 642 return true; 643 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 644 return true; 645 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 646 return true; 647 648 for (i = 0; i < v->rdma_channels; ++i) { 649 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 650 return true; 651 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 652 return true; 653 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 654 return true; 655 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 656 return true; 657 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 658 return true; 659 } 660 661 return false; 662 } 663 664 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg) 665 { 666 struct lpass_data *drvdata = dev_get_drvdata(dev); 667 struct lpass_variant *v = drvdata->variant; 668 int i; 669 670 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 671 return true; 672 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 673 return true; 674 675 for (i = 0; i < v->rdma_channels; ++i) { 676 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 677 return true; 678 } 679 return false; 680 } 681 682 static struct regmap_config lpass_hdmi_regmap_config = { 683 .reg_bits = 32, 684 .reg_stride = 4, 685 .val_bits = 32, 686 .writeable_reg = lpass_hdmi_regmap_writeable, 687 .readable_reg = lpass_hdmi_regmap_readable, 688 .volatile_reg = lpass_hdmi_regmap_volatile, 689 .cache_type = REGCACHE_FLAT, 690 }; 691 692 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev, 693 struct device_node *node, 694 const char *name) 695 { 696 unsigned int lines[LPASS_CPU_MAX_MI2S_LINES]; 697 unsigned int sd_line_mask = 0; 698 int num_lines, i; 699 700 num_lines = of_property_read_variable_u32_array(node, name, lines, 0, 701 LPASS_CPU_MAX_MI2S_LINES); 702 if (num_lines < 0) 703 return LPAIF_I2SCTL_MODE_NONE; 704 705 for (i = 0; i < num_lines; i++) 706 sd_line_mask |= BIT(lines[i]); 707 708 switch (sd_line_mask) { 709 case LPASS_CPU_I2S_SD0_MASK: 710 return LPAIF_I2SCTL_MODE_SD0; 711 case LPASS_CPU_I2S_SD1_MASK: 712 return LPAIF_I2SCTL_MODE_SD1; 713 case LPASS_CPU_I2S_SD2_MASK: 714 return LPAIF_I2SCTL_MODE_SD2; 715 case LPASS_CPU_I2S_SD3_MASK: 716 return LPAIF_I2SCTL_MODE_SD3; 717 case LPASS_CPU_I2S_SD0_1_MASK: 718 return LPAIF_I2SCTL_MODE_QUAD01; 719 case LPASS_CPU_I2S_SD2_3_MASK: 720 return LPAIF_I2SCTL_MODE_QUAD23; 721 case LPASS_CPU_I2S_SD0_1_2_MASK: 722 return LPAIF_I2SCTL_MODE_6CH; 723 case LPASS_CPU_I2S_SD0_1_2_3_MASK: 724 return LPAIF_I2SCTL_MODE_8CH; 725 default: 726 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask); 727 return LPAIF_I2SCTL_MODE_NONE; 728 } 729 } 730 731 static void of_lpass_cpu_parse_dai_data(struct device *dev, 732 struct lpass_data *data) 733 { 734 struct device_node *node; 735 int ret, id; 736 737 /* Allow all channels by default for backwards compatibility */ 738 for (id = 0; id < data->variant->num_dai; id++) { 739 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 740 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 741 } 742 743 for_each_child_of_node(dev->of_node, node) { 744 ret = of_property_read_u32(node, "reg", &id); 745 if (ret || id < 0 || id >= data->variant->num_dai) { 746 dev_err(dev, "valid dai id not found: %d\n", ret); 747 continue; 748 } 749 if (id == LPASS_DP_RX) { 750 data->hdmi_port_enable = 1; 751 dev_err(dev, "HDMI Port is enabled: %d\n", id); 752 } else { 753 data->mi2s_playback_sd_mode[id] = 754 of_lpass_cpu_parse_sd_lines(dev, node, 755 "qcom,playback-sd-lines"); 756 data->mi2s_capture_sd_mode[id] = 757 of_lpass_cpu_parse_sd_lines(dev, node, 758 "qcom,capture-sd-lines"); 759 } 760 } 761 } 762 763 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) 764 { 765 struct lpass_data *drvdata; 766 struct device_node *dsp_of_node; 767 struct resource *res; 768 struct lpass_variant *variant; 769 struct device *dev = &pdev->dev; 770 const struct of_device_id *match; 771 int ret, i, dai_id; 772 773 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); 774 if (dsp_of_node) { 775 dev_err(dev, "DSP exists and holds audio resources\n"); 776 return -EBUSY; 777 } 778 779 drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL); 780 if (!drvdata) 781 return -ENOMEM; 782 platform_set_drvdata(pdev, drvdata); 783 784 match = of_match_device(dev->driver->of_match_table, dev); 785 if (!match || !match->data) 786 return -EINVAL; 787 788 drvdata->variant = (struct lpass_variant *)match->data; 789 variant = drvdata->variant; 790 791 of_lpass_cpu_parse_dai_data(dev, drvdata); 792 793 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif"); 794 795 drvdata->lpaif = devm_ioremap_resource(dev, res); 796 if (IS_ERR((void const __force *)drvdata->lpaif)) { 797 dev_err(dev, "error mapping reg resource: %ld\n", 798 PTR_ERR((void const __force *)drvdata->lpaif)); 799 return PTR_ERR((void const __force *)drvdata->lpaif); 800 } 801 802 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant, 803 variant->wrdma_channels + 804 variant->wrdma_channel_start); 805 806 drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif, 807 &lpass_cpu_regmap_config); 808 if (IS_ERR(drvdata->lpaif_map)) { 809 dev_err(dev, "error initializing regmap: %ld\n", 810 PTR_ERR(drvdata->lpaif_map)); 811 return PTR_ERR(drvdata->lpaif_map); 812 } 813 814 if (drvdata->hdmi_port_enable) { 815 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif"); 816 817 drvdata->hdmiif = devm_ioremap_resource(dev, res); 818 if (IS_ERR((void const __force *)drvdata->hdmiif)) { 819 dev_err(dev, "error mapping reg resource: %ld\n", 820 PTR_ERR((void const __force *)drvdata->hdmiif)); 821 return PTR_ERR((void const __force *)drvdata->hdmiif); 822 } 823 824 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant, 825 variant->hdmi_rdma_channels); 826 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif, 827 &lpass_hdmi_regmap_config); 828 if (IS_ERR(drvdata->hdmiif_map)) { 829 dev_err(dev, "error initializing regmap: %ld\n", 830 PTR_ERR(drvdata->hdmiif_map)); 831 return PTR_ERR(drvdata->hdmiif_map); 832 } 833 } 834 835 if (variant->init) { 836 ret = variant->init(pdev); 837 if (ret) { 838 dev_err(dev, "error initializing variant: %d\n", ret); 839 return ret; 840 } 841 } 842 843 for (i = 0; i < variant->num_dai; i++) { 844 dai_id = variant->dai_driver[i].id; 845 if (dai_id == LPASS_DP_RX) 846 continue; 847 848 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(dev, 849 variant->dai_osr_clk_names[i]); 850 if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) { 851 dev_warn(dev, 852 "%s() error getting optional %s: %ld\n", 853 __func__, 854 variant->dai_osr_clk_names[i], 855 PTR_ERR(drvdata->mi2s_osr_clk[dai_id])); 856 857 drvdata->mi2s_osr_clk[dai_id] = NULL; 858 } 859 860 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev, 861 variant->dai_bit_clk_names[i]); 862 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) { 863 dev_err(dev, 864 "error getting %s: %ld\n", 865 variant->dai_bit_clk_names[i], 866 PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); 867 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); 868 } 869 drvdata->bit_clk_state[dai_id] = LPAIF_BIT_CLK_DISABLE; 870 } 871 872 /* Allocation for i2sctl regmap fields */ 873 drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl), 874 GFP_KERNEL); 875 876 /* Initialize bitfields for dai I2SCTL register */ 877 ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl, 878 drvdata->lpaif_map); 879 if (ret) { 880 dev_err(dev, "error init i2sctl field: %d\n", ret); 881 return ret; 882 } 883 884 if (drvdata->hdmi_port_enable) { 885 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map); 886 if (ret) { 887 dev_err(dev, "%s error hdmi init failed\n", __func__); 888 return ret; 889 } 890 } 891 ret = devm_snd_soc_register_component(dev, 892 &lpass_cpu_comp_driver, 893 variant->dai_driver, 894 variant->num_dai); 895 if (ret) { 896 dev_err(dev, "error registering cpu driver: %d\n", ret); 897 goto err; 898 } 899 900 ret = asoc_qcom_lpass_platform_register(pdev); 901 if (ret) { 902 dev_err(dev, "error registering platform driver: %d\n", ret); 903 goto err; 904 } 905 906 err: 907 return ret; 908 } 909 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe); 910 911 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev) 912 { 913 struct lpass_data *drvdata = platform_get_drvdata(pdev); 914 915 if (drvdata->variant->exit) 916 drvdata->variant->exit(pdev); 917 918 919 return 0; 920 } 921 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove); 922 923 void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev) 924 { 925 struct lpass_data *drvdata = platform_get_drvdata(pdev); 926 927 if (drvdata->variant->exit) 928 drvdata->variant->exit(pdev); 929 930 } 931 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown); 932 933 MODULE_DESCRIPTION("QTi LPASS CPU Driver"); 934 MODULE_LICENSE("GPL v2"); 935