1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 4 * 5 * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <sound/pcm.h> 15 #include <sound/pcm_params.h> 16 #include <linux/regmap.h> 17 #include <sound/soc.h> 18 #include <sound/soc-dai.h> 19 #include "lpass-lpaif-reg.h" 20 #include "lpass.h" 21 22 #define LPASS_CPU_MAX_MI2S_LINES 4 23 #define LPASS_CPU_I2S_SD0_MASK BIT(0) 24 #define LPASS_CPU_I2S_SD1_MASK BIT(1) 25 #define LPASS_CPU_I2S_SD2_MASK BIT(2) 26 #define LPASS_CPU_I2S_SD3_MASK BIT(3) 27 #define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0) 28 #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2) 29 #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0) 30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 31 32 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev, 33 struct lpaif_i2sctl *i2sctl, struct regmap *map) 34 { 35 struct lpass_data *drvdata = dev_get_drvdata(dev); 36 struct lpass_variant *v = drvdata->variant; 37 38 i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback); 39 i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken); 40 i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode); 41 i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono); 42 i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen); 43 i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode); 44 i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono); 45 i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc); 46 i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth); 47 48 if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) || 49 IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) || 50 IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) || 51 IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) || 52 IS_ERR(i2sctl->bitwidth)) 53 return -EINVAL; 54 55 return 0; 56 } 57 58 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, 59 unsigned int freq, int dir) 60 { 61 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 62 int ret; 63 64 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); 65 if (ret) 66 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n", 67 freq, ret); 68 69 return ret; 70 } 71 72 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, 73 struct snd_soc_dai *dai) 74 { 75 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 76 int ret; 77 78 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]); 79 if (ret) { 80 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret); 81 return ret; 82 } 83 ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]); 84 if (ret) { 85 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 86 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 87 return ret; 88 } 89 return 0; 90 } 91 92 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, 93 struct snd_soc_dai *dai) 94 { 95 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 96 97 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 98 clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); 99 } 100 101 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, 102 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 103 { 104 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 105 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 106 unsigned int id = dai->driver->id; 107 snd_pcm_format_t format = params_format(params); 108 unsigned int channels = params_channels(params); 109 unsigned int rate = params_rate(params); 110 unsigned int mode; 111 unsigned int regval; 112 int bitwidth, ret; 113 114 bitwidth = snd_pcm_format_width(format); 115 if (bitwidth < 0) { 116 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth); 117 return bitwidth; 118 } 119 120 ret = regmap_fields_write(i2sctl->loopback, id, 121 LPAIF_I2SCTL_LOOPBACK_DISABLE); 122 if (ret) { 123 dev_err(dai->dev, "error updating loopback field: %d\n", ret); 124 return ret; 125 } 126 127 ret = regmap_fields_write(i2sctl->wssrc, id, 128 LPAIF_I2SCTL_WSSRC_INTERNAL); 129 if (ret) { 130 dev_err(dai->dev, "error updating wssrc field: %d\n", ret); 131 return ret; 132 } 133 134 switch (bitwidth) { 135 case 16: 136 regval = LPAIF_I2SCTL_BITWIDTH_16; 137 break; 138 case 24: 139 regval = LPAIF_I2SCTL_BITWIDTH_24; 140 break; 141 case 32: 142 regval = LPAIF_I2SCTL_BITWIDTH_32; 143 break; 144 default: 145 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth); 146 return -EINVAL; 147 } 148 149 ret = regmap_fields_write(i2sctl->bitwidth, id, regval); 150 if (ret) { 151 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret); 152 return ret; 153 } 154 155 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 156 mode = drvdata->mi2s_playback_sd_mode[id]; 157 else 158 mode = drvdata->mi2s_capture_sd_mode[id]; 159 160 if (!mode) { 161 dev_err(dai->dev, "no line is assigned\n"); 162 return -EINVAL; 163 } 164 165 switch (channels) { 166 case 1: 167 case 2: 168 switch (mode) { 169 case LPAIF_I2SCTL_MODE_QUAD01: 170 case LPAIF_I2SCTL_MODE_6CH: 171 case LPAIF_I2SCTL_MODE_8CH: 172 mode = LPAIF_I2SCTL_MODE_SD0; 173 break; 174 case LPAIF_I2SCTL_MODE_QUAD23: 175 mode = LPAIF_I2SCTL_MODE_SD2; 176 break; 177 } 178 179 break; 180 case 4: 181 if (mode < LPAIF_I2SCTL_MODE_QUAD01) { 182 dev_err(dai->dev, "cannot configure 4 channels with mode %d\n", 183 mode); 184 return -EINVAL; 185 } 186 187 switch (mode) { 188 case LPAIF_I2SCTL_MODE_6CH: 189 case LPAIF_I2SCTL_MODE_8CH: 190 mode = LPAIF_I2SCTL_MODE_QUAD01; 191 break; 192 } 193 break; 194 case 6: 195 if (mode < LPAIF_I2SCTL_MODE_6CH) { 196 dev_err(dai->dev, "cannot configure 6 channels with mode %d\n", 197 mode); 198 return -EINVAL; 199 } 200 201 switch (mode) { 202 case LPAIF_I2SCTL_MODE_8CH: 203 mode = LPAIF_I2SCTL_MODE_6CH; 204 break; 205 } 206 break; 207 case 8: 208 if (mode < LPAIF_I2SCTL_MODE_8CH) { 209 dev_err(dai->dev, "cannot configure 8 channels with mode %d\n", 210 mode); 211 return -EINVAL; 212 } 213 break; 214 default: 215 dev_err(dai->dev, "invalid channels given: %u\n", channels); 216 return -EINVAL; 217 } 218 219 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 220 ret = regmap_fields_write(i2sctl->spkmode, id, 221 LPAIF_I2SCTL_SPKMODE(mode)); 222 if (ret) { 223 dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n", 224 ret); 225 return ret; 226 } 227 if (channels >= 2) 228 ret = regmap_fields_write(i2sctl->spkmono, id, 229 LPAIF_I2SCTL_SPKMONO_STEREO); 230 else 231 ret = regmap_fields_write(i2sctl->spkmono, id, 232 LPAIF_I2SCTL_SPKMONO_MONO); 233 } else { 234 ret = regmap_fields_write(i2sctl->micmode, id, 235 LPAIF_I2SCTL_MICMODE(mode)); 236 if (ret) { 237 dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n", 238 ret); 239 return ret; 240 } 241 if (channels >= 2) 242 ret = regmap_fields_write(i2sctl->micmono, id, 243 LPAIF_I2SCTL_MICMONO_STEREO); 244 else 245 ret = regmap_fields_write(i2sctl->micmono, id, 246 LPAIF_I2SCTL_MICMONO_MONO); 247 } 248 249 if (ret) { 250 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n", 251 ret); 252 return ret; 253 } 254 255 ret = clk_set_rate(drvdata->mi2s_bit_clk[id], 256 rate * bitwidth * 2); 257 if (ret) { 258 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n", 259 rate * bitwidth * 2, ret); 260 return ret; 261 } 262 263 return 0; 264 } 265 266 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream, 267 int cmd, struct snd_soc_dai *dai) 268 { 269 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 270 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 271 unsigned int id = dai->driver->id; 272 int ret = -EINVAL; 273 274 switch (cmd) { 275 case SNDRV_PCM_TRIGGER_START: 276 case SNDRV_PCM_TRIGGER_RESUME: 277 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 278 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 279 ret = regmap_fields_write(i2sctl->spken, id, 280 LPAIF_I2SCTL_SPKEN_ENABLE); 281 } else { 282 ret = regmap_fields_write(i2sctl->micen, id, 283 LPAIF_I2SCTL_MICEN_ENABLE); 284 } 285 if (ret) 286 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 287 ret); 288 289 ret = clk_enable(drvdata->mi2s_bit_clk[id]); 290 if (ret) { 291 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 292 clk_disable(drvdata->mi2s_osr_clk[id]); 293 return ret; 294 } 295 break; 296 case SNDRV_PCM_TRIGGER_STOP: 297 case SNDRV_PCM_TRIGGER_SUSPEND: 298 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 299 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 300 ret = regmap_fields_write(i2sctl->spken, id, 301 LPAIF_I2SCTL_SPKEN_DISABLE); 302 } else { 303 ret = regmap_fields_write(i2sctl->micen, id, 304 LPAIF_I2SCTL_MICEN_DISABLE); 305 } 306 if (ret) 307 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 308 ret); 309 310 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]); 311 312 break; 313 } 314 315 return ret; 316 } 317 318 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = { 319 .set_sysclk = lpass_cpu_daiops_set_sysclk, 320 .startup = lpass_cpu_daiops_startup, 321 .shutdown = lpass_cpu_daiops_shutdown, 322 .hw_params = lpass_cpu_daiops_hw_params, 323 .trigger = lpass_cpu_daiops_trigger, 324 }; 325 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops); 326 327 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai) 328 { 329 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 330 int ret; 331 332 /* ensure audio hardware is disabled */ 333 ret = regmap_write(drvdata->lpaif_map, 334 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0); 335 if (ret) 336 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret); 337 338 return ret; 339 } 340 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe); 341 342 static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component, 343 struct of_phandle_args *args, 344 const char **dai_name) 345 { 346 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component); 347 struct lpass_variant *variant = drvdata->variant; 348 int id = args->args[0]; 349 int ret = -EINVAL; 350 int i; 351 352 for (i = 0; i < variant->num_dai; i++) { 353 if (variant->dai_driver[i].id == id) { 354 *dai_name = variant->dai_driver[i].name; 355 ret = 0; 356 break; 357 } 358 } 359 360 return ret; 361 } 362 363 static const struct snd_soc_component_driver lpass_cpu_comp_driver = { 364 .name = "lpass-cpu", 365 .of_xlate_dai_name = asoc_qcom_of_xlate_dai_name, 366 }; 367 368 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg) 369 { 370 struct lpass_data *drvdata = dev_get_drvdata(dev); 371 struct lpass_variant *v = drvdata->variant; 372 int i; 373 374 for (i = 0; i < v->i2s_ports; ++i) 375 if (reg == LPAIF_I2SCTL_REG(v, i)) 376 return true; 377 378 for (i = 0; i < v->irq_ports; ++i) { 379 if (reg == LPAIF_IRQEN_REG(v, i)) 380 return true; 381 if (reg == LPAIF_IRQCLEAR_REG(v, i)) 382 return true; 383 } 384 385 for (i = 0; i < v->rdma_channels; ++i) { 386 if (reg == LPAIF_RDMACTL_REG(v, i)) 387 return true; 388 if (reg == LPAIF_RDMABASE_REG(v, i)) 389 return true; 390 if (reg == LPAIF_RDMABUFF_REG(v, i)) 391 return true; 392 if (reg == LPAIF_RDMAPER_REG(v, i)) 393 return true; 394 } 395 396 for (i = 0; i < v->wrdma_channels; ++i) { 397 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 398 return true; 399 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 400 return true; 401 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 402 return true; 403 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 404 return true; 405 } 406 407 return false; 408 } 409 410 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg) 411 { 412 struct lpass_data *drvdata = dev_get_drvdata(dev); 413 struct lpass_variant *v = drvdata->variant; 414 int i; 415 416 for (i = 0; i < v->i2s_ports; ++i) 417 if (reg == LPAIF_I2SCTL_REG(v, i)) 418 return true; 419 420 for (i = 0; i < v->irq_ports; ++i) { 421 if (reg == LPAIF_IRQEN_REG(v, i)) 422 return true; 423 if (reg == LPAIF_IRQSTAT_REG(v, i)) 424 return true; 425 } 426 427 for (i = 0; i < v->rdma_channels; ++i) { 428 if (reg == LPAIF_RDMACTL_REG(v, i)) 429 return true; 430 if (reg == LPAIF_RDMABASE_REG(v, i)) 431 return true; 432 if (reg == LPAIF_RDMABUFF_REG(v, i)) 433 return true; 434 if (reg == LPAIF_RDMACURR_REG(v, i)) 435 return true; 436 if (reg == LPAIF_RDMAPER_REG(v, i)) 437 return true; 438 } 439 440 for (i = 0; i < v->wrdma_channels; ++i) { 441 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 442 return true; 443 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 444 return true; 445 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 446 return true; 447 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 448 return true; 449 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 450 return true; 451 } 452 453 return false; 454 } 455 456 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg) 457 { 458 struct lpass_data *drvdata = dev_get_drvdata(dev); 459 struct lpass_variant *v = drvdata->variant; 460 int i; 461 462 for (i = 0; i < v->irq_ports; ++i) 463 if (reg == LPAIF_IRQSTAT_REG(v, i)) 464 return true; 465 466 for (i = 0; i < v->rdma_channels; ++i) 467 if (reg == LPAIF_RDMACURR_REG(v, i)) 468 return true; 469 470 for (i = 0; i < v->wrdma_channels; ++i) 471 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 472 return true; 473 474 return false; 475 } 476 477 static struct regmap_config lpass_cpu_regmap_config = { 478 .name = "lpass_cpu", 479 .reg_bits = 32, 480 .reg_stride = 4, 481 .val_bits = 32, 482 .writeable_reg = lpass_cpu_regmap_writeable, 483 .readable_reg = lpass_cpu_regmap_readable, 484 .volatile_reg = lpass_cpu_regmap_volatile, 485 .cache_type = REGCACHE_FLAT, 486 }; 487 488 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map) 489 { 490 struct lpass_data *drvdata = dev_get_drvdata(dev); 491 struct lpass_variant *v = drvdata->variant; 492 unsigned int i; 493 struct lpass_hdmi_tx_ctl *tx_ctl; 494 struct regmap_field *legacy_en; 495 struct lpass_vbit_ctrl *vbit_ctl; 496 struct regmap_field *tx_parity; 497 struct lpass_dp_metadata_ctl *meta_ctl; 498 struct lpass_sstream_ctl *sstream_ctl; 499 struct regmap_field *ch_msb; 500 struct regmap_field *ch_lsb; 501 struct lpass_hdmitx_dmactl *tx_dmactl; 502 int rval; 503 504 tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL); 505 if (!tx_ctl) 506 return -ENOMEM; 507 508 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset); 509 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset); 510 drvdata->tx_ctl = tx_ctl; 511 512 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en); 513 drvdata->hdmitx_legacy_en = legacy_en; 514 515 vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL); 516 if (!vbit_ctl) 517 return -ENOMEM; 518 519 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit); 520 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream); 521 drvdata->vbit_ctl = vbit_ctl; 522 523 524 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity); 525 drvdata->hdmitx_parity_calc_en = tx_parity; 526 527 meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL); 528 if (!meta_ctl) 529 return -ENOMEM; 530 531 rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7); 532 if (rval) 533 return rval; 534 drvdata->meta_ctl = meta_ctl; 535 536 sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL); 537 if (!sstream_ctl) 538 return -ENOMEM; 539 540 rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9); 541 if (rval) 542 return rval; 543 544 drvdata->sstream_ctl = sstream_ctl; 545 546 for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) { 547 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb); 548 drvdata->hdmitx_ch_msb[i] = ch_msb; 549 550 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb); 551 drvdata->hdmitx_ch_lsb[i] = ch_lsb; 552 553 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL); 554 if (!tx_dmactl) 555 return -ENOMEM; 556 557 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs); 558 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr); 559 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel); 560 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel); 561 drvdata->hdmi_tx_dmactl[i] = tx_dmactl; 562 } 563 return 0; 564 } 565 566 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg) 567 { 568 struct lpass_data *drvdata = dev_get_drvdata(dev); 569 struct lpass_variant *v = drvdata->variant; 570 int i; 571 572 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 573 return true; 574 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 575 return true; 576 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 577 return true; 578 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 579 return true; 580 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 581 return true; 582 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 583 return true; 584 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 585 return true; 586 if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v)) 587 return true; 588 589 for (i = 0; i < v->hdmi_rdma_channels; i++) { 590 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 591 return true; 592 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 593 return true; 594 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 595 return true; 596 } 597 598 for (i = 0; i < v->hdmi_rdma_channels; ++i) { 599 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 600 return true; 601 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 602 return true; 603 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 604 return true; 605 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 606 return true; 607 } 608 return false; 609 } 610 611 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg) 612 { 613 struct lpass_data *drvdata = dev_get_drvdata(dev); 614 struct lpass_variant *v = drvdata->variant; 615 int i; 616 617 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 618 return true; 619 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 620 return true; 621 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 622 return true; 623 624 for (i = 0; i < v->hdmi_rdma_channels; i++) { 625 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 626 return true; 627 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 628 return true; 629 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 630 return true; 631 } 632 633 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 634 return true; 635 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 636 return true; 637 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 638 return true; 639 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 640 return true; 641 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 642 return true; 643 644 for (i = 0; i < v->hdmi_rdma_channels; ++i) { 645 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 646 return true; 647 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 648 return true; 649 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 650 return true; 651 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 652 return true; 653 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 654 return true; 655 } 656 657 return false; 658 } 659 660 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg) 661 { 662 struct lpass_data *drvdata = dev_get_drvdata(dev); 663 struct lpass_variant *v = drvdata->variant; 664 int i; 665 666 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 667 return true; 668 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 669 return true; 670 671 for (i = 0; i < v->hdmi_rdma_channels; ++i) { 672 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 673 return true; 674 } 675 return false; 676 } 677 678 static struct regmap_config lpass_hdmi_regmap_config = { 679 .name = "lpass_hdmi", 680 .reg_bits = 32, 681 .reg_stride = 4, 682 .val_bits = 32, 683 .writeable_reg = lpass_hdmi_regmap_writeable, 684 .readable_reg = lpass_hdmi_regmap_readable, 685 .volatile_reg = lpass_hdmi_regmap_volatile, 686 .cache_type = REGCACHE_FLAT, 687 }; 688 689 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev, 690 struct device_node *node, 691 const char *name) 692 { 693 unsigned int lines[LPASS_CPU_MAX_MI2S_LINES]; 694 unsigned int sd_line_mask = 0; 695 int num_lines, i; 696 697 num_lines = of_property_read_variable_u32_array(node, name, lines, 0, 698 LPASS_CPU_MAX_MI2S_LINES); 699 if (num_lines < 0) 700 return LPAIF_I2SCTL_MODE_NONE; 701 702 for (i = 0; i < num_lines; i++) 703 sd_line_mask |= BIT(lines[i]); 704 705 switch (sd_line_mask) { 706 case LPASS_CPU_I2S_SD0_MASK: 707 return LPAIF_I2SCTL_MODE_SD0; 708 case LPASS_CPU_I2S_SD1_MASK: 709 return LPAIF_I2SCTL_MODE_SD1; 710 case LPASS_CPU_I2S_SD2_MASK: 711 return LPAIF_I2SCTL_MODE_SD2; 712 case LPASS_CPU_I2S_SD3_MASK: 713 return LPAIF_I2SCTL_MODE_SD3; 714 case LPASS_CPU_I2S_SD0_1_MASK: 715 return LPAIF_I2SCTL_MODE_QUAD01; 716 case LPASS_CPU_I2S_SD2_3_MASK: 717 return LPAIF_I2SCTL_MODE_QUAD23; 718 case LPASS_CPU_I2S_SD0_1_2_MASK: 719 return LPAIF_I2SCTL_MODE_6CH; 720 case LPASS_CPU_I2S_SD0_1_2_3_MASK: 721 return LPAIF_I2SCTL_MODE_8CH; 722 default: 723 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask); 724 return LPAIF_I2SCTL_MODE_NONE; 725 } 726 } 727 728 static void of_lpass_cpu_parse_dai_data(struct device *dev, 729 struct lpass_data *data) 730 { 731 struct device_node *node; 732 int ret, id; 733 734 /* Allow all channels by default for backwards compatibility */ 735 for (id = 0; id < data->variant->num_dai; id++) { 736 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 737 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 738 } 739 740 for_each_child_of_node(dev->of_node, node) { 741 ret = of_property_read_u32(node, "reg", &id); 742 if (ret || id < 0 || id >= data->variant->num_dai) { 743 dev_err(dev, "valid dai id not found: %d\n", ret); 744 continue; 745 } 746 if (id == LPASS_DP_RX) { 747 data->hdmi_port_enable = 1; 748 } else { 749 data->mi2s_playback_sd_mode[id] = 750 of_lpass_cpu_parse_sd_lines(dev, node, 751 "qcom,playback-sd-lines"); 752 data->mi2s_capture_sd_mode[id] = 753 of_lpass_cpu_parse_sd_lines(dev, node, 754 "qcom,capture-sd-lines"); 755 } 756 } 757 } 758 759 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) 760 { 761 struct lpass_data *drvdata; 762 struct device_node *dsp_of_node; 763 struct resource *res; 764 struct lpass_variant *variant; 765 struct device *dev = &pdev->dev; 766 const struct of_device_id *match; 767 int ret, i, dai_id; 768 769 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); 770 if (dsp_of_node) { 771 dev_err(dev, "DSP exists and holds audio resources\n"); 772 return -EBUSY; 773 } 774 775 drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL); 776 if (!drvdata) 777 return -ENOMEM; 778 platform_set_drvdata(pdev, drvdata); 779 780 match = of_match_device(dev->driver->of_match_table, dev); 781 if (!match || !match->data) 782 return -EINVAL; 783 784 drvdata->variant = (struct lpass_variant *)match->data; 785 variant = drvdata->variant; 786 787 of_lpass_cpu_parse_dai_data(dev, drvdata); 788 789 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif"); 790 791 drvdata->lpaif = devm_ioremap_resource(dev, res); 792 if (IS_ERR(drvdata->lpaif)) 793 return PTR_ERR(drvdata->lpaif); 794 795 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant, 796 variant->wrdma_channels + 797 variant->wrdma_channel_start); 798 799 drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif, 800 &lpass_cpu_regmap_config); 801 if (IS_ERR(drvdata->lpaif_map)) { 802 dev_err(dev, "error initializing regmap: %ld\n", 803 PTR_ERR(drvdata->lpaif_map)); 804 return PTR_ERR(drvdata->lpaif_map); 805 } 806 807 if (drvdata->hdmi_port_enable) { 808 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif"); 809 810 drvdata->hdmiif = devm_ioremap_resource(dev, res); 811 if (IS_ERR(drvdata->hdmiif)) 812 return PTR_ERR(drvdata->hdmiif); 813 814 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant, 815 variant->hdmi_rdma_channels - 1); 816 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif, 817 &lpass_hdmi_regmap_config); 818 if (IS_ERR(drvdata->hdmiif_map)) { 819 dev_err(dev, "error initializing regmap: %ld\n", 820 PTR_ERR(drvdata->hdmiif_map)); 821 return PTR_ERR(drvdata->hdmiif_map); 822 } 823 } 824 825 if (variant->init) { 826 ret = variant->init(pdev); 827 if (ret) { 828 dev_err(dev, "error initializing variant: %d\n", ret); 829 return ret; 830 } 831 } 832 833 for (i = 0; i < variant->num_dai; i++) { 834 dai_id = variant->dai_driver[i].id; 835 if (dai_id == LPASS_DP_RX) 836 continue; 837 838 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(dev, 839 variant->dai_osr_clk_names[i]); 840 if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) { 841 dev_warn(dev, 842 "%s() error getting optional %s: %ld\n", 843 __func__, 844 variant->dai_osr_clk_names[i], 845 PTR_ERR(drvdata->mi2s_osr_clk[dai_id])); 846 847 drvdata->mi2s_osr_clk[dai_id] = NULL; 848 } 849 850 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev, 851 variant->dai_bit_clk_names[i]); 852 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) { 853 dev_err(dev, 854 "error getting %s: %ld\n", 855 variant->dai_bit_clk_names[i], 856 PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); 857 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); 858 } 859 } 860 861 /* Allocation for i2sctl regmap fields */ 862 drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl), 863 GFP_KERNEL); 864 865 /* Initialize bitfields for dai I2SCTL register */ 866 ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl, 867 drvdata->lpaif_map); 868 if (ret) { 869 dev_err(dev, "error init i2sctl field: %d\n", ret); 870 return ret; 871 } 872 873 if (drvdata->hdmi_port_enable) { 874 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map); 875 if (ret) { 876 dev_err(dev, "%s error hdmi init failed\n", __func__); 877 return ret; 878 } 879 } 880 ret = devm_snd_soc_register_component(dev, 881 &lpass_cpu_comp_driver, 882 variant->dai_driver, 883 variant->num_dai); 884 if (ret) { 885 dev_err(dev, "error registering cpu driver: %d\n", ret); 886 goto err; 887 } 888 889 ret = asoc_qcom_lpass_platform_register(pdev); 890 if (ret) { 891 dev_err(dev, "error registering platform driver: %d\n", ret); 892 goto err; 893 } 894 895 err: 896 return ret; 897 } 898 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe); 899 900 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev) 901 { 902 struct lpass_data *drvdata = platform_get_drvdata(pdev); 903 904 if (drvdata->variant->exit) 905 drvdata->variant->exit(pdev); 906 907 908 return 0; 909 } 910 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove); 911 912 void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev) 913 { 914 struct lpass_data *drvdata = platform_get_drvdata(pdev); 915 916 if (drvdata->variant->exit) 917 drvdata->variant->exit(pdev); 918 919 } 920 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown); 921 922 MODULE_DESCRIPTION("QTi LPASS CPU Driver"); 923 MODULE_LICENSE("GPL v2"); 924