1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 4 * 5 * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <sound/pcm.h> 15 #include <sound/pcm_params.h> 16 #include <linux/regmap.h> 17 #include <sound/soc.h> 18 #include <sound/soc-dai.h> 19 #include "lpass-lpaif-reg.h" 20 #include "lpass.h" 21 22 #define LPASS_CPU_MAX_MI2S_LINES 4 23 #define LPASS_CPU_I2S_SD0_MASK BIT(0) 24 #define LPASS_CPU_I2S_SD1_MASK BIT(1) 25 #define LPASS_CPU_I2S_SD2_MASK BIT(2) 26 #define LPASS_CPU_I2S_SD3_MASK BIT(3) 27 #define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0) 28 #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2) 29 #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0) 30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 31 32 /* 33 * Channel maps for Quad channel playbacks on MI2S Secondary 34 */ 35 static struct snd_pcm_chmap_elem lpass_quad_chmaps[] = { 36 { .channels = 4, 37 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_RL, 38 SNDRV_CHMAP_FR, SNDRV_CHMAP_RR } }, 39 { } 40 }; 41 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev, 42 struct lpaif_i2sctl *i2sctl, struct regmap *map) 43 { 44 struct lpass_data *drvdata = dev_get_drvdata(dev); 45 struct lpass_variant *v = drvdata->variant; 46 47 i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback); 48 i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken); 49 i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode); 50 i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono); 51 i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen); 52 i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode); 53 i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono); 54 i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc); 55 i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth); 56 57 if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) || 58 IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) || 59 IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) || 60 IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) || 61 IS_ERR(i2sctl->bitwidth)) 62 return -EINVAL; 63 64 return 0; 65 } 66 67 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, 68 unsigned int freq, int dir) 69 { 70 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 71 int ret; 72 73 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); 74 if (ret) 75 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n", 76 freq, ret); 77 78 return ret; 79 } 80 81 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, 82 struct snd_soc_dai *dai) 83 { 84 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 85 int ret; 86 87 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]); 88 if (ret) { 89 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret); 90 return ret; 91 } 92 ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]); 93 if (ret) { 94 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 95 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 96 return ret; 97 } 98 return 0; 99 } 100 101 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, 102 struct snd_soc_dai *dai) 103 { 104 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 105 106 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 107 clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); 108 } 109 110 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, 111 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 112 { 113 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 114 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 115 unsigned int id = dai->driver->id; 116 snd_pcm_format_t format = params_format(params); 117 unsigned int channels = params_channels(params); 118 unsigned int rate = params_rate(params); 119 unsigned int mode; 120 unsigned int regval; 121 int bitwidth, ret; 122 123 bitwidth = snd_pcm_format_width(format); 124 if (bitwidth < 0) { 125 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth); 126 return bitwidth; 127 } 128 129 ret = regmap_fields_write(i2sctl->loopback, id, 130 LPAIF_I2SCTL_LOOPBACK_DISABLE); 131 if (ret) { 132 dev_err(dai->dev, "error updating loopback field: %d\n", ret); 133 return ret; 134 } 135 136 ret = regmap_fields_write(i2sctl->wssrc, id, 137 LPAIF_I2SCTL_WSSRC_INTERNAL); 138 if (ret) { 139 dev_err(dai->dev, "error updating wssrc field: %d\n", ret); 140 return ret; 141 } 142 143 switch (bitwidth) { 144 case 16: 145 regval = LPAIF_I2SCTL_BITWIDTH_16; 146 break; 147 case 24: 148 regval = LPAIF_I2SCTL_BITWIDTH_24; 149 break; 150 case 32: 151 regval = LPAIF_I2SCTL_BITWIDTH_32; 152 break; 153 default: 154 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth); 155 return -EINVAL; 156 } 157 158 ret = regmap_fields_write(i2sctl->bitwidth, id, regval); 159 if (ret) { 160 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret); 161 return ret; 162 } 163 164 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 165 mode = drvdata->mi2s_playback_sd_mode[id]; 166 else 167 mode = drvdata->mi2s_capture_sd_mode[id]; 168 169 if (!mode) { 170 dev_err(dai->dev, "no line is assigned\n"); 171 return -EINVAL; 172 } 173 174 switch (channels) { 175 case 1: 176 case 2: 177 switch (mode) { 178 case LPAIF_I2SCTL_MODE_QUAD01: 179 case LPAIF_I2SCTL_MODE_6CH: 180 case LPAIF_I2SCTL_MODE_8CH: 181 mode = LPAIF_I2SCTL_MODE_SD0; 182 break; 183 case LPAIF_I2SCTL_MODE_QUAD23: 184 mode = LPAIF_I2SCTL_MODE_SD2; 185 break; 186 } 187 188 break; 189 case 4: 190 if (mode < LPAIF_I2SCTL_MODE_QUAD01) { 191 dev_err(dai->dev, "cannot configure 4 channels with mode %d\n", 192 mode); 193 return -EINVAL; 194 } 195 196 switch (mode) { 197 case LPAIF_I2SCTL_MODE_6CH: 198 case LPAIF_I2SCTL_MODE_8CH: 199 mode = LPAIF_I2SCTL_MODE_QUAD01; 200 break; 201 } 202 break; 203 case 6: 204 if (mode < LPAIF_I2SCTL_MODE_6CH) { 205 dev_err(dai->dev, "cannot configure 6 channels with mode %d\n", 206 mode); 207 return -EINVAL; 208 } 209 210 switch (mode) { 211 case LPAIF_I2SCTL_MODE_8CH: 212 mode = LPAIF_I2SCTL_MODE_6CH; 213 break; 214 } 215 break; 216 case 8: 217 if (mode < LPAIF_I2SCTL_MODE_8CH) { 218 dev_err(dai->dev, "cannot configure 8 channels with mode %d\n", 219 mode); 220 return -EINVAL; 221 } 222 break; 223 default: 224 dev_err(dai->dev, "invalid channels given: %u\n", channels); 225 return -EINVAL; 226 } 227 228 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 229 ret = regmap_fields_write(i2sctl->spkmode, id, 230 LPAIF_I2SCTL_SPKMODE(mode)); 231 if (ret) { 232 dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n", 233 ret); 234 return ret; 235 } 236 if (channels >= 2) 237 ret = regmap_fields_write(i2sctl->spkmono, id, 238 LPAIF_I2SCTL_SPKMONO_STEREO); 239 else 240 ret = regmap_fields_write(i2sctl->spkmono, id, 241 LPAIF_I2SCTL_SPKMONO_MONO); 242 } else { 243 ret = regmap_fields_write(i2sctl->micmode, id, 244 LPAIF_I2SCTL_MICMODE(mode)); 245 if (ret) { 246 dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n", 247 ret); 248 return ret; 249 } 250 if (channels >= 2) 251 ret = regmap_fields_write(i2sctl->micmono, id, 252 LPAIF_I2SCTL_MICMONO_STEREO); 253 else 254 ret = regmap_fields_write(i2sctl->micmono, id, 255 LPAIF_I2SCTL_MICMONO_MONO); 256 } 257 258 if (ret) { 259 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n", 260 ret); 261 return ret; 262 } 263 264 ret = clk_set_rate(drvdata->mi2s_bit_clk[id], 265 rate * bitwidth * 2); 266 if (ret) { 267 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n", 268 rate * bitwidth * 2, ret); 269 return ret; 270 } 271 272 return 0; 273 } 274 275 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream, 276 int cmd, struct snd_soc_dai *dai) 277 { 278 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 279 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 280 unsigned int id = dai->driver->id; 281 int ret = -EINVAL; 282 283 switch (cmd) { 284 case SNDRV_PCM_TRIGGER_START: 285 case SNDRV_PCM_TRIGGER_RESUME: 286 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 287 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 288 ret = regmap_fields_write(i2sctl->spken, id, 289 LPAIF_I2SCTL_SPKEN_ENABLE); 290 } else { 291 ret = regmap_fields_write(i2sctl->micen, id, 292 LPAIF_I2SCTL_MICEN_ENABLE); 293 } 294 if (ret) 295 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 296 ret); 297 298 ret = clk_enable(drvdata->mi2s_bit_clk[id]); 299 if (ret) { 300 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 301 clk_disable(drvdata->mi2s_osr_clk[id]); 302 return ret; 303 } 304 break; 305 case SNDRV_PCM_TRIGGER_STOP: 306 case SNDRV_PCM_TRIGGER_SUSPEND: 307 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 308 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 309 ret = regmap_fields_write(i2sctl->spken, id, 310 LPAIF_I2SCTL_SPKEN_DISABLE); 311 } else { 312 ret = regmap_fields_write(i2sctl->micen, id, 313 LPAIF_I2SCTL_MICEN_DISABLE); 314 } 315 if (ret) 316 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 317 ret); 318 319 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]); 320 321 break; 322 } 323 324 return ret; 325 } 326 327 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = { 328 .set_sysclk = lpass_cpu_daiops_set_sysclk, 329 .startup = lpass_cpu_daiops_startup, 330 .shutdown = lpass_cpu_daiops_shutdown, 331 .hw_params = lpass_cpu_daiops_hw_params, 332 .trigger = lpass_cpu_daiops_trigger, 333 }; 334 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops); 335 336 int lpass_cpu_pcm_new(struct snd_soc_pcm_runtime *rtd, 337 struct snd_soc_dai *dai) 338 { 339 int ret; 340 struct snd_soc_dai_driver *drv = dai->driver; 341 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 342 343 if (drvdata->mi2s_playback_sd_mode[dai->id] == LPAIF_I2SCTL_MODE_QUAD01) { 344 ret = snd_pcm_add_chmap_ctls(rtd->pcm, SNDRV_PCM_STREAM_PLAYBACK, 345 lpass_quad_chmaps, drv->playback.channels_max, 0, 346 NULL); 347 if (ret < 0) 348 return ret; 349 } 350 351 return 0; 352 } 353 EXPORT_SYMBOL_GPL(lpass_cpu_pcm_new); 354 355 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai) 356 { 357 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 358 int ret; 359 360 /* ensure audio hardware is disabled */ 361 ret = regmap_write(drvdata->lpaif_map, 362 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0); 363 if (ret) 364 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret); 365 366 return ret; 367 } 368 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe); 369 370 static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component, 371 const struct of_phandle_args *args, 372 const char **dai_name) 373 { 374 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component); 375 struct lpass_variant *variant = drvdata->variant; 376 int id = args->args[0]; 377 int ret = -EINVAL; 378 int i; 379 380 for (i = 0; i < variant->num_dai; i++) { 381 if (variant->dai_driver[i].id == id) { 382 *dai_name = variant->dai_driver[i].name; 383 ret = 0; 384 break; 385 } 386 } 387 388 return ret; 389 } 390 391 static const struct snd_soc_component_driver lpass_cpu_comp_driver = { 392 .name = "lpass-cpu", 393 .of_xlate_dai_name = asoc_qcom_of_xlate_dai_name, 394 }; 395 396 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg) 397 { 398 struct lpass_data *drvdata = dev_get_drvdata(dev); 399 struct lpass_variant *v = drvdata->variant; 400 int i; 401 402 for (i = 0; i < v->i2s_ports; ++i) 403 if (reg == LPAIF_I2SCTL_REG(v, i)) 404 return true; 405 406 for (i = 0; i < v->irq_ports; ++i) { 407 if (reg == LPAIF_IRQEN_REG(v, i)) 408 return true; 409 if (reg == LPAIF_IRQCLEAR_REG(v, i)) 410 return true; 411 } 412 413 for (i = 0; i < v->rdma_channels; ++i) { 414 if (reg == LPAIF_RDMACTL_REG(v, i)) 415 return true; 416 if (reg == LPAIF_RDMABASE_REG(v, i)) 417 return true; 418 if (reg == LPAIF_RDMABUFF_REG(v, i)) 419 return true; 420 if (reg == LPAIF_RDMAPER_REG(v, i)) 421 return true; 422 } 423 424 for (i = 0; i < v->wrdma_channels; ++i) { 425 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 426 return true; 427 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 428 return true; 429 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 430 return true; 431 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 432 return true; 433 } 434 435 return false; 436 } 437 438 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg) 439 { 440 struct lpass_data *drvdata = dev_get_drvdata(dev); 441 struct lpass_variant *v = drvdata->variant; 442 int i; 443 444 for (i = 0; i < v->i2s_ports; ++i) 445 if (reg == LPAIF_I2SCTL_REG(v, i)) 446 return true; 447 448 for (i = 0; i < v->irq_ports; ++i) { 449 if (reg == LPAIF_IRQEN_REG(v, i)) 450 return true; 451 if (reg == LPAIF_IRQSTAT_REG(v, i)) 452 return true; 453 } 454 455 for (i = 0; i < v->rdma_channels; ++i) { 456 if (reg == LPAIF_RDMACTL_REG(v, i)) 457 return true; 458 if (reg == LPAIF_RDMABASE_REG(v, i)) 459 return true; 460 if (reg == LPAIF_RDMABUFF_REG(v, i)) 461 return true; 462 if (reg == LPAIF_RDMACURR_REG(v, i)) 463 return true; 464 if (reg == LPAIF_RDMAPER_REG(v, i)) 465 return true; 466 } 467 468 for (i = 0; i < v->wrdma_channels; ++i) { 469 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 470 return true; 471 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 472 return true; 473 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 474 return true; 475 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 476 return true; 477 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 478 return true; 479 } 480 481 return false; 482 } 483 484 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg) 485 { 486 struct lpass_data *drvdata = dev_get_drvdata(dev); 487 struct lpass_variant *v = drvdata->variant; 488 int i; 489 490 for (i = 0; i < v->irq_ports; ++i) 491 if (reg == LPAIF_IRQSTAT_REG(v, i)) 492 return true; 493 494 for (i = 0; i < v->rdma_channels; ++i) 495 if (reg == LPAIF_RDMACURR_REG(v, i)) 496 return true; 497 498 for (i = 0; i < v->wrdma_channels; ++i) 499 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 500 return true; 501 502 return false; 503 } 504 505 static struct regmap_config lpass_cpu_regmap_config = { 506 .name = "lpass_cpu", 507 .reg_bits = 32, 508 .reg_stride = 4, 509 .val_bits = 32, 510 .writeable_reg = lpass_cpu_regmap_writeable, 511 .readable_reg = lpass_cpu_regmap_readable, 512 .volatile_reg = lpass_cpu_regmap_volatile, 513 .cache_type = REGCACHE_FLAT, 514 }; 515 516 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map) 517 { 518 struct lpass_data *drvdata = dev_get_drvdata(dev); 519 struct lpass_variant *v = drvdata->variant; 520 unsigned int i; 521 struct lpass_hdmi_tx_ctl *tx_ctl; 522 struct regmap_field *legacy_en; 523 struct lpass_vbit_ctrl *vbit_ctl; 524 struct regmap_field *tx_parity; 525 struct lpass_dp_metadata_ctl *meta_ctl; 526 struct lpass_sstream_ctl *sstream_ctl; 527 struct regmap_field *ch_msb; 528 struct regmap_field *ch_lsb; 529 struct lpass_hdmitx_dmactl *tx_dmactl; 530 int rval; 531 532 tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL); 533 if (!tx_ctl) 534 return -ENOMEM; 535 536 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset); 537 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset); 538 drvdata->tx_ctl = tx_ctl; 539 540 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en); 541 drvdata->hdmitx_legacy_en = legacy_en; 542 543 vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL); 544 if (!vbit_ctl) 545 return -ENOMEM; 546 547 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit); 548 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream); 549 drvdata->vbit_ctl = vbit_ctl; 550 551 552 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity); 553 drvdata->hdmitx_parity_calc_en = tx_parity; 554 555 meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL); 556 if (!meta_ctl) 557 return -ENOMEM; 558 559 rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7); 560 if (rval) 561 return rval; 562 drvdata->meta_ctl = meta_ctl; 563 564 sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL); 565 if (!sstream_ctl) 566 return -ENOMEM; 567 568 rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9); 569 if (rval) 570 return rval; 571 572 drvdata->sstream_ctl = sstream_ctl; 573 574 for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) { 575 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb); 576 drvdata->hdmitx_ch_msb[i] = ch_msb; 577 578 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb); 579 drvdata->hdmitx_ch_lsb[i] = ch_lsb; 580 581 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL); 582 if (!tx_dmactl) 583 return -ENOMEM; 584 585 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs); 586 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr); 587 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel); 588 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel); 589 drvdata->hdmi_tx_dmactl[i] = tx_dmactl; 590 } 591 return 0; 592 } 593 594 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg) 595 { 596 struct lpass_data *drvdata = dev_get_drvdata(dev); 597 struct lpass_variant *v = drvdata->variant; 598 int i; 599 600 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 601 return true; 602 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 603 return true; 604 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 605 return true; 606 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 607 return true; 608 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 609 return true; 610 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 611 return true; 612 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 613 return true; 614 if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v)) 615 return true; 616 617 for (i = 0; i < v->hdmi_rdma_channels; i++) { 618 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 619 return true; 620 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 621 return true; 622 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 623 return true; 624 } 625 626 for (i = 0; i < v->hdmi_rdma_channels; ++i) { 627 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 628 return true; 629 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 630 return true; 631 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 632 return true; 633 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 634 return true; 635 } 636 return false; 637 } 638 639 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg) 640 { 641 struct lpass_data *drvdata = dev_get_drvdata(dev); 642 struct lpass_variant *v = drvdata->variant; 643 int i; 644 645 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 646 return true; 647 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 648 return true; 649 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 650 return true; 651 652 for (i = 0; i < v->hdmi_rdma_channels; i++) { 653 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 654 return true; 655 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 656 return true; 657 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 658 return true; 659 } 660 661 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 662 return true; 663 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 664 return true; 665 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 666 return true; 667 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 668 return true; 669 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 670 return true; 671 672 for (i = 0; i < v->hdmi_rdma_channels; ++i) { 673 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 674 return true; 675 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 676 return true; 677 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 678 return true; 679 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 680 return true; 681 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 682 return true; 683 } 684 685 return false; 686 } 687 688 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg) 689 { 690 struct lpass_data *drvdata = dev_get_drvdata(dev); 691 struct lpass_variant *v = drvdata->variant; 692 int i; 693 694 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 695 return true; 696 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 697 return true; 698 699 for (i = 0; i < v->hdmi_rdma_channels; ++i) { 700 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 701 return true; 702 } 703 return false; 704 } 705 706 static struct regmap_config lpass_hdmi_regmap_config = { 707 .name = "lpass_hdmi", 708 .reg_bits = 32, 709 .reg_stride = 4, 710 .val_bits = 32, 711 .writeable_reg = lpass_hdmi_regmap_writeable, 712 .readable_reg = lpass_hdmi_regmap_readable, 713 .volatile_reg = lpass_hdmi_regmap_volatile, 714 .cache_type = REGCACHE_FLAT, 715 }; 716 717 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev, 718 struct device_node *node, 719 const char *name) 720 { 721 unsigned int lines[LPASS_CPU_MAX_MI2S_LINES]; 722 unsigned int sd_line_mask = 0; 723 int num_lines, i; 724 725 num_lines = of_property_read_variable_u32_array(node, name, lines, 0, 726 LPASS_CPU_MAX_MI2S_LINES); 727 if (num_lines < 0) 728 return LPAIF_I2SCTL_MODE_NONE; 729 730 for (i = 0; i < num_lines; i++) 731 sd_line_mask |= BIT(lines[i]); 732 733 switch (sd_line_mask) { 734 case LPASS_CPU_I2S_SD0_MASK: 735 return LPAIF_I2SCTL_MODE_SD0; 736 case LPASS_CPU_I2S_SD1_MASK: 737 return LPAIF_I2SCTL_MODE_SD1; 738 case LPASS_CPU_I2S_SD2_MASK: 739 return LPAIF_I2SCTL_MODE_SD2; 740 case LPASS_CPU_I2S_SD3_MASK: 741 return LPAIF_I2SCTL_MODE_SD3; 742 case LPASS_CPU_I2S_SD0_1_MASK: 743 return LPAIF_I2SCTL_MODE_QUAD01; 744 case LPASS_CPU_I2S_SD2_3_MASK: 745 return LPAIF_I2SCTL_MODE_QUAD23; 746 case LPASS_CPU_I2S_SD0_1_2_MASK: 747 return LPAIF_I2SCTL_MODE_6CH; 748 case LPASS_CPU_I2S_SD0_1_2_3_MASK: 749 return LPAIF_I2SCTL_MODE_8CH; 750 default: 751 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask); 752 return LPAIF_I2SCTL_MODE_NONE; 753 } 754 } 755 756 static void of_lpass_cpu_parse_dai_data(struct device *dev, 757 struct lpass_data *data) 758 { 759 struct device_node *node; 760 int ret, id; 761 762 /* Allow all channels by default for backwards compatibility */ 763 for (id = 0; id < data->variant->num_dai; id++) { 764 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 765 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 766 } 767 768 for_each_child_of_node(dev->of_node, node) { 769 ret = of_property_read_u32(node, "reg", &id); 770 if (ret || id < 0) { 771 dev_err(dev, "valid dai id not found: %d\n", ret); 772 continue; 773 } 774 if (id == LPASS_DP_RX) { 775 data->hdmi_port_enable = 1; 776 } else { 777 data->mi2s_playback_sd_mode[id] = 778 of_lpass_cpu_parse_sd_lines(dev, node, 779 "qcom,playback-sd-lines"); 780 data->mi2s_capture_sd_mode[id] = 781 of_lpass_cpu_parse_sd_lines(dev, node, 782 "qcom,capture-sd-lines"); 783 } 784 } 785 } 786 787 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) 788 { 789 struct lpass_data *drvdata; 790 struct device_node *dsp_of_node; 791 struct resource *res; 792 struct lpass_variant *variant; 793 struct device *dev = &pdev->dev; 794 const struct of_device_id *match; 795 int ret, i, dai_id; 796 797 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); 798 if (dsp_of_node) { 799 dev_err(dev, "DSP exists and holds audio resources\n"); 800 return -EBUSY; 801 } 802 803 drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL); 804 if (!drvdata) 805 return -ENOMEM; 806 platform_set_drvdata(pdev, drvdata); 807 808 match = of_match_device(dev->driver->of_match_table, dev); 809 if (!match || !match->data) 810 return -EINVAL; 811 812 drvdata->variant = (struct lpass_variant *)match->data; 813 variant = drvdata->variant; 814 815 of_lpass_cpu_parse_dai_data(dev, drvdata); 816 817 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif"); 818 819 drvdata->lpaif = devm_ioremap_resource(dev, res); 820 if (IS_ERR(drvdata->lpaif)) 821 return PTR_ERR(drvdata->lpaif); 822 823 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant, 824 variant->wrdma_channels + 825 variant->wrdma_channel_start); 826 827 drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif, 828 &lpass_cpu_regmap_config); 829 if (IS_ERR(drvdata->lpaif_map)) { 830 dev_err(dev, "error initializing regmap: %ld\n", 831 PTR_ERR(drvdata->lpaif_map)); 832 return PTR_ERR(drvdata->lpaif_map); 833 } 834 835 if (drvdata->hdmi_port_enable) { 836 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif"); 837 838 drvdata->hdmiif = devm_ioremap_resource(dev, res); 839 if (IS_ERR(drvdata->hdmiif)) 840 return PTR_ERR(drvdata->hdmiif); 841 842 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant, 843 variant->hdmi_rdma_channels - 1); 844 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif, 845 &lpass_hdmi_regmap_config); 846 if (IS_ERR(drvdata->hdmiif_map)) { 847 dev_err(dev, "error initializing regmap: %ld\n", 848 PTR_ERR(drvdata->hdmiif_map)); 849 return PTR_ERR(drvdata->hdmiif_map); 850 } 851 } 852 853 if (variant->init) { 854 ret = variant->init(pdev); 855 if (ret) { 856 dev_err(dev, "error initializing variant: %d\n", ret); 857 return ret; 858 } 859 } 860 861 for (i = 0; i < variant->num_dai; i++) { 862 dai_id = variant->dai_driver[i].id; 863 if (dai_id == LPASS_DP_RX) 864 continue; 865 866 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev, 867 variant->dai_osr_clk_names[i]); 868 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev, 869 variant->dai_bit_clk_names[i]); 870 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) { 871 dev_err(dev, 872 "error getting %s: %ld\n", 873 variant->dai_bit_clk_names[i], 874 PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); 875 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); 876 } 877 if (drvdata->mi2s_playback_sd_mode[dai_id] == 878 LPAIF_I2SCTL_MODE_QUAD01) { 879 variant->dai_driver[dai_id].playback.channels_min = 4; 880 variant->dai_driver[dai_id].playback.channels_max = 4; 881 } 882 } 883 884 /* Allocation for i2sctl regmap fields */ 885 drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl), 886 GFP_KERNEL); 887 888 /* Initialize bitfields for dai I2SCTL register */ 889 ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl, 890 drvdata->lpaif_map); 891 if (ret) { 892 dev_err(dev, "error init i2sctl field: %d\n", ret); 893 return ret; 894 } 895 896 if (drvdata->hdmi_port_enable) { 897 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map); 898 if (ret) { 899 dev_err(dev, "%s error hdmi init failed\n", __func__); 900 return ret; 901 } 902 } 903 ret = devm_snd_soc_register_component(dev, 904 &lpass_cpu_comp_driver, 905 variant->dai_driver, 906 variant->num_dai); 907 if (ret) { 908 dev_err(dev, "error registering cpu driver: %d\n", ret); 909 goto err; 910 } 911 912 ret = asoc_qcom_lpass_platform_register(pdev); 913 if (ret) { 914 dev_err(dev, "error registering platform driver: %d\n", ret); 915 goto err; 916 } 917 918 err: 919 return ret; 920 } 921 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe); 922 923 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev) 924 { 925 struct lpass_data *drvdata = platform_get_drvdata(pdev); 926 927 if (drvdata->variant->exit) 928 drvdata->variant->exit(pdev); 929 930 931 return 0; 932 } 933 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove); 934 935 void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev) 936 { 937 struct lpass_data *drvdata = platform_get_drvdata(pdev); 938 939 if (drvdata->variant->exit) 940 drvdata->variant->exit(pdev); 941 942 } 943 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown); 944 945 MODULE_DESCRIPTION("QTi LPASS CPU Driver"); 946 MODULE_LICENSE("GPL v2"); 947