1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 4 * 5 * lpass-cdc-dma.c -- ALSA SoC CDC DMA CPU DAI driver for QTi LPASS 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/module.h> 10 #include <linux/export.h> 11 #include <sound/soc.h> 12 #include <sound/soc-dai.h> 13 14 #include "lpass-lpaif-reg.h" 15 #include "lpass.h" 16 17 #define CODEC_MEM_HZ_NORMAL 153600000 18 19 enum codec_dma_interfaces { 20 LPASS_CDC_DMA_INTERFACE1 = 1, 21 LPASS_CDC_DMA_INTERFACE2, 22 LPASS_CDC_DMA_INTERFACE3, 23 LPASS_CDC_DMA_INTERFACE4, 24 LPASS_CDC_DMA_INTERFACE5, 25 LPASS_CDC_DMA_INTERFACE6, 26 LPASS_CDC_DMA_INTERFACE7, 27 LPASS_CDC_DMA_INTERFACE8, 28 LPASS_CDC_DMA_INTERFACE9, 29 LPASS_CDC_DMA_INTERFACE10, 30 }; 31 32 static void __lpass_get_dmactl_handle(struct snd_pcm_substream *substream, struct snd_soc_dai *dai, 33 struct lpaif_dmactl **dmactl, int *id) 34 { 35 struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream); 36 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(soc_runtime, 0); 37 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 38 struct snd_pcm_runtime *rt = substream->runtime; 39 struct lpass_pcm_data *pcm_data = rt->private_data; 40 struct lpass_variant *v = drvdata->variant; 41 unsigned int dai_id = cpu_dai->driver->id; 42 43 switch (dai_id) { 44 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: 45 *dmactl = drvdata->rxtx_rd_dmactl; 46 *id = pcm_data->dma_ch; 47 break; 48 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: 49 *dmactl = drvdata->rxtx_wr_dmactl; 50 *id = pcm_data->dma_ch - v->rxtx_wrdma_channel_start; 51 break; 52 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: 53 *dmactl = drvdata->va_wr_dmactl; 54 *id = pcm_data->dma_ch - v->va_wrdma_channel_start; 55 break; 56 default: 57 dev_err(soc_runtime->dev, "invalid dai id for dma ctl: %d\n", dai_id); 58 break; 59 } 60 } 61 62 static int __lpass_get_codec_dma_intf_type(int dai_id) 63 { 64 int ret; 65 66 switch (dai_id) { 67 case LPASS_CDC_DMA_RX0: 68 case LPASS_CDC_DMA_TX0: 69 case LPASS_CDC_DMA_VA_TX0: 70 ret = LPASS_CDC_DMA_INTERFACE1; 71 break; 72 case LPASS_CDC_DMA_RX1: 73 case LPASS_CDC_DMA_TX1: 74 case LPASS_CDC_DMA_VA_TX1: 75 ret = LPASS_CDC_DMA_INTERFACE2; 76 break; 77 case LPASS_CDC_DMA_RX2: 78 case LPASS_CDC_DMA_TX2: 79 case LPASS_CDC_DMA_VA_TX2: 80 ret = LPASS_CDC_DMA_INTERFACE3; 81 break; 82 case LPASS_CDC_DMA_RX3: 83 case LPASS_CDC_DMA_TX3: 84 case LPASS_CDC_DMA_VA_TX3: 85 ret = LPASS_CDC_DMA_INTERFACE4; 86 break; 87 case LPASS_CDC_DMA_RX4: 88 case LPASS_CDC_DMA_TX4: 89 case LPASS_CDC_DMA_VA_TX4: 90 ret = LPASS_CDC_DMA_INTERFACE5; 91 break; 92 case LPASS_CDC_DMA_RX5: 93 case LPASS_CDC_DMA_TX5: 94 case LPASS_CDC_DMA_VA_TX5: 95 ret = LPASS_CDC_DMA_INTERFACE6; 96 break; 97 case LPASS_CDC_DMA_RX6: 98 case LPASS_CDC_DMA_TX6: 99 case LPASS_CDC_DMA_VA_TX6: 100 ret = LPASS_CDC_DMA_INTERFACE7; 101 break; 102 case LPASS_CDC_DMA_RX7: 103 case LPASS_CDC_DMA_TX7: 104 case LPASS_CDC_DMA_VA_TX7: 105 ret = LPASS_CDC_DMA_INTERFACE8; 106 break; 107 case LPASS_CDC_DMA_RX8: 108 case LPASS_CDC_DMA_TX8: 109 case LPASS_CDC_DMA_VA_TX8: 110 ret = LPASS_CDC_DMA_INTERFACE9; 111 break; 112 case LPASS_CDC_DMA_RX9: 113 ret = LPASS_CDC_DMA_INTERFACE10; 114 break; 115 default: 116 ret = -EINVAL; 117 break; 118 } 119 return ret; 120 } 121 122 static int __lpass_platform_codec_intf_init(struct snd_soc_dai *dai, 123 struct snd_pcm_substream *substream) 124 { 125 struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream); 126 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(soc_runtime, 0); 127 struct lpaif_dmactl *dmactl = NULL; 128 struct device *dev = soc_runtime->dev; 129 int ret, id, codec_intf; 130 unsigned int dai_id = cpu_dai->driver->id; 131 132 codec_intf = __lpass_get_codec_dma_intf_type(dai_id); 133 if (codec_intf < 0) { 134 dev_err(dev, "failed to get codec_intf: %d\n", codec_intf); 135 return codec_intf; 136 } 137 138 __lpass_get_dmactl_handle(substream, dai, &dmactl, &id); 139 if (!dmactl) 140 return -EINVAL; 141 142 ret = regmap_fields_write(dmactl->codec_intf, id, codec_intf); 143 if (ret) { 144 dev_err(dev, "error writing to dmactl codec_intf reg field: %d\n", ret); 145 return ret; 146 } 147 ret = regmap_fields_write(dmactl->codec_fs_sel, id, 0x0); 148 if (ret) { 149 dev_err(dev, "error writing to dmactl codec_fs_sel reg field: %d\n", ret); 150 return ret; 151 } 152 ret = regmap_fields_write(dmactl->codec_fs_delay, id, 0x0); 153 if (ret) { 154 dev_err(dev, "error writing to dmactl codec_fs_delay reg field: %d\n", ret); 155 return ret; 156 } 157 ret = regmap_fields_write(dmactl->codec_pack, id, 0x1); 158 if (ret) { 159 dev_err(dev, "error writing to dmactl codec_pack reg field: %d\n", ret); 160 return ret; 161 } 162 ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_ON); 163 if (ret) { 164 dev_err(dev, "error writing to dmactl codec_enable reg field: %d\n", ret); 165 return ret; 166 } 167 return 0; 168 } 169 170 static int lpass_cdc_dma_daiops_startup(struct snd_pcm_substream *substream, 171 struct snd_soc_dai *dai) 172 { 173 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 174 struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream); 175 176 switch (dai->id) { 177 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: 178 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: 179 clk_set_rate(drvdata->codec_mem0, CODEC_MEM_HZ_NORMAL); 180 clk_prepare_enable(drvdata->codec_mem0); 181 break; 182 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0: 183 clk_set_rate(drvdata->va_mem0, CODEC_MEM_HZ_NORMAL); 184 clk_prepare_enable(drvdata->va_mem0); 185 break; 186 default: 187 dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai->id); 188 break; 189 } 190 return 0; 191 } 192 193 static void lpass_cdc_dma_daiops_shutdown(struct snd_pcm_substream *substream, 194 struct snd_soc_dai *dai) 195 { 196 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 197 struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream); 198 199 switch (dai->id) { 200 case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: 201 case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: 202 clk_disable_unprepare(drvdata->codec_mem0); 203 break; 204 case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0: 205 clk_disable_unprepare(drvdata->va_mem0); 206 break; 207 default: 208 dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai->id); 209 break; 210 } 211 } 212 213 static int lpass_cdc_dma_daiops_hw_params(struct snd_pcm_substream *substream, 214 struct snd_pcm_hw_params *params, 215 struct snd_soc_dai *dai) 216 { 217 struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream); 218 struct lpaif_dmactl *dmactl = NULL; 219 unsigned int ret, regval; 220 unsigned int channels = params_channels(params); 221 int id; 222 223 switch (channels) { 224 case 1: 225 regval = LPASS_CDC_DMA_INTF_ONE_CHANNEL; 226 break; 227 case 2: 228 regval = LPASS_CDC_DMA_INTF_TWO_CHANNEL; 229 break; 230 case 4: 231 regval = LPASS_CDC_DMA_INTF_FOUR_CHANNEL; 232 break; 233 case 6: 234 regval = LPASS_CDC_DMA_INTF_SIX_CHANNEL; 235 break; 236 case 8: 237 regval = LPASS_CDC_DMA_INTF_EIGHT_CHANNEL; 238 break; 239 default: 240 dev_err(soc_runtime->dev, "invalid PCM config\n"); 241 return -EINVAL; 242 } 243 244 __lpass_get_dmactl_handle(substream, dai, &dmactl, &id); 245 if (!dmactl) 246 return -EINVAL; 247 248 ret = regmap_fields_write(dmactl->codec_channel, id, regval); 249 if (ret) { 250 dev_err(soc_runtime->dev, 251 "error writing to dmactl codec_channel reg field: %d\n", ret); 252 return ret; 253 } 254 return 0; 255 } 256 257 static int lpass_cdc_dma_daiops_trigger(struct snd_pcm_substream *substream, 258 int cmd, struct snd_soc_dai *dai) 259 { 260 struct snd_soc_pcm_runtime *soc_runtime = snd_soc_substream_to_rtd(substream); 261 struct lpaif_dmactl *dmactl = NULL; 262 int ret = 0, id; 263 264 switch (cmd) { 265 case SNDRV_PCM_TRIGGER_START: 266 case SNDRV_PCM_TRIGGER_RESUME: 267 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 268 __lpass_platform_codec_intf_init(dai, substream); 269 break; 270 case SNDRV_PCM_TRIGGER_STOP: 271 case SNDRV_PCM_TRIGGER_SUSPEND: 272 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 273 __lpass_get_dmactl_handle(substream, dai, &dmactl, &id); 274 if (!dmactl) 275 return -EINVAL; 276 277 ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_OFF); 278 if (ret) { 279 dev_err(soc_runtime->dev, 280 "error writing to dmactl codec_enable reg: %d\n", ret); 281 return ret; 282 } 283 break; 284 default: 285 ret = -EINVAL; 286 dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, cmd); 287 break; 288 } 289 return ret; 290 } 291 292 const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops = { 293 .startup = lpass_cdc_dma_daiops_startup, 294 .shutdown = lpass_cdc_dma_daiops_shutdown, 295 .hw_params = lpass_cdc_dma_daiops_hw_params, 296 .trigger = lpass_cdc_dma_daiops_trigger, 297 }; 298 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cdc_dma_dai_ops); 299 300 MODULE_DESCRIPTION("QTi LPASS CDC DMA Driver"); 301 MODULE_LICENSE("GPL"); 302