1 /* 2 * pxa2xx-i2s.c -- ALSA Soc Audio Layer 3 * 4 * Copyright 2005 Wolfson Microelectronics PLC. 5 * Author: Liam Girdwood 6 * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/device.h> 17 #include <linux/delay.h> 18 #include <linux/clk.h> 19 #include <linux/platform_device.h> 20 #include <sound/core.h> 21 #include <sound/pcm.h> 22 #include <sound/initval.h> 23 #include <sound/soc.h> 24 #include <sound/pxa2xx-lib.h> 25 26 #include <mach/hardware.h> 27 #include <mach/pxa-regs.h> 28 #include <mach/pxa2xx-gpio.h> 29 #include <mach/audio.h> 30 31 #include "pxa2xx-pcm.h" 32 #include "pxa2xx-i2s.h" 33 34 struct pxa2xx_gpio { 35 u32 sys; 36 u32 rx; 37 u32 tx; 38 u32 clk; 39 u32 frm; 40 }; 41 42 /* 43 * I2S Controller Register and Bit Definitions 44 */ 45 #define SACR0 __REG(0x40400000) /* Global Control Register */ 46 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ 47 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ 48 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ 49 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ 50 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ 51 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ 52 53 #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ 54 #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ 55 #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ 56 #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ 57 #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ 58 #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */ 59 #define SACR0_ENB (1 << 0) /* Enable I2S Link */ 60 #define SACR1_ENLBF (1 << 5) /* Enable Loopback */ 61 #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */ 62 #define SACR1_DREC (1 << 3) /* Disable Recording Function */ 63 #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */ 64 65 #define SASR0_I2SOFF (1 << 7) /* Controller Status */ 66 #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */ 67 #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */ 68 #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */ 69 #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */ 70 #define SASR0_BSY (1 << 2) /* I2S Busy */ 71 #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */ 72 #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */ 73 74 #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */ 75 #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */ 76 77 #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */ 78 #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */ 79 #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ 80 #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ 81 82 struct pxa_i2s_port { 83 u32 sadiv; 84 u32 sacr0; 85 u32 sacr1; 86 u32 saimr; 87 int master; 88 u32 fmt; 89 }; 90 static struct pxa_i2s_port pxa_i2s; 91 static struct clk *clk_i2s; 92 93 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = { 94 .name = "I2S PCM Stereo out", 95 .dev_addr = __PREG(SADR), 96 .drcmr = &DRCMR(3), 97 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 98 DCMD_BURST32 | DCMD_WIDTH4, 99 }; 100 101 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = { 102 .name = "I2S PCM Stereo in", 103 .dev_addr = __PREG(SADR), 104 .drcmr = &DRCMR(2), 105 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 106 DCMD_BURST32 | DCMD_WIDTH4, 107 }; 108 109 static struct pxa2xx_gpio gpio_bus[] = { 110 { /* I2S SoC Slave */ 111 .rx = GPIO29_SDATA_IN_I2S_MD, 112 .tx = GPIO30_SDATA_OUT_I2S_MD, 113 .clk = GPIO28_BITCLK_IN_I2S_MD, 114 .frm = GPIO31_SYNC_I2S_MD, 115 }, 116 { /* I2S SoC Master */ 117 .rx = GPIO29_SDATA_IN_I2S_MD, 118 .tx = GPIO30_SDATA_OUT_I2S_MD, 119 .clk = GPIO28_BITCLK_OUT_I2S_MD, 120 .frm = GPIO31_SYNC_I2S_MD, 121 }, 122 }; 123 124 static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream) 125 { 126 struct snd_soc_pcm_runtime *rtd = substream->private_data; 127 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; 128 129 if (IS_ERR(clk_i2s)) 130 return PTR_ERR(clk_i2s); 131 132 if (!cpu_dai->active) { 133 SACR0 |= SACR0_RST; 134 SACR0 = 0; 135 } 136 137 return 0; 138 } 139 140 /* wait for I2S controller to be ready */ 141 static int pxa_i2s_wait(void) 142 { 143 int i; 144 145 /* flush the Rx FIFO */ 146 for(i = 0; i < 16; i++) 147 SADR; 148 return 0; 149 } 150 151 static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, 152 unsigned int fmt) 153 { 154 /* interface format */ 155 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 156 case SND_SOC_DAIFMT_I2S: 157 pxa_i2s.fmt = 0; 158 break; 159 case SND_SOC_DAIFMT_LEFT_J: 160 pxa_i2s.fmt = SACR1_AMSL; 161 break; 162 } 163 164 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 165 case SND_SOC_DAIFMT_CBS_CFS: 166 pxa_i2s.master = 1; 167 break; 168 case SND_SOC_DAIFMT_CBM_CFS: 169 pxa_i2s.master = 0; 170 break; 171 default: 172 break; 173 } 174 return 0; 175 } 176 177 static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 178 int clk_id, unsigned int freq, int dir) 179 { 180 if (clk_id != PXA2XX_I2S_SYSCLK) 181 return -ENODEV; 182 183 if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT) 184 pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys); 185 186 return 0; 187 } 188 189 static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream, 190 struct snd_pcm_hw_params *params) 191 { 192 struct snd_soc_pcm_runtime *rtd = substream->private_data; 193 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; 194 195 pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx); 196 pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx); 197 pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm); 198 pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk); 199 BUG_ON(IS_ERR(clk_i2s)); 200 clk_enable(clk_i2s); 201 pxa_i2s_wait(); 202 203 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 204 cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out; 205 else 206 cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in; 207 208 /* is port used by another stream */ 209 if (!(SACR0 & SACR0_ENB)) { 210 211 SACR0 = 0; 212 SACR1 = 0; 213 if (pxa_i2s.master) 214 SACR0 |= SACR0_BCKD; 215 216 SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1); 217 SACR1 |= pxa_i2s.fmt; 218 } 219 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 220 SAIMR |= SAIMR_TFS; 221 else 222 SAIMR |= SAIMR_RFS; 223 224 switch (params_rate(params)) { 225 case 8000: 226 SADIV = 0x48; 227 break; 228 case 11025: 229 SADIV = 0x34; 230 break; 231 case 16000: 232 SADIV = 0x24; 233 break; 234 case 22050: 235 SADIV = 0x1a; 236 break; 237 case 44100: 238 SADIV = 0xd; 239 break; 240 case 48000: 241 SADIV = 0xc; 242 break; 243 case 96000: /* not in manual and possibly slightly inaccurate */ 244 SADIV = 0x6; 245 break; 246 } 247 248 return 0; 249 } 250 251 static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd) 252 { 253 int ret = 0; 254 255 switch (cmd) { 256 case SNDRV_PCM_TRIGGER_START: 257 SACR0 |= SACR0_ENB; 258 break; 259 case SNDRV_PCM_TRIGGER_RESUME: 260 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 261 case SNDRV_PCM_TRIGGER_STOP: 262 case SNDRV_PCM_TRIGGER_SUSPEND: 263 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 264 break; 265 default: 266 ret = -EINVAL; 267 } 268 269 return ret; 270 } 271 272 static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream) 273 { 274 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 275 SACR1 |= SACR1_DRPL; 276 SAIMR &= ~SAIMR_TFS; 277 } else { 278 SACR1 |= SACR1_DREC; 279 SAIMR &= ~SAIMR_RFS; 280 } 281 282 if (SACR1 & (SACR1_DREC | SACR1_DRPL)) { 283 SACR0 &= ~SACR0_ENB; 284 pxa_i2s_wait(); 285 clk_disable(clk_i2s); 286 } 287 288 clk_put(clk_i2s); 289 } 290 291 #ifdef CONFIG_PM 292 static int pxa2xx_i2s_suspend(struct platform_device *dev, 293 struct snd_soc_dai *dai) 294 { 295 if (!dai->active) 296 return 0; 297 298 /* store registers */ 299 pxa_i2s.sacr0 = SACR0; 300 pxa_i2s.sacr1 = SACR1; 301 pxa_i2s.saimr = SAIMR; 302 pxa_i2s.sadiv = SADIV; 303 304 /* deactivate link */ 305 SACR0 &= ~SACR0_ENB; 306 pxa_i2s_wait(); 307 return 0; 308 } 309 310 static int pxa2xx_i2s_resume(struct platform_device *pdev, 311 struct snd_soc_dai *dai) 312 { 313 if (!dai->active) 314 return 0; 315 316 pxa_i2s_wait(); 317 318 SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB; 319 SACR1 = pxa_i2s.sacr1; 320 SAIMR = pxa_i2s.saimr; 321 SADIV = pxa_i2s.sadiv; 322 SACR0 |= SACR0_ENB; 323 324 return 0; 325 } 326 327 #else 328 #define pxa2xx_i2s_suspend NULL 329 #define pxa2xx_i2s_resume NULL 330 #endif 331 332 #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 333 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 334 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000) 335 336 struct snd_soc_dai pxa_i2s_dai = { 337 .name = "pxa2xx-i2s", 338 .id = 0, 339 .type = SND_SOC_DAI_I2S, 340 .suspend = pxa2xx_i2s_suspend, 341 .resume = pxa2xx_i2s_resume, 342 .playback = { 343 .channels_min = 2, 344 .channels_max = 2, 345 .rates = PXA2XX_I2S_RATES, 346 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 347 .capture = { 348 .channels_min = 2, 349 .channels_max = 2, 350 .rates = PXA2XX_I2S_RATES, 351 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 352 .ops = { 353 .startup = pxa2xx_i2s_startup, 354 .shutdown = pxa2xx_i2s_shutdown, 355 .trigger = pxa2xx_i2s_trigger, 356 .hw_params = pxa2xx_i2s_hw_params,}, 357 .dai_ops = { 358 .set_fmt = pxa2xx_i2s_set_dai_fmt, 359 .set_sysclk = pxa2xx_i2s_set_dai_sysclk, 360 }, 361 }; 362 363 EXPORT_SYMBOL_GPL(pxa_i2s_dai); 364 365 static int pxa2xx_i2s_probe(struct platform_device *dev) 366 { 367 clk_i2s = clk_get(&dev->dev, "I2SCLK"); 368 return IS_ERR(clk_i2s) ? PTR_ERR(clk_i2s) : 0; 369 } 370 371 static int __devexit pxa2xx_i2s_remove(struct platform_device *dev) 372 { 373 clk_put(clk_i2s); 374 clk_i2s = ERR_PTR(-ENOENT); 375 return 0; 376 } 377 378 static struct platform_driver pxa2xx_i2s_driver = { 379 .probe = pxa2xx_i2s_probe, 380 .remove = __devexit_p(pxa2xx_i2s_remove), 381 382 .driver = { 383 .name = "pxa2xx-i2s", 384 .owner = THIS_MODULE, 385 }, 386 }; 387 388 static int __init pxa2xx_i2s_init(void) 389 { 390 if (cpu_is_pxa27x()) 391 gpio_bus[1].sys = GPIO113_I2S_SYSCLK_MD; 392 else 393 gpio_bus[1].sys = GPIO32_SYSCLK_I2S_MD; 394 395 clk_i2s = ERR_PTR(-ENOENT); 396 return platform_driver_register(&pxa2xx_i2s_driver); 397 } 398 399 static void __exit pxa2xx_i2s_exit(void) 400 { 401 platform_driver_unregister(&pxa2xx_i2s_driver); 402 } 403 404 module_init(pxa2xx_i2s_init); 405 module_exit(pxa2xx_i2s_exit); 406 407 /* Module information */ 408 MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com"); 409 MODULE_DESCRIPTION("pxa2xx I2S SoC Interface"); 410 MODULE_LICENSE("GPL"); 411