xref: /openbmc/linux/sound/soc/pxa/pxa2xx-i2s.c (revision 52358ba3) 
1 /*
2  * pxa2xx-i2s.c  --  ALSA Soc Audio Layer
3  *
4  * Copyright 2005 Wolfson Microelectronics PLC.
5  * Author: Liam Girdwood
6  *         liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
7  *
8  *  This program is free software; you can redistribute  it and/or modify it
9  *  under  the terms of  the GNU General  Public License as published by the
10  *  Free Software Foundation;  either version 2 of the  License, or (at your
11  *  option) any later version.
12  */
13 
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/delay.h>
18 #include <linux/clk.h>
19 #include <linux/platform_device.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/initval.h>
23 #include <sound/soc.h>
24 
25 #include <mach/hardware.h>
26 #include <mach/pxa-regs.h>
27 #include <mach/pxa2xx-gpio.h>
28 #include <mach/audio.h>
29 
30 #include "pxa2xx-pcm.h"
31 #include "pxa2xx-i2s.h"
32 
33 /*
34  * I2S Controller Register and Bit Definitions
35  */
36 #define SACR0		__REG(0x40400000)  /* Global Control Register */
37 #define SACR1		__REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
38 #define SASR0		__REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
39 #define SAIMR		__REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
40 #define SAICR		__REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
41 #define SADIV		__REG(0x40400060)  /* Audio Clock Divider Register. */
42 #define SADR		__REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
43 
44 #define SACR0_RFTH(x)	((x) << 12)	/* Rx FIFO Interrupt or DMA Trigger Threshold */
45 #define SACR0_TFTH(x)	((x) << 8)	/* Tx FIFO Interrupt or DMA Trigger Threshold */
46 #define SACR0_STRF	(1 << 5)	/* FIFO Select for EFWR Special Function */
47 #define SACR0_EFWR	(1 << 4)	/* Enable EFWR Function  */
48 #define SACR0_RST	(1 << 3)	/* FIFO, i2s Register Reset */
49 #define SACR0_BCKD	(1 << 2) 	/* Bit Clock Direction */
50 #define SACR0_ENB	(1 << 0)	/* Enable I2S Link */
51 #define SACR1_ENLBF	(1 << 5)	/* Enable Loopback */
52 #define SACR1_DRPL	(1 << 4) 	/* Disable Replaying Function */
53 #define SACR1_DREC	(1 << 3)	/* Disable Recording Function */
54 #define SACR1_AMSL	(1 << 0)	/* Specify Alternate Mode */
55 
56 #define SASR0_I2SOFF	(1 << 7)	/* Controller Status */
57 #define SASR0_ROR	(1 << 6)	/* Rx FIFO Overrun */
58 #define SASR0_TUR	(1 << 5)	/* Tx FIFO Underrun */
59 #define SASR0_RFS	(1 << 4)	/* Rx FIFO Service Request */
60 #define SASR0_TFS	(1 << 3)	/* Tx FIFO Service Request */
61 #define SASR0_BSY	(1 << 2)	/* I2S Busy */
62 #define SASR0_RNE	(1 << 1)	/* Rx FIFO Not Empty */
63 #define SASR0_TNF	(1 << 0) 	/* Tx FIFO Not Empty */
64 
65 #define SAICR_ROR	(1 << 6)	/* Clear Rx FIFO Overrun Interrupt */
66 #define SAICR_TUR	(1 << 5)	/* Clear Tx FIFO Underrun Interrupt */
67 
68 #define SAIMR_ROR	(1 << 6)	/* Enable Rx FIFO Overrun Condition Interrupt */
69 #define SAIMR_TUR	(1 << 5)	/* Enable Tx FIFO Underrun Condition Interrupt */
70 #define SAIMR_RFS	(1 << 4)	/* Enable Rx FIFO Service Interrupt */
71 #define SAIMR_TFS	(1 << 3)	/* Enable Tx FIFO Service Interrupt */
72 
73 struct pxa_i2s_port {
74 	u32 sadiv;
75 	u32 sacr0;
76 	u32 sacr1;
77 	u32 saimr;
78 	int master;
79 	u32 fmt;
80 };
81 static struct pxa_i2s_port pxa_i2s;
82 static struct clk *clk_i2s;
83 
84 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
85 	.name			= "I2S PCM Stereo out",
86 	.dev_addr		= __PREG(SADR),
87 	.drcmr			= &DRCMR(3),
88 	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
89 				  DCMD_BURST32 | DCMD_WIDTH4,
90 };
91 
92 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
93 	.name			= "I2S PCM Stereo in",
94 	.dev_addr		= __PREG(SADR),
95 	.drcmr			= &DRCMR(2),
96 	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
97 				  DCMD_BURST32 | DCMD_WIDTH4,
98 };
99 
100 static struct pxa2xx_gpio gpio_bus[] = {
101 	{ /* I2S SoC Slave */
102 		.rx = GPIO29_SDATA_IN_I2S_MD,
103 		.tx = GPIO30_SDATA_OUT_I2S_MD,
104 		.clk = GPIO28_BITCLK_IN_I2S_MD,
105 		.frm = GPIO31_SYNC_I2S_MD,
106 	},
107 	{ /* I2S SoC Master */
108 #ifdef CONFIG_PXA27x
109 		.sys = GPIO113_I2S_SYSCLK_MD,
110 #else
111 		.sys = GPIO32_SYSCLK_I2S_MD,
112 #endif
113 		.rx = GPIO29_SDATA_IN_I2S_MD,
114 		.tx = GPIO30_SDATA_OUT_I2S_MD,
115 		.clk = GPIO28_BITCLK_OUT_I2S_MD,
116 		.frm = GPIO31_SYNC_I2S_MD,
117 	},
118 };
119 
120 static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
121 {
122 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
123 	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
124 
125 	if (IS_ERR(clk_i2s))
126 		return PTR_ERR(clk_i2s);
127 
128 	if (!cpu_dai->active) {
129 		SACR0 |= SACR0_RST;
130 		SACR0 = 0;
131 	}
132 
133 	return 0;
134 }
135 
136 /* wait for I2S controller to be ready */
137 static int pxa_i2s_wait(void)
138 {
139 	int i;
140 
141 	/* flush the Rx FIFO */
142 	for(i = 0; i < 16; i++)
143 		SADR;
144 	return 0;
145 }
146 
147 static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
148 		unsigned int fmt)
149 {
150 	/* interface format */
151 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
152 	case SND_SOC_DAIFMT_I2S:
153 		pxa_i2s.fmt = 0;
154 		break;
155 	case SND_SOC_DAIFMT_LEFT_J:
156 		pxa_i2s.fmt = SACR1_AMSL;
157 		break;
158 	}
159 
160 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
161 	case SND_SOC_DAIFMT_CBS_CFS:
162 		pxa_i2s.master = 1;
163 		break;
164 	case SND_SOC_DAIFMT_CBM_CFS:
165 		pxa_i2s.master = 0;
166 		break;
167 	default:
168 		break;
169 	}
170 	return 0;
171 }
172 
173 static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
174 		int clk_id, unsigned int freq, int dir)
175 {
176 	if (clk_id != PXA2XX_I2S_SYSCLK)
177 		return -ENODEV;
178 
179 	if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
180 		pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
181 
182 	return 0;
183 }
184 
185 static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
186 				struct snd_pcm_hw_params *params)
187 {
188 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
189 	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
190 
191 	pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
192 	pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
193 	pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
194 	pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
195 	BUG_ON(IS_ERR(clk_i2s));
196 	clk_enable(clk_i2s);
197 	pxa_i2s_wait();
198 
199 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
200 		cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
201 	else
202 		cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
203 
204 	/* is port used by another stream */
205 	if (!(SACR0 & SACR0_ENB)) {
206 
207 		SACR0 = 0;
208 		SACR1 = 0;
209 		if (pxa_i2s.master)
210 			SACR0 |= SACR0_BCKD;
211 
212 		SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
213 		SACR1 |= pxa_i2s.fmt;
214 	}
215 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
216 		SAIMR |= SAIMR_TFS;
217 	else
218 		SAIMR |= SAIMR_RFS;
219 
220 	switch (params_rate(params)) {
221 	case 8000:
222 		SADIV = 0x48;
223 		break;
224 	case 11025:
225 		SADIV = 0x34;
226 		break;
227 	case 16000:
228 		SADIV = 0x24;
229 		break;
230 	case 22050:
231 		SADIV = 0x1a;
232 		break;
233 	case 44100:
234 		SADIV = 0xd;
235 		break;
236 	case 48000:
237 		SADIV = 0xc;
238 		break;
239 	case 96000: /* not in manual and possibly slightly inaccurate */
240 		SADIV = 0x6;
241 		break;
242 	}
243 
244 	return 0;
245 }
246 
247 static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
248 {
249 	int ret = 0;
250 
251 	switch (cmd) {
252 	case SNDRV_PCM_TRIGGER_START:
253 		SACR0 |= SACR0_ENB;
254 		break;
255 	case SNDRV_PCM_TRIGGER_RESUME:
256 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
257 	case SNDRV_PCM_TRIGGER_STOP:
258 	case SNDRV_PCM_TRIGGER_SUSPEND:
259 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
260 		break;
261 	default:
262 		ret = -EINVAL;
263 	}
264 
265 	return ret;
266 }
267 
268 static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
269 {
270 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
271 		SACR1 |= SACR1_DRPL;
272 		SAIMR &= ~SAIMR_TFS;
273 	} else {
274 		SACR1 |= SACR1_DREC;
275 		SAIMR &= ~SAIMR_RFS;
276 	}
277 
278 	if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
279 		SACR0 &= ~SACR0_ENB;
280 		pxa_i2s_wait();
281 		clk_disable(clk_i2s);
282 	}
283 
284 	clk_put(clk_i2s);
285 }
286 
287 #ifdef CONFIG_PM
288 static int pxa2xx_i2s_suspend(struct platform_device *dev,
289 	struct snd_soc_dai *dai)
290 {
291 	if (!dai->active)
292 		return 0;
293 
294 	/* store registers */
295 	pxa_i2s.sacr0 = SACR0;
296 	pxa_i2s.sacr1 = SACR1;
297 	pxa_i2s.saimr = SAIMR;
298 	pxa_i2s.sadiv = SADIV;
299 
300 	/* deactivate link */
301 	SACR0 &= ~SACR0_ENB;
302 	pxa_i2s_wait();
303 	return 0;
304 }
305 
306 static int pxa2xx_i2s_resume(struct platform_device *pdev,
307 	struct snd_soc_dai *dai)
308 {
309 	if (!dai->active)
310 		return 0;
311 
312 	pxa_i2s_wait();
313 
314 	SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
315 	SACR1 = pxa_i2s.sacr1;
316 	SAIMR = pxa_i2s.saimr;
317 	SADIV = pxa_i2s.sadiv;
318 	SACR0 |= SACR0_ENB;
319 
320 	return 0;
321 }
322 
323 #else
324 #define pxa2xx_i2s_suspend	NULL
325 #define pxa2xx_i2s_resume	NULL
326 #endif
327 
328 #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
329 		SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
330 		SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
331 
332 struct snd_soc_dai pxa_i2s_dai = {
333 	.name = "pxa2xx-i2s",
334 	.id = 0,
335 	.type = SND_SOC_DAI_I2S,
336 	.suspend = pxa2xx_i2s_suspend,
337 	.resume = pxa2xx_i2s_resume,
338 	.playback = {
339 		.channels_min = 2,
340 		.channels_max = 2,
341 		.rates = PXA2XX_I2S_RATES,
342 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
343 	.capture = {
344 		.channels_min = 2,
345 		.channels_max = 2,
346 		.rates = PXA2XX_I2S_RATES,
347 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
348 	.ops = {
349 		.startup = pxa2xx_i2s_startup,
350 		.shutdown = pxa2xx_i2s_shutdown,
351 		.trigger = pxa2xx_i2s_trigger,
352 		.hw_params = pxa2xx_i2s_hw_params,},
353 	.dai_ops = {
354 		.set_fmt = pxa2xx_i2s_set_dai_fmt,
355 		.set_sysclk = pxa2xx_i2s_set_dai_sysclk,
356 	},
357 };
358 
359 EXPORT_SYMBOL_GPL(pxa_i2s_dai);
360 
361 static int pxa2xx_i2s_probe(struct platform_device *dev)
362 {
363 	clk_i2s = clk_get(&dev->dev, "I2SCLK");
364 	return IS_ERR(clk_i2s) ? PTR_ERR(clk_i2s) : 0;
365 }
366 
367 static int __devexit pxa2xx_i2s_remove(struct platform_device *dev)
368 {
369 	clk_put(clk_i2s);
370 	clk_i2s = ERR_PTR(-ENOENT);
371 	return 0;
372 }
373 
374 static struct platform_driver pxa2xx_i2s_driver = {
375 	.probe = pxa2xx_i2s_probe,
376 	.remove = __devexit_p(pxa2xx_i2s_remove),
377 
378 	.driver = {
379 		.name = "pxa2xx-i2s",
380 		.owner = THIS_MODULE,
381 	},
382 };
383 
384 static int __init pxa2xx_i2s_init(void)
385 {
386 	clk_i2s = ERR_PTR(-ENOENT);
387 	return platform_driver_register(&pxa2xx_i2s_driver);
388 }
389 
390 static void __exit pxa2xx_i2s_exit(void)
391 {
392 	platform_driver_unregister(&pxa2xx_i2s_driver);
393 }
394 
395 module_init(pxa2xx_i2s_init);
396 module_exit(pxa2xx_i2s_exit);
397 
398 /* Module information */
399 MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
400 MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
401 MODULE_LICENSE("GPL");
402