1 /* 2 * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip. 3 * 4 * Author: Nicolas Pitre 5 * Created: Dec 02, 2004 6 * Copyright: MontaVista Software Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/interrupt.h> 17 #include <linux/wait.h> 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/ac97_codec.h> 24 #include <sound/initval.h> 25 #include <sound/soc.h> 26 27 #include <asm/irq.h> 28 #include <linux/mutex.h> 29 #include <asm/arch/hardware.h> 30 #include <asm/arch/pxa-regs.h> 31 #include <asm/arch/pxa2xx-gpio.h> 32 #include <asm/arch/audio.h> 33 34 #include "pxa2xx-pcm.h" 35 #include "pxa2xx-ac97.h" 36 37 static DEFINE_MUTEX(car_mutex); 38 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); 39 static volatile long gsr_bits; 40 static struct clk *ac97_clk; 41 #ifdef CONFIG_PXA27x 42 static struct clk *ac97conf_clk; 43 #endif 44 45 /* 46 * Beware PXA27x bugs: 47 * 48 * o Slot 12 read from modem space will hang controller. 49 * o CDONE, SDONE interrupt fails after any slot 12 IO. 50 * 51 * We therefore have an hybrid approach for waiting on SDONE (interrupt or 52 * 1 jiffy timeout if interrupt never comes). 53 */ 54 55 static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, 56 unsigned short reg) 57 { 58 unsigned short val = -1; 59 volatile u32 *reg_addr; 60 61 mutex_lock(&car_mutex); 62 63 /* set up primary or secondary codec/modem space */ 64 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 65 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 66 #else 67 if (reg == AC97_GPIO_STATUS) 68 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; 69 else 70 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 71 #endif 72 reg_addr += (reg >> 1); 73 74 #ifndef CONFIG_PXA27x 75 if (reg == AC97_GPIO_STATUS) { 76 /* read from controller cache */ 77 val = *reg_addr; 78 goto out; 79 } 80 #endif 81 82 /* start read access across the ac97 link */ 83 GSR = GSR_CDONE | GSR_SDONE; 84 gsr_bits = 0; 85 val = *reg_addr; 86 87 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); 88 if (!((GSR | gsr_bits) & GSR_SDONE)) { 89 printk(KERN_ERR "%s: read error (ac97_reg=%x GSR=%#lx)\n", 90 __func__, reg, GSR | gsr_bits); 91 val = -1; 92 goto out; 93 } 94 95 /* valid data now */ 96 GSR = GSR_CDONE | GSR_SDONE; 97 gsr_bits = 0; 98 val = *reg_addr; 99 /* but we've just started another cycle... */ 100 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); 101 102 out: mutex_unlock(&car_mutex); 103 return val; 104 } 105 106 static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 107 unsigned short val) 108 { 109 volatile u32 *reg_addr; 110 111 mutex_lock(&car_mutex); 112 113 /* set up primary or secondary codec/modem space */ 114 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 115 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 116 #else 117 if (reg == AC97_GPIO_STATUS) 118 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; 119 else 120 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 121 #endif 122 reg_addr += (reg >> 1); 123 124 GSR = GSR_CDONE | GSR_SDONE; 125 gsr_bits = 0; 126 *reg_addr = val; 127 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1); 128 if (!((GSR | gsr_bits) & GSR_CDONE)) 129 printk(KERN_ERR "%s: write error (ac97_reg=%x GSR=%#lx)\n", 130 __func__, reg, GSR | gsr_bits); 131 132 mutex_unlock(&car_mutex); 133 } 134 135 static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97) 136 { 137 #ifdef CONFIG_PXA3xx 138 int timeout = 100; 139 #endif 140 gsr_bits = 0; 141 142 #ifdef CONFIG_PXA27x 143 /* warm reset broken on Bulverde, 144 so manually keep AC97 reset high */ 145 pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 146 udelay(10); 147 GCR |= GCR_WARM_RST; 148 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 149 udelay(500); 150 #elif defined(CONFIG_PXA3xx) 151 /* Can't use interrupts */ 152 GCR |= GCR_WARM_RST; 153 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--) 154 mdelay(1); 155 #else 156 GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN; 157 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 158 #endif 159 160 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) 161 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", 162 __func__, gsr_bits); 163 164 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 165 GCR |= GCR_SDONE_IE|GCR_CDONE_IE; 166 } 167 168 static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97) 169 { 170 #ifdef CONFIG_PXA3xx 171 int timeout = 1000; 172 173 /* Hold CLKBPB for 100us */ 174 GCR = 0; 175 GCR = GCR_CLKBPB; 176 udelay(100); 177 GCR = 0; 178 #endif 179 180 GCR &= GCR_COLD_RST; /* clear everything but nCRST */ 181 GCR &= ~GCR_COLD_RST; /* then assert nCRST */ 182 183 gsr_bits = 0; 184 #ifdef CONFIG_PXA27x 185 /* PXA27x Developers Manual section 13.5.2.2.1 */ 186 clk_enable(ac97conf_clk); 187 udelay(5); 188 clk_disable(ac97conf_clk); 189 GCR = GCR_COLD_RST; 190 udelay(50); 191 #elif defined(CONFIG_PXA3xx) 192 /* Can't use interrupts on PXA3xx */ 193 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 194 195 GCR = GCR_WARM_RST | GCR_COLD_RST; 196 while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--) 197 mdelay(10); 198 #else 199 GCR = GCR_COLD_RST; 200 GCR |= GCR_CDONE_IE|GCR_SDONE_IE; 201 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 202 #endif 203 204 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) 205 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", 206 __func__, gsr_bits); 207 208 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 209 GCR |= GCR_SDONE_IE|GCR_CDONE_IE; 210 } 211 212 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id) 213 { 214 long status; 215 216 status = GSR; 217 if (status) { 218 GSR = status; 219 gsr_bits |= status; 220 wake_up(&gsr_wq); 221 222 #ifdef CONFIG_PXA27x 223 /* Although we don't use those we still need to clear them 224 since they tend to spuriously trigger when MMC is used 225 (hardware bug? go figure)... */ 226 MISR = MISR_EOC; 227 PISR = PISR_EOC; 228 MCSR = MCSR_EOC; 229 #endif 230 231 return IRQ_HANDLED; 232 } 233 234 return IRQ_NONE; 235 } 236 237 struct snd_ac97_bus_ops soc_ac97_ops = { 238 .read = pxa2xx_ac97_read, 239 .write = pxa2xx_ac97_write, 240 .warm_reset = pxa2xx_ac97_warm_reset, 241 .reset = pxa2xx_ac97_cold_reset, 242 }; 243 244 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = { 245 .name = "AC97 PCM Stereo out", 246 .dev_addr = __PREG(PCDR), 247 .drcmr = &DRCMRTXPCDR, 248 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 249 DCMD_BURST32 | DCMD_WIDTH4, 250 }; 251 252 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = { 253 .name = "AC97 PCM Stereo in", 254 .dev_addr = __PREG(PCDR), 255 .drcmr = &DRCMRRXPCDR, 256 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 257 DCMD_BURST32 | DCMD_WIDTH4, 258 }; 259 260 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = { 261 .name = "AC97 Aux PCM (Slot 5) Mono out", 262 .dev_addr = __PREG(MODR), 263 .drcmr = &DRCMRTXMODR, 264 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 265 DCMD_BURST16 | DCMD_WIDTH2, 266 }; 267 268 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = { 269 .name = "AC97 Aux PCM (Slot 5) Mono in", 270 .dev_addr = __PREG(MODR), 271 .drcmr = &DRCMRRXMODR, 272 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 273 DCMD_BURST16 | DCMD_WIDTH2, 274 }; 275 276 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = { 277 .name = "AC97 Mic PCM (Slot 6) Mono in", 278 .dev_addr = __PREG(MCDR), 279 .drcmr = &DRCMRRXMCDR, 280 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 281 DCMD_BURST16 | DCMD_WIDTH2, 282 }; 283 284 #ifdef CONFIG_PM 285 static int pxa2xx_ac97_suspend(struct platform_device *pdev, 286 struct snd_soc_dai *dai) 287 { 288 GCR |= GCR_ACLINK_OFF; 289 clk_disable(ac97_clk); 290 return 0; 291 } 292 293 static int pxa2xx_ac97_resume(struct platform_device *pdev, 294 struct snd_soc_dai *dai) 295 { 296 pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 297 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 298 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 299 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 300 #ifdef CONFIG_PXA27x 301 /* Use GPIO 113 as AC97 Reset on Bulverde */ 302 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 303 #endif 304 clk_enable(ac97_clk); 305 return 0; 306 } 307 308 #else 309 #define pxa2xx_ac97_suspend NULL 310 #define pxa2xx_ac97_resume NULL 311 #endif 312 313 static int pxa2xx_ac97_probe(struct platform_device *pdev, 314 struct snd_soc_dai *dai) 315 { 316 int ret; 317 318 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL); 319 if (ret < 0) 320 goto err; 321 322 pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 323 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 324 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 325 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 326 #ifdef CONFIG_PXA27x 327 /* Use GPIO 113 as AC97 Reset on Bulverde */ 328 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 329 330 ac97conf_clk = clk_get(&pdev->dev, "AC97CONFCLK"); 331 if (IS_ERR(ac97conf_clk)) { 332 ret = PTR_ERR(ac97conf_clk); 333 ac97conf_clk = NULL; 334 goto err_irq; 335 } 336 #endif 337 ac97_clk = clk_get(&pdev->dev, "AC97CLK"); 338 if (IS_ERR(ac97_clk)) { 339 ret = PTR_ERR(ac97_clk); 340 ac97_clk = NULL; 341 goto err_irq; 342 } 343 clk_enable(ac97_clk); 344 return 0; 345 346 err_irq: 347 GCR |= GCR_ACLINK_OFF; 348 #ifdef CONFIG_PXA27x 349 if (ac97conf_clk) { 350 clk_put(ac97conf_clk); 351 ac97conf_clk = NULL; 352 } 353 #endif 354 free_irq(IRQ_AC97, NULL); 355 err: 356 return ret; 357 } 358 359 static void pxa2xx_ac97_remove(struct platform_device *pdev, 360 struct snd_soc_dai *dai) 361 { 362 GCR |= GCR_ACLINK_OFF; 363 free_irq(IRQ_AC97, NULL); 364 #ifdef CONFIG_PXA27x 365 clk_put(ac97conf_clk); 366 ac97conf_clk = NULL; 367 #endif 368 clk_disable(ac97_clk); 369 clk_put(ac97_clk); 370 ac97_clk = NULL; 371 } 372 373 static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream, 374 struct snd_pcm_hw_params *params) 375 { 376 struct snd_soc_pcm_runtime *rtd = substream->private_data; 377 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; 378 379 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 380 cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_out; 381 else 382 cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_in; 383 384 return 0; 385 } 386 387 static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream, 388 struct snd_pcm_hw_params *params) 389 { 390 struct snd_soc_pcm_runtime *rtd = substream->private_data; 391 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; 392 393 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 394 cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_out; 395 else 396 cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_in; 397 398 return 0; 399 } 400 401 static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream, 402 struct snd_pcm_hw_params *params) 403 { 404 struct snd_soc_pcm_runtime *rtd = substream->private_data; 405 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; 406 407 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 408 return -ENODEV; 409 else 410 cpu_dai->dma_data = &pxa2xx_ac97_pcm_mic_mono_in; 411 412 return 0; 413 } 414 415 #define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 416 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 417 SNDRV_PCM_RATE_48000) 418 419 /* 420 * There is only 1 physical AC97 interface for pxa2xx, but it 421 * has extra fifo's that can be used for aux DACs and ADCs. 422 */ 423 struct snd_soc_dai pxa_ac97_dai[] = { 424 { 425 .name = "pxa2xx-ac97", 426 .id = 0, 427 .type = SND_SOC_DAI_AC97, 428 .probe = pxa2xx_ac97_probe, 429 .remove = pxa2xx_ac97_remove, 430 .suspend = pxa2xx_ac97_suspend, 431 .resume = pxa2xx_ac97_resume, 432 .playback = { 433 .stream_name = "AC97 Playback", 434 .channels_min = 2, 435 .channels_max = 2, 436 .rates = PXA2XX_AC97_RATES, 437 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 438 .capture = { 439 .stream_name = "AC97 Capture", 440 .channels_min = 2, 441 .channels_max = 2, 442 .rates = PXA2XX_AC97_RATES, 443 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 444 .ops = { 445 .hw_params = pxa2xx_ac97_hw_params,}, 446 }, 447 { 448 .name = "pxa2xx-ac97-aux", 449 .id = 1, 450 .type = SND_SOC_DAI_AC97, 451 .playback = { 452 .stream_name = "AC97 Aux Playback", 453 .channels_min = 1, 454 .channels_max = 1, 455 .rates = PXA2XX_AC97_RATES, 456 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 457 .capture = { 458 .stream_name = "AC97 Aux Capture", 459 .channels_min = 1, 460 .channels_max = 1, 461 .rates = PXA2XX_AC97_RATES, 462 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 463 .ops = { 464 .hw_params = pxa2xx_ac97_hw_aux_params,}, 465 }, 466 { 467 .name = "pxa2xx-ac97-mic", 468 .id = 2, 469 .type = SND_SOC_DAI_AC97, 470 .capture = { 471 .stream_name = "AC97 Mic Capture", 472 .channels_min = 1, 473 .channels_max = 1, 474 .rates = PXA2XX_AC97_RATES, 475 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 476 .ops = { 477 .hw_params = pxa2xx_ac97_hw_mic_params,}, 478 }, 479 }; 480 481 EXPORT_SYMBOL_GPL(pxa_ac97_dai); 482 EXPORT_SYMBOL_GPL(soc_ac97_ops); 483 484 MODULE_AUTHOR("Nicolas Pitre"); 485 MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip"); 486 MODULE_LICENSE("GPL"); 487