1 /* 2 * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip. 3 * 4 * Author: Nicolas Pitre 5 * Created: Dec 02, 2004 6 * Copyright: MontaVista Software Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/interrupt.h> 17 #include <linux/wait.h> 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/ac97_codec.h> 24 #include <sound/initval.h> 25 #include <sound/soc.h> 26 27 #include <asm/irq.h> 28 #include <linux/mutex.h> 29 #include <asm/hardware.h> 30 #include <asm/arch/pxa-regs.h> 31 #include <asm/arch/audio.h> 32 33 #include "pxa2xx-pcm.h" 34 #include "pxa2xx-ac97.h" 35 36 static DEFINE_MUTEX(car_mutex); 37 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); 38 static volatile long gsr_bits; 39 static struct clk *ac97_clk; 40 #ifdef CONFIG_PXA27x 41 static struct clk *ac97conf_clk; 42 #endif 43 44 /* 45 * Beware PXA27x bugs: 46 * 47 * o Slot 12 read from modem space will hang controller. 48 * o CDONE, SDONE interrupt fails after any slot 12 IO. 49 * 50 * We therefore have an hybrid approach for waiting on SDONE (interrupt or 51 * 1 jiffy timeout if interrupt never comes). 52 */ 53 54 static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, 55 unsigned short reg) 56 { 57 unsigned short val = -1; 58 volatile u32 *reg_addr; 59 60 mutex_lock(&car_mutex); 61 62 /* set up primary or secondary codec/modem space */ 63 #ifdef CONFIG_PXA27x 64 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 65 #else 66 if (reg == AC97_GPIO_STATUS) 67 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; 68 else 69 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 70 #endif 71 reg_addr += (reg >> 1); 72 73 #ifndef CONFIG_PXA27x 74 if (reg == AC97_GPIO_STATUS) { 75 /* read from controller cache */ 76 val = *reg_addr; 77 goto out; 78 } 79 #endif 80 81 /* start read access across the ac97 link */ 82 GSR = GSR_CDONE | GSR_SDONE; 83 gsr_bits = 0; 84 val = *reg_addr; 85 86 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); 87 if (!((GSR | gsr_bits) & GSR_SDONE)) { 88 printk(KERN_ERR "%s: read error (ac97_reg=%x GSR=%#lx)\n", 89 __FUNCTION__, reg, GSR | gsr_bits); 90 val = -1; 91 goto out; 92 } 93 94 /* valid data now */ 95 GSR = GSR_CDONE | GSR_SDONE; 96 gsr_bits = 0; 97 val = *reg_addr; 98 /* but we've just started another cycle... */ 99 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); 100 101 out: mutex_unlock(&car_mutex); 102 return val; 103 } 104 105 static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 106 unsigned short val) 107 { 108 volatile u32 *reg_addr; 109 110 mutex_lock(&car_mutex); 111 112 /* set up primary or secondary codec/modem space */ 113 #ifdef CONFIG_PXA27x 114 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 115 #else 116 if (reg == AC97_GPIO_STATUS) 117 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; 118 else 119 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 120 #endif 121 reg_addr += (reg >> 1); 122 123 GSR = GSR_CDONE | GSR_SDONE; 124 gsr_bits = 0; 125 *reg_addr = val; 126 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1); 127 if (!((GSR | gsr_bits) & GSR_CDONE)) 128 printk(KERN_ERR "%s: write error (ac97_reg=%x GSR=%#lx)\n", 129 __FUNCTION__, reg, GSR | gsr_bits); 130 131 mutex_unlock(&car_mutex); 132 } 133 134 static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97) 135 { 136 gsr_bits = 0; 137 138 #ifdef CONFIG_PXA27x 139 /* warm reset broken on Bulverde, 140 so manually keep AC97 reset high */ 141 pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 142 udelay(10); 143 GCR |= GCR_WARM_RST; 144 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 145 udelay(500); 146 #else 147 GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN; 148 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 149 #endif 150 151 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) 152 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", 153 __FUNCTION__, gsr_bits); 154 155 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 156 GCR |= GCR_SDONE_IE|GCR_CDONE_IE; 157 } 158 159 static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97) 160 { 161 GCR &= GCR_COLD_RST; /* clear everything but nCRST */ 162 GCR &= ~GCR_COLD_RST; /* then assert nCRST */ 163 164 gsr_bits = 0; 165 #ifdef CONFIG_PXA27x 166 /* PXA27x Developers Manual section 13.5.2.2.1 */ 167 clk_enable(ac97conf_clk); 168 udelay(5); 169 clk_disable(ac97conf_clk); 170 GCR = GCR_COLD_RST; 171 udelay(50); 172 #else 173 GCR = GCR_COLD_RST; 174 GCR |= GCR_CDONE_IE|GCR_SDONE_IE; 175 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 176 #endif 177 178 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) 179 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", 180 __FUNCTION__, gsr_bits); 181 182 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 183 GCR |= GCR_SDONE_IE|GCR_CDONE_IE; 184 } 185 186 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id) 187 { 188 long status; 189 190 status = GSR; 191 if (status) { 192 GSR = status; 193 gsr_bits |= status; 194 wake_up(&gsr_wq); 195 196 #ifdef CONFIG_PXA27x 197 /* Although we don't use those we still need to clear them 198 since they tend to spuriously trigger when MMC is used 199 (hardware bug? go figure)... */ 200 MISR = MISR_EOC; 201 PISR = PISR_EOC; 202 MCSR = MCSR_EOC; 203 #endif 204 205 return IRQ_HANDLED; 206 } 207 208 return IRQ_NONE; 209 } 210 211 struct snd_ac97_bus_ops soc_ac97_ops = { 212 .read = pxa2xx_ac97_read, 213 .write = pxa2xx_ac97_write, 214 .warm_reset = pxa2xx_ac97_warm_reset, 215 .reset = pxa2xx_ac97_cold_reset, 216 }; 217 218 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = { 219 .name = "AC97 PCM Stereo out", 220 .dev_addr = __PREG(PCDR), 221 .drcmr = &DRCMRTXPCDR, 222 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 223 DCMD_BURST32 | DCMD_WIDTH4, 224 }; 225 226 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = { 227 .name = "AC97 PCM Stereo in", 228 .dev_addr = __PREG(PCDR), 229 .drcmr = &DRCMRRXPCDR, 230 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 231 DCMD_BURST32 | DCMD_WIDTH4, 232 }; 233 234 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = { 235 .name = "AC97 Aux PCM (Slot 5) Mono out", 236 .dev_addr = __PREG(MODR), 237 .drcmr = &DRCMRTXMODR, 238 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 239 DCMD_BURST16 | DCMD_WIDTH2, 240 }; 241 242 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = { 243 .name = "AC97 Aux PCM (Slot 5) Mono in", 244 .dev_addr = __PREG(MODR), 245 .drcmr = &DRCMRRXMODR, 246 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 247 DCMD_BURST16 | DCMD_WIDTH2, 248 }; 249 250 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = { 251 .name = "AC97 Mic PCM (Slot 6) Mono in", 252 .dev_addr = __PREG(MCDR), 253 .drcmr = &DRCMRRXMCDR, 254 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 255 DCMD_BURST16 | DCMD_WIDTH2, 256 }; 257 258 #ifdef CONFIG_PM 259 static int pxa2xx_ac97_suspend(struct platform_device *pdev, 260 struct snd_soc_cpu_dai *dai) 261 { 262 GCR |= GCR_ACLINK_OFF; 263 clk_disable(ac97_clk); 264 return 0; 265 } 266 267 static int pxa2xx_ac97_resume(struct platform_device *pdev, 268 struct snd_soc_cpu_dai *dai) 269 { 270 pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 271 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 272 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 273 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 274 #ifdef CONFIG_PXA27x 275 /* Use GPIO 113 as AC97 Reset on Bulverde */ 276 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 277 #endif 278 clk_enable(ac97_clk); 279 return 0; 280 } 281 282 #else 283 #define pxa2xx_ac97_suspend NULL 284 #define pxa2xx_ac97_resume NULL 285 #endif 286 287 static int pxa2xx_ac97_probe(struct platform_device *pdev) 288 { 289 int ret; 290 291 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL); 292 if (ret < 0) 293 goto err; 294 295 pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 296 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 297 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 298 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 299 #ifdef CONFIG_PXA27x 300 /* Use GPIO 113 as AC97 Reset on Bulverde */ 301 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 302 303 ac97conf_clk = clk_get(&pdev->dev, "AC97CONFCLK"); 304 if (IS_ERR(ac97conf_clk)) { 305 ret = PTR_ERR(ac97conf_clk); 306 ac97conf_clk = NULL; 307 goto err_irq; 308 } 309 #endif 310 ac97_clk = clk_get(&pdev->dev, "AC97CLK"); 311 if (IS_ERR(ac97_clk)) { 312 ret = PTR_ERR(ac97_clk); 313 ac97_clk = NULL; 314 goto err_irq; 315 } 316 return 0; 317 318 err_irq: 319 GCR |= GCR_ACLINK_OFF; 320 #ifdef CONFIG_PXA27x 321 if (ac97conf_clk) { 322 clk_put(ac97conf_clk); 323 ac97conf_clk = NULL; 324 } 325 #endif 326 free_irq(IRQ_AC97, NULL); 327 err: 328 return ret; 329 } 330 331 static void pxa2xx_ac97_remove(struct platform_device *pdev) 332 { 333 GCR |= GCR_ACLINK_OFF; 334 free_irq(IRQ_AC97, NULL); 335 #ifdef CONFIG_PXA27x 336 clk_put(ac97conf_clk); 337 ac97conf_clk = NULL; 338 #endif 339 clk_disable(ac97_clk); 340 clk_put(ac97_clk); 341 ac97_clk = NULL; 342 } 343 344 static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream, 345 struct snd_pcm_hw_params *params) 346 { 347 struct snd_soc_pcm_runtime *rtd = substream->private_data; 348 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; 349 350 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 351 cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_out; 352 else 353 cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_in; 354 355 return 0; 356 } 357 358 static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream, 359 struct snd_pcm_hw_params *params) 360 { 361 struct snd_soc_pcm_runtime *rtd = substream->private_data; 362 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; 363 364 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 365 cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_out; 366 else 367 cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_in; 368 369 return 0; 370 } 371 372 static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream, 373 struct snd_pcm_hw_params *params) 374 { 375 struct snd_soc_pcm_runtime *rtd = substream->private_data; 376 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; 377 378 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 379 return -ENODEV; 380 else 381 cpu_dai->dma_data = &pxa2xx_ac97_pcm_mic_mono_in; 382 383 return 0; 384 } 385 386 #define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 387 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 388 SNDRV_PCM_RATE_48000) 389 390 /* 391 * There is only 1 physical AC97 interface for pxa2xx, but it 392 * has extra fifo's that can be used for aux DACs and ADCs. 393 */ 394 struct snd_soc_cpu_dai pxa_ac97_dai[] = { 395 { 396 .name = "pxa2xx-ac97", 397 .id = 0, 398 .type = SND_SOC_DAI_AC97, 399 .probe = pxa2xx_ac97_probe, 400 .remove = pxa2xx_ac97_remove, 401 .suspend = pxa2xx_ac97_suspend, 402 .resume = pxa2xx_ac97_resume, 403 .playback = { 404 .stream_name = "AC97 Playback", 405 .channels_min = 2, 406 .channels_max = 2, 407 .rates = PXA2XX_AC97_RATES, 408 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 409 .capture = { 410 .stream_name = "AC97 Capture", 411 .channels_min = 2, 412 .channels_max = 2, 413 .rates = PXA2XX_AC97_RATES, 414 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 415 .ops = { 416 .hw_params = pxa2xx_ac97_hw_params,}, 417 }, 418 { 419 .name = "pxa2xx-ac97-aux", 420 .id = 1, 421 .type = SND_SOC_DAI_AC97, 422 .playback = { 423 .stream_name = "AC97 Aux Playback", 424 .channels_min = 1, 425 .channels_max = 1, 426 .rates = PXA2XX_AC97_RATES, 427 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 428 .capture = { 429 .stream_name = "AC97 Aux Capture", 430 .channels_min = 1, 431 .channels_max = 1, 432 .rates = PXA2XX_AC97_RATES, 433 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 434 .ops = { 435 .hw_params = pxa2xx_ac97_hw_aux_params,}, 436 }, 437 { 438 .name = "pxa2xx-ac97-mic", 439 .id = 2, 440 .type = SND_SOC_DAI_AC97, 441 .capture = { 442 .stream_name = "AC97 Mic Capture", 443 .channels_min = 1, 444 .channels_max = 1, 445 .rates = PXA2XX_AC97_RATES, 446 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 447 .ops = { 448 .hw_params = pxa2xx_ac97_hw_mic_params,}, 449 }, 450 }; 451 452 EXPORT_SYMBOL_GPL(pxa_ac97_dai); 453 EXPORT_SYMBOL_GPL(soc_ac97_ops); 454 455 MODULE_AUTHOR("Nicolas Pitre"); 456 MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip"); 457 MODULE_LICENSE("GPL"); 458