1 /* 2 * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip. 3 * 4 * Author: Nicolas Pitre 5 * Created: Dec 02, 2004 6 * Copyright: MontaVista Software Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/interrupt.h> 17 #include <linux/wait.h> 18 #include <linux/delay.h> 19 20 #include <sound/driver.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/ac97_codec.h> 24 #include <sound/initval.h> 25 #include <sound/soc.h> 26 27 #include <asm/irq.h> 28 #include <linux/mutex.h> 29 #include <asm/hardware.h> 30 #include <asm/arch/pxa-regs.h> 31 #include <asm/arch/audio.h> 32 33 #include "pxa2xx-pcm.h" 34 35 static DEFINE_MUTEX(car_mutex); 36 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); 37 static volatile long gsr_bits; 38 39 #define AC97_DIR \ 40 (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE) 41 42 #define AC97_RATES \ 43 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \ 44 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 45 46 /* may need to expand this */ 47 static struct snd_soc_dai_mode pxa2xx_ac97_modes[] = { 48 { 49 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE, 50 .pcmrate = AC97_RATES, 51 .pcmdir = AC97_DIR, 52 }, 53 }; 54 55 /* 56 * Beware PXA27x bugs: 57 * 58 * o Slot 12 read from modem space will hang controller. 59 * o CDONE, SDONE interrupt fails after any slot 12 IO. 60 * 61 * We therefore have an hybrid approach for waiting on SDONE (interrupt or 62 * 1 jiffy timeout if interrupt never comes). 63 */ 64 65 static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, 66 unsigned short reg) 67 { 68 unsigned short val = -1; 69 volatile u32 *reg_addr; 70 71 mutex_lock(&car_mutex); 72 73 /* set up primary or secondary codec/modem space */ 74 #ifdef CONFIG_PXA27x 75 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 76 #else 77 if (reg == AC97_GPIO_STATUS) 78 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; 79 else 80 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 81 #endif 82 reg_addr += (reg >> 1); 83 84 #ifndef CONFIG_PXA27x 85 if (reg == AC97_GPIO_STATUS) { 86 /* read from controller cache */ 87 val = *reg_addr; 88 goto out; 89 } 90 #endif 91 92 /* start read access across the ac97 link */ 93 GSR = GSR_CDONE | GSR_SDONE; 94 gsr_bits = 0; 95 val = *reg_addr; 96 97 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); 98 if (!((GSR | gsr_bits) & GSR_SDONE)) { 99 printk(KERN_ERR "%s: read error (ac97_reg=%x GSR=%#lx)\n", 100 __FUNCTION__, reg, GSR | gsr_bits); 101 val = -1; 102 goto out; 103 } 104 105 /* valid data now */ 106 GSR = GSR_CDONE | GSR_SDONE; 107 gsr_bits = 0; 108 val = *reg_addr; 109 /* but we've just started another cycle... */ 110 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); 111 112 out: mutex_unlock(&car_mutex); 113 return val; 114 } 115 116 static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 117 unsigned short val) 118 { 119 volatile u32 *reg_addr; 120 121 mutex_lock(&car_mutex); 122 123 /* set up primary or secondary codec/modem space */ 124 #ifdef CONFIG_PXA27x 125 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 126 #else 127 if (reg == AC97_GPIO_STATUS) 128 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; 129 else 130 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 131 #endif 132 reg_addr += (reg >> 1); 133 134 GSR = GSR_CDONE | GSR_SDONE; 135 gsr_bits = 0; 136 *reg_addr = val; 137 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1); 138 if (!((GSR | gsr_bits) & GSR_CDONE)) 139 printk(KERN_ERR "%s: write error (ac97_reg=%x GSR=%#lx)\n", 140 __FUNCTION__, reg, GSR | gsr_bits); 141 142 mutex_unlock(&car_mutex); 143 } 144 145 static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97) 146 { 147 gsr_bits = 0; 148 149 #ifdef CONFIG_PXA27x 150 /* warm reset broken on Bulverde, 151 so manually keep AC97 reset high */ 152 pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 153 udelay(10); 154 GCR |= GCR_WARM_RST; 155 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 156 udelay(500); 157 #else 158 GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN; 159 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 160 #endif 161 162 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) 163 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", 164 __FUNCTION__, gsr_bits); 165 166 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 167 GCR |= GCR_SDONE_IE|GCR_CDONE_IE; 168 } 169 170 static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97) 171 { 172 GCR &= GCR_COLD_RST; /* clear everything but nCRST */ 173 GCR &= ~GCR_COLD_RST; /* then assert nCRST */ 174 175 gsr_bits = 0; 176 #ifdef CONFIG_PXA27x 177 /* PXA27x Developers Manual section 13.5.2.2.1 */ 178 pxa_set_cken(1 << 31, 1); 179 udelay(5); 180 pxa_set_cken(1 << 31, 0); 181 GCR = GCR_COLD_RST; 182 udelay(50); 183 #else 184 GCR = GCR_COLD_RST; 185 GCR |= GCR_CDONE_IE|GCR_SDONE_IE; 186 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 187 #endif 188 189 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) 190 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", 191 __FUNCTION__, gsr_bits); 192 193 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 194 GCR |= GCR_SDONE_IE|GCR_CDONE_IE; 195 } 196 197 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id) 198 { 199 long status; 200 201 status = GSR; 202 if (status) { 203 GSR = status; 204 gsr_bits |= status; 205 wake_up(&gsr_wq); 206 207 #ifdef CONFIG_PXA27x 208 /* Although we don't use those we still need to clear them 209 since they tend to spuriously trigger when MMC is used 210 (hardware bug? go figure)... */ 211 MISR = MISR_EOC; 212 PISR = PISR_EOC; 213 MCSR = MCSR_EOC; 214 #endif 215 216 return IRQ_HANDLED; 217 } 218 219 return IRQ_NONE; 220 } 221 222 struct snd_ac97_bus_ops soc_ac97_ops = { 223 .read = pxa2xx_ac97_read, 224 .write = pxa2xx_ac97_write, 225 .warm_reset = pxa2xx_ac97_warm_reset, 226 .reset = pxa2xx_ac97_cold_reset, 227 }; 228 229 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = { 230 .name = "AC97 PCM Stereo out", 231 .dev_addr = __PREG(PCDR), 232 .drcmr = &DRCMRTXPCDR, 233 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 234 DCMD_BURST32 | DCMD_WIDTH4, 235 }; 236 237 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = { 238 .name = "AC97 PCM Stereo in", 239 .dev_addr = __PREG(PCDR), 240 .drcmr = &DRCMRRXPCDR, 241 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 242 DCMD_BURST32 | DCMD_WIDTH4, 243 }; 244 245 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = { 246 .name = "AC97 Aux PCM (Slot 5) Mono out", 247 .dev_addr = __PREG(MODR), 248 .drcmr = &DRCMRTXMODR, 249 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 250 DCMD_BURST16 | DCMD_WIDTH2, 251 }; 252 253 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = { 254 .name = "AC97 Aux PCM (Slot 5) Mono in", 255 .dev_addr = __PREG(MODR), 256 .drcmr = &DRCMRRXMODR, 257 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 258 DCMD_BURST16 | DCMD_WIDTH2, 259 }; 260 261 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = { 262 .name = "AC97 Mic PCM (Slot 6) Mono in", 263 .dev_addr = __PREG(MCDR), 264 .drcmr = &DRCMRRXMCDR, 265 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 266 DCMD_BURST16 | DCMD_WIDTH2, 267 }; 268 269 #ifdef CONFIG_PM 270 static int pxa2xx_ac97_suspend(struct platform_device *pdev, 271 struct snd_soc_cpu_dai *dai) 272 { 273 GCR |= GCR_ACLINK_OFF; 274 pxa_set_cken(CKEN2_AC97, 0); 275 return 0; 276 } 277 278 static int pxa2xx_ac97_resume(struct platform_device *pdev, 279 struct snd_soc_cpu_dai *dai) 280 { 281 pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 282 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 283 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 284 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 285 #ifdef CONFIG_PXA27x 286 /* Use GPIO 113 as AC97 Reset on Bulverde */ 287 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 288 #endif 289 pxa_set_cken(CKEN2_AC97, 1); 290 return 0; 291 } 292 293 #else 294 #define pxa2xx_ac97_suspend NULL 295 #define pxa2xx_ac97_resume NULL 296 #endif 297 298 static int pxa2xx_ac97_probe(struct platform_device *pdev) 299 { 300 int ret; 301 302 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL); 303 if (ret < 0) 304 goto err; 305 306 pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 307 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 308 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 309 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 310 #ifdef CONFIG_PXA27x 311 /* Use GPIO 113 as AC97 Reset on Bulverde */ 312 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 313 #endif 314 pxa_set_cken(CKEN2_AC97, 1); 315 return 0; 316 317 err: 318 if (CKEN & CKEN2_AC97) { 319 GCR |= GCR_ACLINK_OFF; 320 free_irq(IRQ_AC97, NULL); 321 pxa_set_cken(CKEN2_AC97, 0); 322 } 323 return ret; 324 } 325 326 static void pxa2xx_ac97_remove(struct platform_device *pdev) 327 { 328 GCR |= GCR_ACLINK_OFF; 329 free_irq(IRQ_AC97, NULL); 330 pxa_set_cken(CKEN2_AC97, 0); 331 } 332 333 static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream, 334 struct snd_pcm_hw_params *params) 335 { 336 struct snd_soc_pcm_runtime *rtd = substream->private_data; 337 338 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 339 rtd->cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_out; 340 else 341 rtd->cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_in; 342 343 return 0; 344 } 345 346 static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream, 347 struct snd_pcm_hw_params *params) 348 { 349 struct snd_soc_pcm_runtime *rtd = substream->private_data; 350 351 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 352 rtd->cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_out; 353 else 354 rtd->cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_in; 355 356 return 0; 357 } 358 359 static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream, 360 struct snd_pcm_hw_params *params) 361 { 362 struct snd_soc_pcm_runtime *rtd = substream->private_data; 363 364 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 365 return -ENODEV; 366 else 367 rtd->cpu_dai->dma_data = &pxa2xx_ac97_pcm_mic_mono_in; 368 369 return 0; 370 } 371 372 /* 373 * There is only 1 physical AC97 interface for pxa2xx, but it 374 * has extra fifo's that can be used for aux DACs and ADCs. 375 */ 376 struct snd_soc_cpu_dai pxa_ac97_dai[] = { 377 { 378 .name = "pxa2xx-ac97", 379 .id = 0, 380 .type = SND_SOC_DAI_AC97, 381 .probe = pxa2xx_ac97_probe, 382 .remove = pxa2xx_ac97_remove, 383 .suspend = pxa2xx_ac97_suspend, 384 .resume = pxa2xx_ac97_resume, 385 .playback = { 386 .stream_name = "AC97 Playback", 387 .channels_min = 2, 388 .channels_max = 2,}, 389 .capture = { 390 .stream_name = "AC97 Capture", 391 .channels_min = 2, 392 .channels_max = 2,}, 393 .ops = { 394 .hw_params = pxa2xx_ac97_hw_params,}, 395 .caps = { 396 .num_modes = ARRAY_SIZE(pxa2xx_ac97_modes), 397 .mode = pxa2xx_ac97_modes,}, 398 }, 399 { 400 .name = "pxa2xx-ac97-aux", 401 .id = 1, 402 .type = SND_SOC_DAI_AC97, 403 .playback = { 404 .stream_name = "AC97 Aux Playback", 405 .channels_min = 1, 406 .channels_max = 1,}, 407 .capture = { 408 .stream_name = "AC97 Aux Capture", 409 .channels_min = 1, 410 .channels_max = 1,}, 411 .ops = { 412 .hw_params = pxa2xx_ac97_hw_aux_params,}, 413 .caps = { 414 .num_modes = ARRAY_SIZE(pxa2xx_ac97_modes), 415 .mode = pxa2xx_ac97_modes,}, 416 }, 417 { 418 .name = "pxa2xx-ac97-mic", 419 .id = 2, 420 .type = SND_SOC_DAI_AC97, 421 .capture = { 422 .stream_name = "AC97 Mic Capture", 423 .channels_min = 1, 424 .channels_max = 1,}, 425 .ops = { 426 .hw_params = pxa2xx_ac97_hw_mic_params,}, 427 .caps = { 428 .num_modes = ARRAY_SIZE(pxa2xx_ac97_modes), 429 .mode = pxa2xx_ac97_modes,},}, 430 }; 431 432 EXPORT_SYMBOL_GPL(pxa_ac97_dai); 433 EXPORT_SYMBOL_GPL(soc_ac97_ops); 434 435 MODULE_AUTHOR("Nicolas Pitre"); 436 MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip"); 437 MODULE_LICENSE("GPL"); 438