1 /* 2 * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip. 3 * 4 * Author: Nicolas Pitre 5 * Created: Dec 02, 2004 6 * Copyright: MontaVista Software Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/interrupt.h> 17 #include <linux/wait.h> 18 #include <linux/delay.h> 19 20 #include <sound/core.h> 21 #include <sound/pcm.h> 22 #include <sound/ac97_codec.h> 23 #include <sound/initval.h> 24 #include <sound/soc.h> 25 26 #include <asm/irq.h> 27 #include <linux/mutex.h> 28 #include <asm/hardware.h> 29 #include <asm/arch/pxa-regs.h> 30 #include <asm/arch/audio.h> 31 32 #include "pxa2xx-pcm.h" 33 #include "pxa2xx-ac97.h" 34 35 static DEFINE_MUTEX(car_mutex); 36 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); 37 static volatile long gsr_bits; 38 39 /* 40 * Beware PXA27x bugs: 41 * 42 * o Slot 12 read from modem space will hang controller. 43 * o CDONE, SDONE interrupt fails after any slot 12 IO. 44 * 45 * We therefore have an hybrid approach for waiting on SDONE (interrupt or 46 * 1 jiffy timeout if interrupt never comes). 47 */ 48 49 static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, 50 unsigned short reg) 51 { 52 unsigned short val = -1; 53 volatile u32 *reg_addr; 54 55 mutex_lock(&car_mutex); 56 57 /* set up primary or secondary codec/modem space */ 58 #ifdef CONFIG_PXA27x 59 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 60 #else 61 if (reg == AC97_GPIO_STATUS) 62 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; 63 else 64 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 65 #endif 66 reg_addr += (reg >> 1); 67 68 #ifndef CONFIG_PXA27x 69 if (reg == AC97_GPIO_STATUS) { 70 /* read from controller cache */ 71 val = *reg_addr; 72 goto out; 73 } 74 #endif 75 76 /* start read access across the ac97 link */ 77 GSR = GSR_CDONE | GSR_SDONE; 78 gsr_bits = 0; 79 val = *reg_addr; 80 81 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); 82 if (!((GSR | gsr_bits) & GSR_SDONE)) { 83 printk(KERN_ERR "%s: read error (ac97_reg=%x GSR=%#lx)\n", 84 __FUNCTION__, reg, GSR | gsr_bits); 85 val = -1; 86 goto out; 87 } 88 89 /* valid data now */ 90 GSR = GSR_CDONE | GSR_SDONE; 91 gsr_bits = 0; 92 val = *reg_addr; 93 /* but we've just started another cycle... */ 94 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); 95 96 out: mutex_unlock(&car_mutex); 97 return val; 98 } 99 100 static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 101 unsigned short val) 102 { 103 volatile u32 *reg_addr; 104 105 mutex_lock(&car_mutex); 106 107 /* set up primary or secondary codec/modem space */ 108 #ifdef CONFIG_PXA27x 109 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 110 #else 111 if (reg == AC97_GPIO_STATUS) 112 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; 113 else 114 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; 115 #endif 116 reg_addr += (reg >> 1); 117 118 GSR = GSR_CDONE | GSR_SDONE; 119 gsr_bits = 0; 120 *reg_addr = val; 121 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1); 122 if (!((GSR | gsr_bits) & GSR_CDONE)) 123 printk(KERN_ERR "%s: write error (ac97_reg=%x GSR=%#lx)\n", 124 __FUNCTION__, reg, GSR | gsr_bits); 125 126 mutex_unlock(&car_mutex); 127 } 128 129 static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97) 130 { 131 gsr_bits = 0; 132 133 #ifdef CONFIG_PXA27x 134 /* warm reset broken on Bulverde, 135 so manually keep AC97 reset high */ 136 pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 137 udelay(10); 138 GCR |= GCR_WARM_RST; 139 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 140 udelay(500); 141 #else 142 GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN; 143 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 144 #endif 145 146 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) 147 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", 148 __FUNCTION__, gsr_bits); 149 150 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 151 GCR |= GCR_SDONE_IE|GCR_CDONE_IE; 152 } 153 154 static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97) 155 { 156 GCR &= GCR_COLD_RST; /* clear everything but nCRST */ 157 GCR &= ~GCR_COLD_RST; /* then assert nCRST */ 158 159 gsr_bits = 0; 160 #ifdef CONFIG_PXA27x 161 /* PXA27x Developers Manual section 13.5.2.2.1 */ 162 pxa_set_cken(CKEN_AC97CONF, 1); 163 udelay(5); 164 pxa_set_cken(CKEN_AC97CONF, 0); 165 GCR = GCR_COLD_RST; 166 udelay(50); 167 #else 168 GCR = GCR_COLD_RST; 169 GCR |= GCR_CDONE_IE|GCR_SDONE_IE; 170 wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); 171 #endif 172 173 if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) 174 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", 175 __FUNCTION__, gsr_bits); 176 177 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); 178 GCR |= GCR_SDONE_IE|GCR_CDONE_IE; 179 } 180 181 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id) 182 { 183 long status; 184 185 status = GSR; 186 if (status) { 187 GSR = status; 188 gsr_bits |= status; 189 wake_up(&gsr_wq); 190 191 #ifdef CONFIG_PXA27x 192 /* Although we don't use those we still need to clear them 193 since they tend to spuriously trigger when MMC is used 194 (hardware bug? go figure)... */ 195 MISR = MISR_EOC; 196 PISR = PISR_EOC; 197 MCSR = MCSR_EOC; 198 #endif 199 200 return IRQ_HANDLED; 201 } 202 203 return IRQ_NONE; 204 } 205 206 struct snd_ac97_bus_ops soc_ac97_ops = { 207 .read = pxa2xx_ac97_read, 208 .write = pxa2xx_ac97_write, 209 .warm_reset = pxa2xx_ac97_warm_reset, 210 .reset = pxa2xx_ac97_cold_reset, 211 }; 212 213 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = { 214 .name = "AC97 PCM Stereo out", 215 .dev_addr = __PREG(PCDR), 216 .drcmr = &DRCMRTXPCDR, 217 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 218 DCMD_BURST32 | DCMD_WIDTH4, 219 }; 220 221 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = { 222 .name = "AC97 PCM Stereo in", 223 .dev_addr = __PREG(PCDR), 224 .drcmr = &DRCMRRXPCDR, 225 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 226 DCMD_BURST32 | DCMD_WIDTH4, 227 }; 228 229 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = { 230 .name = "AC97 Aux PCM (Slot 5) Mono out", 231 .dev_addr = __PREG(MODR), 232 .drcmr = &DRCMRTXMODR, 233 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | 234 DCMD_BURST16 | DCMD_WIDTH2, 235 }; 236 237 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = { 238 .name = "AC97 Aux PCM (Slot 5) Mono in", 239 .dev_addr = __PREG(MODR), 240 .drcmr = &DRCMRRXMODR, 241 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 242 DCMD_BURST16 | DCMD_WIDTH2, 243 }; 244 245 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = { 246 .name = "AC97 Mic PCM (Slot 6) Mono in", 247 .dev_addr = __PREG(MCDR), 248 .drcmr = &DRCMRRXMCDR, 249 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | 250 DCMD_BURST16 | DCMD_WIDTH2, 251 }; 252 253 #ifdef CONFIG_PM 254 static int pxa2xx_ac97_suspend(struct platform_device *pdev, 255 struct snd_soc_cpu_dai *dai) 256 { 257 GCR |= GCR_ACLINK_OFF; 258 pxa_set_cken(CKEN_AC97, 0); 259 return 0; 260 } 261 262 static int pxa2xx_ac97_resume(struct platform_device *pdev, 263 struct snd_soc_cpu_dai *dai) 264 { 265 pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 266 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 267 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 268 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 269 #ifdef CONFIG_PXA27x 270 /* Use GPIO 113 as AC97 Reset on Bulverde */ 271 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 272 #endif 273 pxa_set_cken(CKEN_AC97, 1); 274 return 0; 275 } 276 277 #else 278 #define pxa2xx_ac97_suspend NULL 279 #define pxa2xx_ac97_resume NULL 280 #endif 281 282 static int pxa2xx_ac97_probe(struct platform_device *pdev) 283 { 284 int ret; 285 286 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL); 287 if (ret < 0) 288 goto err; 289 290 pxa_gpio_mode(GPIO31_SYNC_AC97_MD); 291 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); 292 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); 293 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); 294 #ifdef CONFIG_PXA27x 295 /* Use GPIO 113 as AC97 Reset on Bulverde */ 296 pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); 297 #endif 298 pxa_set_cken(CKEN_AC97, 1); 299 return 0; 300 301 err: 302 if (CKEN & (1 << CKEN_AC97)) { 303 GCR |= GCR_ACLINK_OFF; 304 free_irq(IRQ_AC97, NULL); 305 pxa_set_cken(CKEN_AC97, 0); 306 } 307 return ret; 308 } 309 310 static void pxa2xx_ac97_remove(struct platform_device *pdev) 311 { 312 GCR |= GCR_ACLINK_OFF; 313 free_irq(IRQ_AC97, NULL); 314 pxa_set_cken(CKEN_AC97, 0); 315 } 316 317 static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream, 318 struct snd_pcm_hw_params *params) 319 { 320 struct snd_soc_pcm_runtime *rtd = substream->private_data; 321 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; 322 323 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 324 cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_out; 325 else 326 cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_in; 327 328 return 0; 329 } 330 331 static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream, 332 struct snd_pcm_hw_params *params) 333 { 334 struct snd_soc_pcm_runtime *rtd = substream->private_data; 335 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; 336 337 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 338 cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_out; 339 else 340 cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_in; 341 342 return 0; 343 } 344 345 static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream, 346 struct snd_pcm_hw_params *params) 347 { 348 struct snd_soc_pcm_runtime *rtd = substream->private_data; 349 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; 350 351 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 352 return -ENODEV; 353 else 354 cpu_dai->dma_data = &pxa2xx_ac97_pcm_mic_mono_in; 355 356 return 0; 357 } 358 359 #define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 360 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 361 SNDRV_PCM_RATE_48000) 362 363 /* 364 * There is only 1 physical AC97 interface for pxa2xx, but it 365 * has extra fifo's that can be used for aux DACs and ADCs. 366 */ 367 struct snd_soc_cpu_dai pxa_ac97_dai[] = { 368 { 369 .name = "pxa2xx-ac97", 370 .id = 0, 371 .type = SND_SOC_DAI_AC97, 372 .probe = pxa2xx_ac97_probe, 373 .remove = pxa2xx_ac97_remove, 374 .suspend = pxa2xx_ac97_suspend, 375 .resume = pxa2xx_ac97_resume, 376 .playback = { 377 .stream_name = "AC97 Playback", 378 .channels_min = 2, 379 .channels_max = 2, 380 .rates = PXA2XX_AC97_RATES, 381 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 382 .capture = { 383 .stream_name = "AC97 Capture", 384 .channels_min = 2, 385 .channels_max = 2, 386 .rates = PXA2XX_AC97_RATES, 387 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 388 .ops = { 389 .hw_params = pxa2xx_ac97_hw_params,}, 390 }, 391 { 392 .name = "pxa2xx-ac97-aux", 393 .id = 1, 394 .type = SND_SOC_DAI_AC97, 395 .playback = { 396 .stream_name = "AC97 Aux Playback", 397 .channels_min = 1, 398 .channels_max = 1, 399 .rates = PXA2XX_AC97_RATES, 400 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 401 .capture = { 402 .stream_name = "AC97 Aux Capture", 403 .channels_min = 1, 404 .channels_max = 1, 405 .rates = PXA2XX_AC97_RATES, 406 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 407 .ops = { 408 .hw_params = pxa2xx_ac97_hw_aux_params,}, 409 }, 410 { 411 .name = "pxa2xx-ac97-mic", 412 .id = 2, 413 .type = SND_SOC_DAI_AC97, 414 .capture = { 415 .stream_name = "AC97 Mic Capture", 416 .channels_min = 1, 417 .channels_max = 1, 418 .rates = PXA2XX_AC97_RATES, 419 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 420 .ops = { 421 .hw_params = pxa2xx_ac97_hw_mic_params,}, 422 }, 423 }; 424 425 EXPORT_SYMBOL_GPL(pxa_ac97_dai); 426 EXPORT_SYMBOL_GPL(soc_ac97_ops); 427 428 MODULE_AUTHOR("Nicolas Pitre"); 429 MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip"); 430 MODULE_LICENSE("GPL"); 431