1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21b340bd7SMark Brown /* 31b340bd7SMark Brown * ASoC PXA SSP port support 41b340bd7SMark Brown */ 51b340bd7SMark Brown 61b340bd7SMark Brown #ifndef _PXA_SSP_H 71b340bd7SMark Brown #define _PXA_SSP_H 81b340bd7SMark Brown 91b340bd7SMark Brown /* SSP clock sources */ 101b340bd7SMark Brown #define PXA_SSP_CLK_PLL 0 111b340bd7SMark Brown #define PXA_SSP_CLK_EXT 1 121b340bd7SMark Brown #define PXA_SSP_CLK_NET 2 131b340bd7SMark Brown #define PXA_SSP_CLK_AUDIO 3 141b340bd7SMark Brown #define PXA_SSP_CLK_NET_PLL 4 151b340bd7SMark Brown 161b340bd7SMark Brown /* SSP audio dividers */ 171b340bd7SMark Brown #define PXA_SSP_AUDIO_DIV_ACDS 0 181b340bd7SMark Brown #define PXA_SSP_AUDIO_DIV_SCDB 1 191b340bd7SMark Brown #define PXA_SSP_DIV_SCR 2 201b340bd7SMark Brown 211b340bd7SMark Brown /* SSP ACDS audio dividers values */ 221b340bd7SMark Brown #define PXA_SSP_CLK_AUDIO_DIV_1 0 231b340bd7SMark Brown #define PXA_SSP_CLK_AUDIO_DIV_2 1 241b340bd7SMark Brown #define PXA_SSP_CLK_AUDIO_DIV_4 2 251b340bd7SMark Brown #define PXA_SSP_CLK_AUDIO_DIV_8 3 261b340bd7SMark Brown #define PXA_SSP_CLK_AUDIO_DIV_16 4 271b340bd7SMark Brown #define PXA_SSP_CLK_AUDIO_DIV_32 5 281b340bd7SMark Brown 291b340bd7SMark Brown /* SSP divider bypass */ 301b340bd7SMark Brown #define PXA_SSP_CLK_SCDB_4 0 311b340bd7SMark Brown #define PXA_SSP_CLK_SCDB_1 1 321b340bd7SMark Brown #define PXA_SSP_CLK_SCDB_8 2 331b340bd7SMark Brown 341b340bd7SMark Brown #define PXA_SSP_PLL_OUT 0 351b340bd7SMark Brown 361b340bd7SMark Brown #endif 37