1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pxa-ssp.c -- ALSA Soc Audio Layer 4 * 5 * Copyright 2005,2008 Wolfson Microelectronics PLC. 6 * Author: Liam Girdwood 7 * Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * 9 * TODO: 10 * o Test network mode for > 16bit sample size 11 */ 12 13 #include <linux/init.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/platform_device.h> 17 #include <linux/clk.h> 18 #include <linux/io.h> 19 #include <linux/pxa2xx_ssp.h> 20 #include <linux/of.h> 21 #include <linux/dmaengine.h> 22 23 #include <asm/irq.h> 24 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/initval.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/pxa2xx-lib.h> 31 #include <sound/dmaengine_pcm.h> 32 33 #include "pxa-ssp.h" 34 35 /* 36 * SSP audio private data 37 */ 38 struct ssp_priv { 39 struct ssp_device *ssp; 40 struct clk *extclk; 41 unsigned long ssp_clk; 42 unsigned int sysclk; 43 unsigned int dai_fmt; 44 unsigned int configured_dai_fmt; 45 #ifdef CONFIG_PM 46 uint32_t cr0; 47 uint32_t cr1; 48 uint32_t to; 49 uint32_t psp; 50 #endif 51 }; 52 53 static void dump_registers(struct ssp_device *ssp) 54 { 55 dev_dbg(ssp->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", 56 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1), 57 pxa_ssp_read_reg(ssp, SSTO)); 58 59 dev_dbg(ssp->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", 60 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR), 61 pxa_ssp_read_reg(ssp, SSACD)); 62 } 63 64 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4, 65 int out, struct snd_dmaengine_dai_dma_data *dma) 66 { 67 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES : 68 DMA_SLAVE_BUSWIDTH_2_BYTES; 69 dma->maxburst = 16; 70 dma->addr = ssp->phys_base + SSDR; 71 } 72 73 static int pxa_ssp_startup(struct snd_pcm_substream *substream, 74 struct snd_soc_dai *cpu_dai) 75 { 76 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 77 struct ssp_device *ssp = priv->ssp; 78 struct snd_dmaengine_dai_dma_data *dma; 79 int ret = 0; 80 81 if (!snd_soc_dai_active(cpu_dai)) { 82 clk_prepare_enable(ssp->clk); 83 pxa_ssp_disable(ssp); 84 } 85 86 clk_prepare_enable(priv->extclk); 87 88 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL); 89 if (!dma) 90 return -ENOMEM; 91 dma->chan_name = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 92 "tx" : "rx"; 93 94 snd_soc_dai_set_dma_data(cpu_dai, substream, dma); 95 96 return ret; 97 } 98 99 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, 100 struct snd_soc_dai *cpu_dai) 101 { 102 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 103 struct ssp_device *ssp = priv->ssp; 104 105 if (!snd_soc_dai_active(cpu_dai)) { 106 pxa_ssp_disable(ssp); 107 clk_disable_unprepare(ssp->clk); 108 } 109 110 clk_disable_unprepare(priv->extclk); 111 112 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream)); 113 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL); 114 } 115 116 #ifdef CONFIG_PM 117 118 static int pxa_ssp_suspend(struct snd_soc_component *component) 119 { 120 struct ssp_priv *priv = snd_soc_component_get_drvdata(component); 121 struct ssp_device *ssp = priv->ssp; 122 123 if (!snd_soc_component_active(component)) 124 clk_prepare_enable(ssp->clk); 125 126 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0); 127 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1); 128 priv->to = __raw_readl(ssp->mmio_base + SSTO); 129 priv->psp = __raw_readl(ssp->mmio_base + SSPSP); 130 131 pxa_ssp_disable(ssp); 132 clk_disable_unprepare(ssp->clk); 133 return 0; 134 } 135 136 static int pxa_ssp_resume(struct snd_soc_component *component) 137 { 138 struct ssp_priv *priv = snd_soc_component_get_drvdata(component); 139 struct ssp_device *ssp = priv->ssp; 140 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE; 141 142 clk_prepare_enable(ssp->clk); 143 144 __raw_writel(sssr, ssp->mmio_base + SSSR); 145 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0); 146 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1); 147 __raw_writel(priv->to, ssp->mmio_base + SSTO); 148 __raw_writel(priv->psp, ssp->mmio_base + SSPSP); 149 150 if (snd_soc_component_active(component)) 151 pxa_ssp_enable(ssp); 152 else 153 clk_disable_unprepare(ssp->clk); 154 155 return 0; 156 } 157 158 #else 159 #define pxa_ssp_suspend NULL 160 #define pxa_ssp_resume NULL 161 #endif 162 163 /* 164 * ssp_set_clkdiv - set SSP clock divider 165 * @div: serial clock rate divider 166 */ 167 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div) 168 { 169 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); 170 171 if (ssp->type == PXA25x_SSP) { 172 sscr0 &= ~0x0000ff00; 173 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */ 174 } else { 175 sscr0 &= ~0x000fff00; 176 sscr0 |= (div - 1) << 8; /* 1..4096 */ 177 } 178 pxa_ssp_write_reg(ssp, SSCR0, sscr0); 179 } 180 181 /* 182 * Set the SSP ports SYSCLK. 183 */ 184 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 185 int clk_id, unsigned int freq, int dir) 186 { 187 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 188 struct ssp_device *ssp = priv->ssp; 189 190 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & 191 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); 192 193 if (priv->extclk) { 194 int ret; 195 196 /* 197 * For DT based boards, if an extclk is given, use it 198 * here and configure PXA_SSP_CLK_EXT. 199 */ 200 201 ret = clk_set_rate(priv->extclk, freq); 202 if (ret < 0) 203 return ret; 204 205 clk_id = PXA_SSP_CLK_EXT; 206 } 207 208 dev_dbg(ssp->dev, 209 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n", 210 cpu_dai->id, clk_id, freq); 211 212 switch (clk_id) { 213 case PXA_SSP_CLK_NET_PLL: 214 sscr0 |= SSCR0_MOD; 215 break; 216 case PXA_SSP_CLK_PLL: 217 /* Internal PLL is fixed */ 218 if (ssp->type == PXA25x_SSP) 219 priv->sysclk = 1843200; 220 else 221 priv->sysclk = 13000000; 222 break; 223 case PXA_SSP_CLK_EXT: 224 priv->sysclk = freq; 225 sscr0 |= SSCR0_ECS; 226 break; 227 case PXA_SSP_CLK_NET: 228 priv->sysclk = freq; 229 sscr0 |= SSCR0_NCS | SSCR0_MOD; 230 break; 231 case PXA_SSP_CLK_AUDIO: 232 priv->sysclk = 0; 233 pxa_ssp_set_scr(ssp, 1); 234 sscr0 |= SSCR0_ACS; 235 break; 236 default: 237 return -ENODEV; 238 } 239 240 /* The SSP clock must be disabled when changing SSP clock mode 241 * on PXA2xx. On PXA3xx it must be enabled when doing so. */ 242 if (ssp->type != PXA3xx_SSP) 243 clk_disable_unprepare(ssp->clk); 244 pxa_ssp_write_reg(ssp, SSCR0, sscr0); 245 if (ssp->type != PXA3xx_SSP) 246 clk_prepare_enable(ssp->clk); 247 248 return 0; 249 } 250 251 /* 252 * Configure the PLL frequency pxa27x and (afaik - pxa320 only) 253 */ 254 static int pxa_ssp_set_pll(struct ssp_priv *priv, unsigned int freq) 255 { 256 struct ssp_device *ssp = priv->ssp; 257 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70; 258 259 if (ssp->type == PXA3xx_SSP) 260 pxa_ssp_write_reg(ssp, SSACDD, 0); 261 262 switch (freq) { 263 case 5622000: 264 break; 265 case 11345000: 266 ssacd |= (0x1 << 4); 267 break; 268 case 12235000: 269 ssacd |= (0x2 << 4); 270 break; 271 case 14857000: 272 ssacd |= (0x3 << 4); 273 break; 274 case 32842000: 275 ssacd |= (0x4 << 4); 276 break; 277 case 48000000: 278 ssacd |= (0x5 << 4); 279 break; 280 case 0: 281 /* Disable */ 282 break; 283 284 default: 285 /* PXA3xx has a clock ditherer which can be used to generate 286 * a wider range of frequencies - calculate a value for it. 287 */ 288 if (ssp->type == PXA3xx_SSP) { 289 u32 val; 290 u64 tmp = 19968; 291 292 tmp *= 1000000; 293 do_div(tmp, freq); 294 val = tmp; 295 296 val = (val << 16) | 64; 297 pxa_ssp_write_reg(ssp, SSACDD, val); 298 299 ssacd |= (0x6 << 4); 300 301 dev_dbg(ssp->dev, 302 "Using SSACDD %x to supply %uHz\n", 303 val, freq); 304 break; 305 } 306 307 return -EINVAL; 308 } 309 310 pxa_ssp_write_reg(ssp, SSACD, ssacd); 311 312 return 0; 313 } 314 315 /* 316 * Set the active slots in TDM/Network mode 317 */ 318 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, 319 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 320 { 321 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 322 struct ssp_device *ssp = priv->ssp; 323 u32 sscr0; 324 325 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); 326 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS); 327 328 /* set slot width */ 329 if (slot_width > 16) 330 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16); 331 else 332 sscr0 |= SSCR0_DataSize(slot_width); 333 334 if (slots > 1) { 335 /* enable network mode */ 336 sscr0 |= SSCR0_MOD; 337 338 /* set number of active slots */ 339 sscr0 |= SSCR0_SlotsPerFrm(slots); 340 341 /* set active slot mask */ 342 pxa_ssp_write_reg(ssp, SSTSA, tx_mask); 343 pxa_ssp_write_reg(ssp, SSRSA, rx_mask); 344 } 345 pxa_ssp_write_reg(ssp, SSCR0, sscr0); 346 347 return 0; 348 } 349 350 /* 351 * Tristate the SSP DAI lines 352 */ 353 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, 354 int tristate) 355 { 356 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 357 struct ssp_device *ssp = priv->ssp; 358 u32 sscr1; 359 360 sscr1 = pxa_ssp_read_reg(ssp, SSCR1); 361 if (tristate) 362 sscr1 &= ~SSCR1_TTE; 363 else 364 sscr1 |= SSCR1_TTE; 365 pxa_ssp_write_reg(ssp, SSCR1, sscr1); 366 367 return 0; 368 } 369 370 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 371 unsigned int fmt) 372 { 373 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 374 375 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 376 case SND_SOC_DAIFMT_CBM_CFM: 377 case SND_SOC_DAIFMT_CBM_CFS: 378 case SND_SOC_DAIFMT_CBS_CFS: 379 break; 380 default: 381 return -EINVAL; 382 } 383 384 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 385 case SND_SOC_DAIFMT_NB_NF: 386 case SND_SOC_DAIFMT_NB_IF: 387 case SND_SOC_DAIFMT_IB_IF: 388 case SND_SOC_DAIFMT_IB_NF: 389 break; 390 default: 391 return -EINVAL; 392 } 393 394 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 395 case SND_SOC_DAIFMT_I2S: 396 case SND_SOC_DAIFMT_DSP_A: 397 case SND_SOC_DAIFMT_DSP_B: 398 break; 399 400 default: 401 return -EINVAL; 402 } 403 404 /* Settings will be applied in hw_params() */ 405 priv->dai_fmt = fmt; 406 407 return 0; 408 } 409 410 /* 411 * Set up the SSP DAI format. 412 * The SSP Port must be inactive before calling this function as the 413 * physical interface format is changed. 414 */ 415 static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv) 416 { 417 struct ssp_device *ssp = priv->ssp; 418 u32 sscr0, sscr1, sspsp, scfr; 419 420 /* check if we need to change anything at all */ 421 if (priv->configured_dai_fmt == priv->dai_fmt) 422 return 0; 423 424 /* reset port settings */ 425 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & 426 ~(SSCR0_PSP | SSCR0_MOD); 427 sscr1 = pxa_ssp_read_reg(ssp, SSCR1) & 428 ~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR | 429 SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT); 430 sspsp = pxa_ssp_read_reg(ssp, SSPSP) & 431 ~(SSPSP_SFRMP | SSPSP_SCMODE(3)); 432 433 sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7); 434 435 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) { 436 case SND_SOC_DAIFMT_CBM_CFM: 437 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR; 438 break; 439 case SND_SOC_DAIFMT_CBM_CFS: 440 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR; 441 break; 442 case SND_SOC_DAIFMT_CBS_CFS: 443 break; 444 default: 445 return -EINVAL; 446 } 447 448 switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) { 449 case SND_SOC_DAIFMT_NB_NF: 450 sspsp |= SSPSP_SFRMP; 451 break; 452 case SND_SOC_DAIFMT_NB_IF: 453 break; 454 case SND_SOC_DAIFMT_IB_IF: 455 sspsp |= SSPSP_SCMODE(2); 456 break; 457 case SND_SOC_DAIFMT_IB_NF: 458 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP; 459 break; 460 default: 461 return -EINVAL; 462 } 463 464 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 465 case SND_SOC_DAIFMT_I2S: 466 sscr0 |= SSCR0_PSP; 467 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL; 468 /* See hw_params() */ 469 break; 470 471 case SND_SOC_DAIFMT_DSP_A: 472 sspsp |= SSPSP_FSRT; 473 fallthrough; 474 case SND_SOC_DAIFMT_DSP_B: 475 sscr0 |= SSCR0_MOD | SSCR0_PSP; 476 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT; 477 break; 478 479 default: 480 return -EINVAL; 481 } 482 483 pxa_ssp_write_reg(ssp, SSCR0, sscr0); 484 pxa_ssp_write_reg(ssp, SSCR1, sscr1); 485 pxa_ssp_write_reg(ssp, SSPSP, sspsp); 486 487 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) { 488 case SND_SOC_DAIFMT_CBM_CFM: 489 case SND_SOC_DAIFMT_CBM_CFS: 490 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR; 491 pxa_ssp_write_reg(ssp, SSCR1, scfr); 492 493 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY) 494 cpu_relax(); 495 break; 496 } 497 498 dump_registers(ssp); 499 500 /* Since we are configuring the timings for the format by hand 501 * we have to defer some things until hw_params() where we 502 * know parameters like the sample size. 503 */ 504 priv->configured_dai_fmt = priv->dai_fmt; 505 506 return 0; 507 } 508 509 struct pxa_ssp_clock_mode { 510 int rate; 511 int pll; 512 u8 acds; 513 u8 scdb; 514 }; 515 516 static const struct pxa_ssp_clock_mode pxa_ssp_clock_modes[] = { 517 { .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X }, 518 { .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X }, 519 { .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X }, 520 { .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, 521 { .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, 522 { .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, 523 { .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X }, 524 {} 525 }; 526 527 /* 528 * Set the SSP audio DMA parameters and sample size. 529 * Can be called multiple times by oss emulation. 530 */ 531 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, 532 struct snd_pcm_hw_params *params, 533 struct snd_soc_dai *cpu_dai) 534 { 535 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 536 struct ssp_device *ssp = priv->ssp; 537 int chn = params_channels(params); 538 u32 sscr0, sspsp; 539 int width = snd_pcm_format_physical_width(params_format(params)); 540 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf; 541 struct snd_dmaengine_dai_dma_data *dma_data; 542 int rate = params_rate(params); 543 int bclk = rate * chn * (width / 8); 544 int ret; 545 546 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); 547 548 /* Network mode with one active slot (ttsa == 1) can be used 549 * to force 16-bit frame width on the wire (for S16_LE), even 550 * with two channels. Use 16-bit DMA transfers for this case. 551 */ 552 pxa_ssp_set_dma_params(ssp, 553 ((chn == 2) && (ttsa != 1)) || (width == 32), 554 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data); 555 556 /* we can only change the settings if the port is not in use */ 557 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) 558 return 0; 559 560 ret = pxa_ssp_configure_dai_fmt(priv); 561 if (ret < 0) 562 return ret; 563 564 /* clear selected SSP bits */ 565 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); 566 567 /* bit size */ 568 switch (params_format(params)) { 569 case SNDRV_PCM_FORMAT_S16_LE: 570 if (ssp->type == PXA3xx_SSP) 571 sscr0 |= SSCR0_FPCKE; 572 sscr0 |= SSCR0_DataSize(16); 573 break; 574 case SNDRV_PCM_FORMAT_S24_LE: 575 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8)); 576 break; 577 case SNDRV_PCM_FORMAT_S32_LE: 578 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); 579 break; 580 } 581 pxa_ssp_write_reg(ssp, SSCR0, sscr0); 582 583 if (sscr0 & SSCR0_ACS) { 584 ret = pxa_ssp_set_pll(priv, bclk); 585 586 /* 587 * If we were able to generate the bclk directly, 588 * all is fine. Otherwise, look up the closest rate 589 * from the table and also set the dividers. 590 */ 591 592 if (ret < 0) { 593 const struct pxa_ssp_clock_mode *m; 594 int ssacd, acds; 595 596 for (m = pxa_ssp_clock_modes; m->rate; m++) { 597 if (m->rate == rate) 598 break; 599 } 600 601 if (!m->rate) 602 return -EINVAL; 603 604 acds = m->acds; 605 606 /* The values in the table are for 16 bits */ 607 if (width == 32) 608 acds--; 609 610 ret = pxa_ssp_set_pll(priv, bclk); 611 if (ret < 0) 612 return ret; 613 614 ssacd = pxa_ssp_read_reg(ssp, SSACD); 615 ssacd &= ~(SSACD_ACDS(7) | SSACD_SCDB_1X); 616 ssacd |= SSACD_ACDS(m->acds); 617 ssacd |= m->scdb; 618 pxa_ssp_write_reg(ssp, SSACD, ssacd); 619 } 620 } else if (sscr0 & SSCR0_ECS) { 621 /* 622 * For setups with external clocking, the PLL and its diviers 623 * are not active. Instead, the SCR bits in SSCR0 can be used 624 * to divide the clock. 625 */ 626 pxa_ssp_set_scr(ssp, bclk / rate); 627 } 628 629 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 630 case SND_SOC_DAIFMT_I2S: 631 sspsp = pxa_ssp_read_reg(ssp, SSPSP); 632 633 if (((priv->sysclk / bclk) == 64) && (width == 16)) { 634 /* This is a special case where the bitclk is 64fs 635 * and we're not dealing with 2*32 bits of audio 636 * samples. 637 * 638 * The SSP values used for that are all found out by 639 * trying and failing a lot; some of the registers 640 * needed for that mode are only available on PXA3xx. 641 */ 642 if (ssp->type != PXA3xx_SSP) 643 return -EINVAL; 644 645 sspsp |= SSPSP_SFRMWDTH(width * 2); 646 sspsp |= SSPSP_SFRMDLY(width * 4); 647 sspsp |= SSPSP_EDMYSTOP(3); 648 sspsp |= SSPSP_DMYSTOP(3); 649 sspsp |= SSPSP_DMYSTRT(1); 650 } else { 651 /* The frame width is the width the LRCLK is 652 * asserted for; the delay is expressed in 653 * half cycle units. We need the extra cycle 654 * because the data starts clocking out one BCLK 655 * after LRCLK changes polarity. 656 */ 657 sspsp |= SSPSP_SFRMWDTH(width + 1); 658 sspsp |= SSPSP_SFRMDLY((width + 1) * 2); 659 sspsp |= SSPSP_DMYSTRT(1); 660 } 661 662 pxa_ssp_write_reg(ssp, SSPSP, sspsp); 663 break; 664 default: 665 break; 666 } 667 668 /* When we use a network mode, we always require TDM slots 669 * - complain loudly and fail if they've not been set up yet. 670 */ 671 if ((sscr0 & SSCR0_MOD) && !ttsa) { 672 dev_err(ssp->dev, "No TDM timeslot configured\n"); 673 return -EINVAL; 674 } 675 676 dump_registers(ssp); 677 678 return 0; 679 } 680 681 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream, 682 struct ssp_device *ssp, int value) 683 { 684 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0); 685 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1); 686 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP); 687 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR); 688 689 if (value && (sscr0 & SSCR0_SSE)) 690 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE); 691 692 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 693 if (value) 694 sscr1 |= SSCR1_TSRE; 695 else 696 sscr1 &= ~SSCR1_TSRE; 697 } else { 698 if (value) 699 sscr1 |= SSCR1_RSRE; 700 else 701 sscr1 &= ~SSCR1_RSRE; 702 } 703 704 pxa_ssp_write_reg(ssp, SSCR1, sscr1); 705 706 if (value) { 707 pxa_ssp_write_reg(ssp, SSSR, sssr); 708 pxa_ssp_write_reg(ssp, SSPSP, sspsp); 709 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE); 710 } 711 } 712 713 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, 714 struct snd_soc_dai *cpu_dai) 715 { 716 int ret = 0; 717 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 718 struct ssp_device *ssp = priv->ssp; 719 int val; 720 721 switch (cmd) { 722 case SNDRV_PCM_TRIGGER_RESUME: 723 pxa_ssp_enable(ssp); 724 break; 725 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 726 pxa_ssp_set_running_bit(substream, ssp, 1); 727 val = pxa_ssp_read_reg(ssp, SSSR); 728 pxa_ssp_write_reg(ssp, SSSR, val); 729 break; 730 case SNDRV_PCM_TRIGGER_START: 731 pxa_ssp_set_running_bit(substream, ssp, 1); 732 break; 733 case SNDRV_PCM_TRIGGER_STOP: 734 pxa_ssp_set_running_bit(substream, ssp, 0); 735 break; 736 case SNDRV_PCM_TRIGGER_SUSPEND: 737 pxa_ssp_disable(ssp); 738 break; 739 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 740 pxa_ssp_set_running_bit(substream, ssp, 0); 741 break; 742 743 default: 744 ret = -EINVAL; 745 } 746 747 dump_registers(ssp); 748 749 return ret; 750 } 751 752 static int pxa_ssp_probe(struct snd_soc_dai *dai) 753 { 754 struct device *dev = dai->dev; 755 struct ssp_priv *priv; 756 int ret; 757 758 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL); 759 if (!priv) 760 return -ENOMEM; 761 762 if (dev->of_node) { 763 struct device_node *ssp_handle; 764 765 ssp_handle = of_parse_phandle(dev->of_node, "port", 0); 766 if (!ssp_handle) { 767 dev_err(dev, "unable to get 'port' phandle\n"); 768 ret = -ENODEV; 769 goto err_priv; 770 } 771 772 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio"); 773 if (priv->ssp == NULL) { 774 ret = -ENODEV; 775 goto err_priv; 776 } 777 778 priv->extclk = devm_clk_get(dev, "extclk"); 779 if (IS_ERR(priv->extclk)) { 780 ret = PTR_ERR(priv->extclk); 781 if (ret == -EPROBE_DEFER) 782 return ret; 783 784 priv->extclk = NULL; 785 } 786 } else { 787 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio"); 788 if (priv->ssp == NULL) { 789 ret = -ENODEV; 790 goto err_priv; 791 } 792 } 793 794 priv->dai_fmt = (unsigned int) -1; 795 snd_soc_dai_set_drvdata(dai, priv); 796 797 return 0; 798 799 err_priv: 800 kfree(priv); 801 return ret; 802 } 803 804 static int pxa_ssp_remove(struct snd_soc_dai *dai) 805 { 806 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai); 807 808 pxa_ssp_free(priv->ssp); 809 kfree(priv); 810 return 0; 811 } 812 813 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 814 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ 815 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 816 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ 817 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) 818 819 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 820 821 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = { 822 .startup = pxa_ssp_startup, 823 .shutdown = pxa_ssp_shutdown, 824 .trigger = pxa_ssp_trigger, 825 .hw_params = pxa_ssp_hw_params, 826 .set_sysclk = pxa_ssp_set_dai_sysclk, 827 .set_fmt = pxa_ssp_set_dai_fmt, 828 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, 829 .set_tristate = pxa_ssp_set_dai_tristate, 830 }; 831 832 static struct snd_soc_dai_driver pxa_ssp_dai = { 833 .probe = pxa_ssp_probe, 834 .remove = pxa_ssp_remove, 835 .playback = { 836 .channels_min = 1, 837 .channels_max = 8, 838 .rates = PXA_SSP_RATES, 839 .formats = PXA_SSP_FORMATS, 840 }, 841 .capture = { 842 .channels_min = 1, 843 .channels_max = 8, 844 .rates = PXA_SSP_RATES, 845 .formats = PXA_SSP_FORMATS, 846 }, 847 .ops = &pxa_ssp_dai_ops, 848 }; 849 850 static const struct snd_soc_component_driver pxa_ssp_component = { 851 .name = "pxa-ssp", 852 .pcm_construct = pxa2xx_soc_pcm_new, 853 .pcm_destruct = pxa2xx_soc_pcm_free, 854 .open = pxa2xx_soc_pcm_open, 855 .close = pxa2xx_soc_pcm_close, 856 .hw_params = pxa2xx_soc_pcm_hw_params, 857 .hw_free = pxa2xx_soc_pcm_hw_free, 858 .prepare = pxa2xx_soc_pcm_prepare, 859 .trigger = pxa2xx_soc_pcm_trigger, 860 .pointer = pxa2xx_soc_pcm_pointer, 861 .mmap = pxa2xx_soc_pcm_mmap, 862 .suspend = pxa_ssp_suspend, 863 .resume = pxa_ssp_resume, 864 }; 865 866 #ifdef CONFIG_OF 867 static const struct of_device_id pxa_ssp_of_ids[] = { 868 { .compatible = "mrvl,pxa-ssp-dai" }, 869 {} 870 }; 871 MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids); 872 #endif 873 874 static int asoc_ssp_probe(struct platform_device *pdev) 875 { 876 return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component, 877 &pxa_ssp_dai, 1); 878 } 879 880 static struct platform_driver asoc_ssp_driver = { 881 .driver = { 882 .name = "pxa-ssp-dai", 883 .of_match_table = of_match_ptr(pxa_ssp_of_ids), 884 }, 885 886 .probe = asoc_ssp_probe, 887 }; 888 889 module_platform_driver(asoc_ssp_driver); 890 891 /* Module information */ 892 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 893 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface"); 894 MODULE_LICENSE("GPL"); 895 MODULE_ALIAS("platform:pxa-ssp-dai"); 896