12a24f2ceSDong Aisheng /* 22a24f2ceSDong Aisheng * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 32a24f2ceSDong Aisheng * 42a24f2ceSDong Aisheng * This program is free software; you can redistribute it and/or modify 52a24f2ceSDong Aisheng * it under the terms of the GNU General Public License as published by 62a24f2ceSDong Aisheng * the Free Software Foundation; either version 2 of the License, or 72a24f2ceSDong Aisheng * (at your option) any later version. 82a24f2ceSDong Aisheng * 92a24f2ceSDong Aisheng * This program is distributed in the hope that it will be useful, 102a24f2ceSDong Aisheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 112a24f2ceSDong Aisheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122a24f2ceSDong Aisheng * GNU General Public License for more details. 132a24f2ceSDong Aisheng * 142a24f2ceSDong Aisheng * You should have received a copy of the GNU General Public License along 152a24f2ceSDong Aisheng * with this program; if not, write to the Free Software Foundation, Inc., 162a24f2ceSDong Aisheng * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 172a24f2ceSDong Aisheng */ 182a24f2ceSDong Aisheng 192a24f2ceSDong Aisheng 202a24f2ceSDong Aisheng #ifndef _MXS_SAIF_H 212a24f2ceSDong Aisheng #define _MXS_SAIF_H 222a24f2ceSDong Aisheng 232a24f2ceSDong Aisheng #define SAIF_CTRL 0x0 242a24f2ceSDong Aisheng #define SAIF_STAT 0x10 252a24f2ceSDong Aisheng #define SAIF_DATA 0x20 262a24f2ceSDong Aisheng #define SAIF_VERSION 0X30 272a24f2ceSDong Aisheng 282a24f2ceSDong Aisheng /* SAIF_CTRL */ 292a24f2ceSDong Aisheng #define BM_SAIF_CTRL_SFTRST 0x80000000 302a24f2ceSDong Aisheng #define BM_SAIF_CTRL_CLKGATE 0x40000000 312a24f2ceSDong Aisheng #define BP_SAIF_CTRL_BITCLK_MULT_RATE 27 322a24f2ceSDong Aisheng #define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000 332a24f2ceSDong Aisheng #define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \ 342a24f2ceSDong Aisheng (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE) 352a24f2ceSDong Aisheng #define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000 362a24f2ceSDong Aisheng #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000 372a24f2ceSDong Aisheng #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000 382a24f2ceSDong Aisheng #define BP_SAIF_CTRL_RSRVD2 21 392a24f2ceSDong Aisheng #define BM_SAIF_CTRL_RSRVD2 0x00E00000 402a24f2ceSDong Aisheng 412a24f2ceSDong Aisheng #define BP_SAIF_CTRL_DMAWAIT_COUNT 16 422a24f2ceSDong Aisheng #define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F0000 432a24f2ceSDong Aisheng #define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \ 442a24f2ceSDong Aisheng (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT) 452a24f2ceSDong Aisheng #define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14 462a24f2ceSDong Aisheng #define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000 472a24f2ceSDong Aisheng #define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \ 482a24f2ceSDong Aisheng (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT) 492a24f2ceSDong Aisheng #define BM_SAIF_CTRL_LRCLK_PULSE 0x00002000 502a24f2ceSDong Aisheng #define BM_SAIF_CTRL_BIT_ORDER 0x00001000 512a24f2ceSDong Aisheng #define BM_SAIF_CTRL_DELAY 0x00000800 522a24f2ceSDong Aisheng #define BM_SAIF_CTRL_JUSTIFY 0x00000400 532a24f2ceSDong Aisheng #define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200 542a24f2ceSDong Aisheng #define BM_SAIF_CTRL_BITCLK_EDGE 0x00000100 552a24f2ceSDong Aisheng #define BP_SAIF_CTRL_WORD_LENGTH 4 562a24f2ceSDong Aisheng #define BM_SAIF_CTRL_WORD_LENGTH 0x000000F0 572a24f2ceSDong Aisheng #define BF_SAIF_CTRL_WORD_LENGTH(v) \ 582a24f2ceSDong Aisheng (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH) 592a24f2ceSDong Aisheng #define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x00000008 602a24f2ceSDong Aisheng #define BM_SAIF_CTRL_SLAVE_MODE 0x00000004 612a24f2ceSDong Aisheng #define BM_SAIF_CTRL_READ_MODE 0x00000002 622a24f2ceSDong Aisheng #define BM_SAIF_CTRL_RUN 0x00000001 632a24f2ceSDong Aisheng 642a24f2ceSDong Aisheng /* SAIF_STAT */ 652a24f2ceSDong Aisheng #define BM_SAIF_STAT_PRESENT 0x80000000 662a24f2ceSDong Aisheng #define BP_SAIF_STAT_RSRVD2 17 672a24f2ceSDong Aisheng #define BM_SAIF_STAT_RSRVD2 0x7FFE0000 682a24f2ceSDong Aisheng #define BF_SAIF_STAT_RSRVD2(v) \ 692a24f2ceSDong Aisheng (((v) << 17) & BM_SAIF_STAT_RSRVD2) 702a24f2ceSDong Aisheng #define BM_SAIF_STAT_DMA_PREQ 0x00010000 712a24f2ceSDong Aisheng #define BP_SAIF_STAT_RSRVD1 7 722a24f2ceSDong Aisheng #define BM_SAIF_STAT_RSRVD1 0x0000FF80 732a24f2ceSDong Aisheng #define BF_SAIF_STAT_RSRVD1(v) \ 742a24f2ceSDong Aisheng (((v) << 7) & BM_SAIF_STAT_RSRVD1) 752a24f2ceSDong Aisheng 762a24f2ceSDong Aisheng #define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040 772a24f2ceSDong Aisheng #define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x00000020 782a24f2ceSDong Aisheng #define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x00000010 792a24f2ceSDong Aisheng #define BP_SAIF_STAT_RSRVD0 1 802a24f2ceSDong Aisheng #define BM_SAIF_STAT_RSRVD0 0x0000000E 812a24f2ceSDong Aisheng #define BF_SAIF_STAT_RSRVD0(v) \ 822a24f2ceSDong Aisheng (((v) << 1) & BM_SAIF_STAT_RSRVD0) 832a24f2ceSDong Aisheng #define BM_SAIF_STAT_BUSY 0x00000001 842a24f2ceSDong Aisheng 852a24f2ceSDong Aisheng /* SAFI_DATA */ 862a24f2ceSDong Aisheng #define BP_SAIF_DATA_PCM_RIGHT 16 872a24f2ceSDong Aisheng #define BM_SAIF_DATA_PCM_RIGHT 0xFFFF0000 882a24f2ceSDong Aisheng #define BF_SAIF_DATA_PCM_RIGHT(v) \ 892a24f2ceSDong Aisheng (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT) 902a24f2ceSDong Aisheng #define BP_SAIF_DATA_PCM_LEFT 0 912a24f2ceSDong Aisheng #define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF 922a24f2ceSDong Aisheng #define BF_SAIF_DATA_PCM_LEFT(v) \ 932a24f2ceSDong Aisheng (((v) << 0) & BM_SAIF_DATA_PCM_LEFT) 942a24f2ceSDong Aisheng 952a24f2ceSDong Aisheng /* SAIF_VERSION */ 962a24f2ceSDong Aisheng #define BP_SAIF_VERSION_MAJOR 24 972a24f2ceSDong Aisheng #define BM_SAIF_VERSION_MAJOR 0xFF000000 982a24f2ceSDong Aisheng #define BF_SAIF_VERSION_MAJOR(v) \ 992a24f2ceSDong Aisheng (((v) << 24) & BM_SAIF_VERSION_MAJOR) 1002a24f2ceSDong Aisheng #define BP_SAIF_VERSION_MINOR 16 1012a24f2ceSDong Aisheng #define BM_SAIF_VERSION_MINOR 0x00FF0000 1022a24f2ceSDong Aisheng #define BF_SAIF_VERSION_MINOR(v) \ 1032a24f2ceSDong Aisheng (((v) << 16) & BM_SAIF_VERSION_MINOR) 1042a24f2ceSDong Aisheng #define BP_SAIF_VERSION_STEP 0 1052a24f2ceSDong Aisheng #define BM_SAIF_VERSION_STEP 0x0000FFFF 1062a24f2ceSDong Aisheng #define BF_SAIF_VERSION_STEP(v) \ 1072a24f2ceSDong Aisheng (((v) << 0) & BM_SAIF_VERSION_STEP) 1082a24f2ceSDong Aisheng 1092a24f2ceSDong Aisheng #define MXS_SAIF_MCLK 0 1102a24f2ceSDong Aisheng 1112a24f2ceSDong Aisheng #include "mxs-pcm.h" 1122a24f2ceSDong Aisheng 1132a24f2ceSDong Aisheng struct mxs_saif { 1142a24f2ceSDong Aisheng struct device *dev; 1152a24f2ceSDong Aisheng struct clk *clk; 1162a24f2ceSDong Aisheng unsigned int mclk; 1172a24f2ceSDong Aisheng unsigned int mclk_in_use; 1182a24f2ceSDong Aisheng void __iomem *base; 1192a24f2ceSDong Aisheng int irq; 12076067540SDong Aisheng unsigned int id; 12176067540SDong Aisheng unsigned int master_id; 12276067540SDong Aisheng unsigned int cur_rate; 12376067540SDong Aisheng unsigned int ongoing; 1242a24f2ceSDong Aisheng 1252a24f2ceSDong Aisheng u32 fifo_underrun; 1262a24f2ceSDong Aisheng u32 fifo_overrun; 12788cf632aSMarkus Pargmann 12888cf632aSMarkus Pargmann enum { 12988cf632aSMarkus Pargmann MXS_SAIF_STATE_STOPPED, 13088cf632aSMarkus Pargmann MXS_SAIF_STATE_RUNNING, 13188cf632aSMarkus Pargmann } state; 1322a24f2ceSDong Aisheng }; 1332a24f2ceSDong Aisheng 1342a24f2ceSDong Aisheng extern int mxs_saif_put_mclk(unsigned int saif_id); 1352a24f2ceSDong Aisheng extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 1362a24f2ceSDong Aisheng unsigned int rate); 1372a24f2ceSDong Aisheng #endif 138