xref: /openbmc/linux/sound/soc/mxs/mxs-saif.c (revision f3a8b664)
1 /*
2  * Copyright 2011 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License along
15  * with this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17  */
18 
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/clk.h>
27 #include <linux/clk-provider.h>
28 #include <linux/delay.h>
29 #include <linux/time.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 
35 #include "mxs-saif.h"
36 
37 #define MXS_SET_ADDR	0x4
38 #define MXS_CLR_ADDR	0x8
39 
40 static struct mxs_saif *mxs_saif[2];
41 
42 /*
43  * SAIF is a little different with other normal SOC DAIs on clock using.
44  *
45  * For MXS, two SAIF modules are instantiated on-chip.
46  * Each SAIF has a set of clock pins and can be operating in master
47  * mode simultaneously if they are connected to different off-chip codecs.
48  * Also, one of the two SAIFs can master or drive the clock pins while the
49  * other SAIF, in slave mode, receives clocking from the master SAIF.
50  * This also means that both SAIFs must operate at the same sample rate.
51  *
52  * We abstract this as each saif has a master, the master could be
53  * itself or other saifs. In the generic saif driver, saif does not need
54  * to know the different clkmux. Saif only needs to know who is its master
55  * and operating its master to generate the proper clock rate for it.
56  * The master id is provided in mach-specific layer according to different
57  * clkmux setting.
58  */
59 
60 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
61 			int clk_id, unsigned int freq, int dir)
62 {
63 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
64 
65 	switch (clk_id) {
66 	case MXS_SAIF_MCLK:
67 		saif->mclk = freq;
68 		break;
69 	default:
70 		return -EINVAL;
71 	}
72 	return 0;
73 }
74 
75 /*
76  * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
77  * is provided by other SAIF, we provide a interface here to get its master
78  * from its master_id.
79  * Note that the master could be itself.
80  */
81 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
82 {
83 	return mxs_saif[saif->master_id];
84 }
85 
86 /*
87  * Set SAIF clock and MCLK
88  */
89 static int mxs_saif_set_clk(struct mxs_saif *saif,
90 				  unsigned int mclk,
91 				  unsigned int rate)
92 {
93 	u32 scr;
94 	int ret;
95 	struct mxs_saif *master_saif;
96 
97 	dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
98 
99 	/* Set master saif to generate proper clock */
100 	master_saif = mxs_saif_get_master(saif);
101 	if (!master_saif)
102 		return -EINVAL;
103 
104 	dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
105 
106 	/* Checking if can playback and capture simutaneously */
107 	if (master_saif->ongoing && rate != master_saif->cur_rate) {
108 		dev_err(saif->dev,
109 			"can not change clock, master saif%d(rate %d) is ongoing\n",
110 			master_saif->id, master_saif->cur_rate);
111 		return -EINVAL;
112 	}
113 
114 	scr = __raw_readl(master_saif->base + SAIF_CTRL);
115 	scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
116 	scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
117 
118 	/*
119 	 * Set SAIF clock
120 	 *
121 	 * The SAIF clock should be either 384*fs or 512*fs.
122 	 * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
123 	 *  For 32x mclk, set saif clk as 512*fs.
124 	 *  For 48x mclk, set saif clk as 384*fs.
125 	 *
126 	 * If MCLK is not used, we just set saif clk to 512*fs.
127 	 */
128 	clk_prepare_enable(master_saif->clk);
129 
130 	if (master_saif->mclk_in_use) {
131 		if (mclk % 32 == 0) {
132 			scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
133 			ret = clk_set_rate(master_saif->clk, 512 * rate);
134 		} else if (mclk % 48 == 0) {
135 			scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
136 			ret = clk_set_rate(master_saif->clk, 384 * rate);
137 		} else {
138 			/* SAIF MCLK should be either 32x or 48x */
139 			clk_disable_unprepare(master_saif->clk);
140 			return -EINVAL;
141 		}
142 	} else {
143 		ret = clk_set_rate(master_saif->clk, 512 * rate);
144 		scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
145 	}
146 
147 	clk_disable_unprepare(master_saif->clk);
148 
149 	if (ret)
150 		return ret;
151 
152 	master_saif->cur_rate = rate;
153 
154 	if (!master_saif->mclk_in_use) {
155 		__raw_writel(scr, master_saif->base + SAIF_CTRL);
156 		return 0;
157 	}
158 
159 	/*
160 	 * Program the over-sample rate for MCLK output
161 	 *
162 	 * The available MCLK range is 32x, 48x... 512x. The rate
163 	 * could be from 8kHz to 192kH.
164 	 */
165 	switch (mclk / rate) {
166 	case 32:
167 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
168 		break;
169 	case 64:
170 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
171 		break;
172 	case 128:
173 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
174 		break;
175 	case 256:
176 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
177 		break;
178 	case 512:
179 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
180 		break;
181 	case 48:
182 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
183 		break;
184 	case 96:
185 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
186 		break;
187 	case 192:
188 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
189 		break;
190 	case 384:
191 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
192 		break;
193 	default:
194 		return -EINVAL;
195 	}
196 
197 	__raw_writel(scr, master_saif->base + SAIF_CTRL);
198 
199 	return 0;
200 }
201 
202 /*
203  * Put and disable MCLK.
204  */
205 int mxs_saif_put_mclk(unsigned int saif_id)
206 {
207 	struct mxs_saif *saif = mxs_saif[saif_id];
208 	u32 stat;
209 
210 	if (!saif)
211 		return -EINVAL;
212 
213 	stat = __raw_readl(saif->base + SAIF_STAT);
214 	if (stat & BM_SAIF_STAT_BUSY) {
215 		dev_err(saif->dev, "error: busy\n");
216 		return -EBUSY;
217 	}
218 
219 	clk_disable_unprepare(saif->clk);
220 
221 	/* disable MCLK output */
222 	__raw_writel(BM_SAIF_CTRL_CLKGATE,
223 		saif->base + SAIF_CTRL + MXS_SET_ADDR);
224 	__raw_writel(BM_SAIF_CTRL_RUN,
225 		saif->base + SAIF_CTRL + MXS_CLR_ADDR);
226 
227 	saif->mclk_in_use = 0;
228 	return 0;
229 }
230 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk);
231 
232 /*
233  * Get MCLK and set clock rate, then enable it
234  *
235  * This interface is used for codecs who are using MCLK provided
236  * by saif.
237  */
238 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
239 					unsigned int rate)
240 {
241 	struct mxs_saif *saif = mxs_saif[saif_id];
242 	u32 stat;
243 	int ret;
244 	struct mxs_saif *master_saif;
245 
246 	if (!saif)
247 		return -EINVAL;
248 
249 	/* Clear Reset */
250 	__raw_writel(BM_SAIF_CTRL_SFTRST,
251 		saif->base + SAIF_CTRL + MXS_CLR_ADDR);
252 
253 	/* FIXME: need clear clk gate for register r/w */
254 	__raw_writel(BM_SAIF_CTRL_CLKGATE,
255 		saif->base + SAIF_CTRL + MXS_CLR_ADDR);
256 
257 	master_saif = mxs_saif_get_master(saif);
258 	if (saif != master_saif) {
259 		dev_err(saif->dev, "can not get mclk from a non-master saif\n");
260 		return -EINVAL;
261 	}
262 
263 	stat = __raw_readl(saif->base + SAIF_STAT);
264 	if (stat & BM_SAIF_STAT_BUSY) {
265 		dev_err(saif->dev, "error: busy\n");
266 		return -EBUSY;
267 	}
268 
269 	saif->mclk_in_use = 1;
270 	ret = mxs_saif_set_clk(saif, mclk, rate);
271 	if (ret)
272 		return ret;
273 
274 	ret = clk_prepare_enable(saif->clk);
275 	if (ret)
276 		return ret;
277 
278 	/* enable MCLK output */
279 	__raw_writel(BM_SAIF_CTRL_RUN,
280 		saif->base + SAIF_CTRL + MXS_SET_ADDR);
281 
282 	return 0;
283 }
284 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk);
285 
286 /*
287  * SAIF DAI format configuration.
288  * Should only be called when port is inactive.
289  */
290 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
291 {
292 	u32 scr, stat;
293 	u32 scr0;
294 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
295 
296 	stat = __raw_readl(saif->base + SAIF_STAT);
297 	if (stat & BM_SAIF_STAT_BUSY) {
298 		dev_err(cpu_dai->dev, "error: busy\n");
299 		return -EBUSY;
300 	}
301 
302 	scr0 = __raw_readl(saif->base + SAIF_CTRL);
303 	scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
304 		& ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
305 	scr = 0;
306 
307 	/* DAI mode */
308 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
309 	case SND_SOC_DAIFMT_I2S:
310 		/* data frame low 1clk before data */
311 		scr |= BM_SAIF_CTRL_DELAY;
312 		scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
313 		break;
314 	case SND_SOC_DAIFMT_LEFT_J:
315 		/* data frame high with data */
316 		scr &= ~BM_SAIF_CTRL_DELAY;
317 		scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
318 		scr &= ~BM_SAIF_CTRL_JUSTIFY;
319 		break;
320 	default:
321 		return -EINVAL;
322 	}
323 
324 	/* DAI clock inversion */
325 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
326 	case SND_SOC_DAIFMT_IB_IF:
327 		scr |= BM_SAIF_CTRL_BITCLK_EDGE;
328 		scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
329 		break;
330 	case SND_SOC_DAIFMT_IB_NF:
331 		scr |= BM_SAIF_CTRL_BITCLK_EDGE;
332 		scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
333 		break;
334 	case SND_SOC_DAIFMT_NB_IF:
335 		scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
336 		scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
337 		break;
338 	case SND_SOC_DAIFMT_NB_NF:
339 		scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
340 		scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
341 		break;
342 	}
343 
344 	/*
345 	 * Note: We simply just support master mode since SAIF TX can only
346 	 * work as master.
347 	 * Here the master is relative to codec side.
348 	 * Saif internally could be slave when working on EXTMASTER mode.
349 	 * We just hide this to machine driver.
350 	 */
351 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
352 	case SND_SOC_DAIFMT_CBS_CFS:
353 		if (saif->id == saif->master_id)
354 			scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
355 		else
356 			scr |= BM_SAIF_CTRL_SLAVE_MODE;
357 
358 		__raw_writel(scr | scr0, saif->base + SAIF_CTRL);
359 		break;
360 	default:
361 		return -EINVAL;
362 	}
363 
364 	return 0;
365 }
366 
367 static int mxs_saif_startup(struct snd_pcm_substream *substream,
368 			   struct snd_soc_dai *cpu_dai)
369 {
370 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
371 
372 	/* clear error status to 0 for each re-open */
373 	saif->fifo_underrun = 0;
374 	saif->fifo_overrun = 0;
375 
376 	/* Clear Reset for normal operations */
377 	__raw_writel(BM_SAIF_CTRL_SFTRST,
378 		saif->base + SAIF_CTRL + MXS_CLR_ADDR);
379 
380 	/* clear clock gate */
381 	__raw_writel(BM_SAIF_CTRL_CLKGATE,
382 		saif->base + SAIF_CTRL + MXS_CLR_ADDR);
383 
384 	clk_prepare(saif->clk);
385 
386 	return 0;
387 }
388 
389 static void mxs_saif_shutdown(struct snd_pcm_substream *substream,
390 			      struct snd_soc_dai *cpu_dai)
391 {
392 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
393 
394 	clk_unprepare(saif->clk);
395 }
396 
397 /*
398  * Should only be called when port is inactive.
399  * although can be called multiple times by upper layers.
400  */
401 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
402 			     struct snd_pcm_hw_params *params,
403 			     struct snd_soc_dai *cpu_dai)
404 {
405 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
406 	struct mxs_saif *master_saif;
407 	u32 scr, stat;
408 	int ret;
409 
410 	master_saif = mxs_saif_get_master(saif);
411 	if (!master_saif)
412 		return -EINVAL;
413 
414 	/* mclk should already be set */
415 	if (!saif->mclk && saif->mclk_in_use) {
416 		dev_err(cpu_dai->dev, "set mclk first\n");
417 		return -EINVAL;
418 	}
419 
420 	stat = __raw_readl(saif->base + SAIF_STAT);
421 	if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) {
422 		dev_err(cpu_dai->dev, "error: busy\n");
423 		return -EBUSY;
424 	}
425 
426 	/*
427 	 * Set saif clk based on sample rate.
428 	 * If mclk is used, we also set mclk, if not, saif->mclk is
429 	 * default 0, means not used.
430 	 */
431 	ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
432 	if (ret) {
433 		dev_err(cpu_dai->dev, "unable to get proper clk\n");
434 		return ret;
435 	}
436 
437 	if (saif != master_saif) {
438 		/*
439 		* Set an initial clock rate for the saif internal logic to work
440 		* properly. This is important when working in EXTMASTER mode
441 		* that uses the other saif's BITCLK&LRCLK but it still needs a
442 		* basic clock which should be fast enough for the internal
443 		* logic.
444 		*/
445 		clk_enable(saif->clk);
446 		ret = clk_set_rate(saif->clk, 24000000);
447 		clk_disable(saif->clk);
448 		if (ret)
449 			return ret;
450 
451 		clk_prepare(master_saif->clk);
452 	}
453 
454 	scr = __raw_readl(saif->base + SAIF_CTRL);
455 
456 	scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
457 	scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
458 	switch (params_format(params)) {
459 	case SNDRV_PCM_FORMAT_S16_LE:
460 		scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
461 		break;
462 	case SNDRV_PCM_FORMAT_S20_3LE:
463 		scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
464 		scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
465 		break;
466 	case SNDRV_PCM_FORMAT_S24_LE:
467 		scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
468 		scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
469 		break;
470 	default:
471 		return -EINVAL;
472 	}
473 
474 	/* Tx/Rx config */
475 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
476 		/* enable TX mode */
477 		scr &= ~BM_SAIF_CTRL_READ_MODE;
478 	} else {
479 		/* enable RX mode */
480 		scr |= BM_SAIF_CTRL_READ_MODE;
481 	}
482 
483 	__raw_writel(scr, saif->base + SAIF_CTRL);
484 	return 0;
485 }
486 
487 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
488 			   struct snd_soc_dai *cpu_dai)
489 {
490 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
491 
492 	/* enable FIFO error irqs */
493 	__raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
494 		saif->base + SAIF_CTRL + MXS_SET_ADDR);
495 
496 	return 0;
497 }
498 
499 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
500 				struct snd_soc_dai *cpu_dai)
501 {
502 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
503 	struct mxs_saif *master_saif;
504 	u32 delay;
505 	int ret;
506 
507 	master_saif = mxs_saif_get_master(saif);
508 	if (!master_saif)
509 		return -EINVAL;
510 
511 	switch (cmd) {
512 	case SNDRV_PCM_TRIGGER_START:
513 	case SNDRV_PCM_TRIGGER_RESUME:
514 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
515 		if (saif->state == MXS_SAIF_STATE_RUNNING)
516 			return 0;
517 
518 		dev_dbg(cpu_dai->dev, "start\n");
519 
520 		ret = clk_enable(master_saif->clk);
521 		if (ret) {
522 			dev_err(saif->dev, "Failed to enable master clock\n");
523 			return ret;
524 		}
525 
526 		/*
527 		 * If the saif's master is not itself, we also need to enable
528 		 * itself clk for its internal basic logic to work.
529 		 */
530 		if (saif != master_saif) {
531 			ret = clk_enable(saif->clk);
532 			if (ret) {
533 				dev_err(saif->dev, "Failed to enable master clock\n");
534 				clk_disable(master_saif->clk);
535 				return ret;
536 			}
537 
538 			__raw_writel(BM_SAIF_CTRL_RUN,
539 				saif->base + SAIF_CTRL + MXS_SET_ADDR);
540 		}
541 
542 		if (!master_saif->mclk_in_use)
543 			__raw_writel(BM_SAIF_CTRL_RUN,
544 				master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
545 
546 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
547 			/*
548 			 * write data to saif data register to trigger
549 			 * the transfer.
550 			 * For 24-bit format the 32-bit FIFO register stores
551 			 * only one channel, so we need to write twice.
552 			 * This is also safe for the other non 24-bit formats.
553 			 */
554 			__raw_writel(0, saif->base + SAIF_DATA);
555 			__raw_writel(0, saif->base + SAIF_DATA);
556 		} else {
557 			/*
558 			 * read data from saif data register to trigger
559 			 * the receive.
560 			 * For 24-bit format the 32-bit FIFO register stores
561 			 * only one channel, so we need to read twice.
562 			 * This is also safe for the other non 24-bit formats.
563 			 */
564 			__raw_readl(saif->base + SAIF_DATA);
565 			__raw_readl(saif->base + SAIF_DATA);
566 		}
567 
568 		master_saif->ongoing = 1;
569 		saif->state = MXS_SAIF_STATE_RUNNING;
570 
571 		dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
572 			__raw_readl(saif->base + SAIF_CTRL),
573 			__raw_readl(saif->base + SAIF_STAT));
574 
575 		dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
576 			__raw_readl(master_saif->base + SAIF_CTRL),
577 			__raw_readl(master_saif->base + SAIF_STAT));
578 		break;
579 	case SNDRV_PCM_TRIGGER_SUSPEND:
580 	case SNDRV_PCM_TRIGGER_STOP:
581 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
582 		if (saif->state == MXS_SAIF_STATE_STOPPED)
583 			return 0;
584 
585 		dev_dbg(cpu_dai->dev, "stop\n");
586 
587 		/* wait a while for the current sample to complete */
588 		delay = USEC_PER_SEC / master_saif->cur_rate;
589 
590 		if (!master_saif->mclk_in_use) {
591 			__raw_writel(BM_SAIF_CTRL_RUN,
592 				master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
593 			udelay(delay);
594 		}
595 		clk_disable(master_saif->clk);
596 
597 		if (saif != master_saif) {
598 			__raw_writel(BM_SAIF_CTRL_RUN,
599 				saif->base + SAIF_CTRL + MXS_CLR_ADDR);
600 			udelay(delay);
601 			clk_disable(saif->clk);
602 		}
603 
604 		master_saif->ongoing = 0;
605 		saif->state = MXS_SAIF_STATE_STOPPED;
606 
607 		break;
608 	default:
609 		return -EINVAL;
610 	}
611 
612 	return 0;
613 }
614 
615 #define MXS_SAIF_RATES		SNDRV_PCM_RATE_8000_192000
616 #define MXS_SAIF_FORMATS \
617 	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
618 	SNDRV_PCM_FMTBIT_S24_LE)
619 
620 static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
621 	.startup = mxs_saif_startup,
622 	.shutdown = mxs_saif_shutdown,
623 	.trigger = mxs_saif_trigger,
624 	.prepare = mxs_saif_prepare,
625 	.hw_params = mxs_saif_hw_params,
626 	.set_sysclk = mxs_saif_set_dai_sysclk,
627 	.set_fmt = mxs_saif_set_dai_fmt,
628 };
629 
630 static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
631 {
632 	struct mxs_saif *saif = dev_get_drvdata(dai->dev);
633 
634 	snd_soc_dai_set_drvdata(dai, saif);
635 
636 	return 0;
637 }
638 
639 static struct snd_soc_dai_driver mxs_saif_dai = {
640 	.name = "mxs-saif",
641 	.probe = mxs_saif_dai_probe,
642 	.playback = {
643 		.channels_min = 2,
644 		.channels_max = 2,
645 		.rates = MXS_SAIF_RATES,
646 		.formats = MXS_SAIF_FORMATS,
647 	},
648 	.capture = {
649 		.channels_min = 2,
650 		.channels_max = 2,
651 		.rates = MXS_SAIF_RATES,
652 		.formats = MXS_SAIF_FORMATS,
653 	},
654 	.ops = &mxs_saif_dai_ops,
655 };
656 
657 static const struct snd_soc_component_driver mxs_saif_component = {
658 	.name		= "mxs-saif",
659 };
660 
661 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
662 {
663 	struct mxs_saif *saif = dev_id;
664 	unsigned int stat;
665 
666 	stat = __raw_readl(saif->base + SAIF_STAT);
667 	if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
668 			BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
669 		return IRQ_NONE;
670 
671 	if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
672 		dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
673 		__raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
674 				saif->base + SAIF_STAT + MXS_CLR_ADDR);
675 	}
676 
677 	if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
678 		dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
679 		__raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
680 				saif->base + SAIF_STAT + MXS_CLR_ADDR);
681 	}
682 
683 	dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
684 	       __raw_readl(saif->base + SAIF_CTRL),
685 	       __raw_readl(saif->base + SAIF_STAT));
686 
687 	return IRQ_HANDLED;
688 }
689 
690 static int mxs_saif_mclk_init(struct platform_device *pdev)
691 {
692 	struct mxs_saif *saif = platform_get_drvdata(pdev);
693 	struct device_node *np = pdev->dev.of_node;
694 	struct clk *clk;
695 	int ret;
696 
697 	clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
698 				   __clk_get_name(saif->clk), 0,
699 				   saif->base + SAIF_CTRL,
700 				   BP_SAIF_CTRL_BITCLK_MULT_RATE, 3,
701 				   0, NULL);
702 	if (IS_ERR(clk)) {
703 		ret = PTR_ERR(clk);
704 		if (ret == -EEXIST)
705 			return 0;
706 		dev_err(&pdev->dev, "failed to register mclk: %d\n", ret);
707 		return PTR_ERR(clk);
708 	}
709 
710 	ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
711 	if (ret)
712 		return ret;
713 
714 	return 0;
715 }
716 
717 static int mxs_saif_probe(struct platform_device *pdev)
718 {
719 	struct device_node *np = pdev->dev.of_node;
720 	struct resource *iores;
721 	struct mxs_saif *saif;
722 	int irq, ret = 0;
723 	struct device_node *master;
724 
725 	if (!np)
726 		return -EINVAL;
727 
728 	saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
729 	if (!saif)
730 		return -ENOMEM;
731 
732 	ret = of_alias_get_id(np, "saif");
733 	if (ret < 0)
734 		return ret;
735 	else
736 		saif->id = ret;
737 
738 	/*
739 	 * If there is no "fsl,saif-master" phandle, it's a saif
740 	 * master.  Otherwise, it's a slave and its phandle points
741 	 * to the master.
742 	 */
743 	master = of_parse_phandle(np, "fsl,saif-master", 0);
744 	if (!master) {
745 		saif->master_id = saif->id;
746 	} else {
747 		ret = of_alias_get_id(master, "saif");
748 		if (ret < 0)
749 			return ret;
750 		else
751 			saif->master_id = ret;
752 	}
753 
754 	if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
755 		dev_err(&pdev->dev, "get wrong master id\n");
756 		return -EINVAL;
757 	}
758 
759 	mxs_saif[saif->id] = saif;
760 
761 	saif->clk = devm_clk_get(&pdev->dev, NULL);
762 	if (IS_ERR(saif->clk)) {
763 		ret = PTR_ERR(saif->clk);
764 		dev_err(&pdev->dev, "Cannot get the clock: %d\n",
765 			ret);
766 		return ret;
767 	}
768 
769 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
770 
771 	saif->base = devm_ioremap_resource(&pdev->dev, iores);
772 	if (IS_ERR(saif->base))
773 		return PTR_ERR(saif->base);
774 
775 	irq = platform_get_irq(pdev, 0);
776 	if (irq < 0) {
777 		ret = irq;
778 		dev_err(&pdev->dev, "failed to get irq resource: %d\n",
779 			ret);
780 		return ret;
781 	}
782 
783 	saif->dev = &pdev->dev;
784 	ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0,
785 			       dev_name(&pdev->dev), saif);
786 	if (ret) {
787 		dev_err(&pdev->dev, "failed to request irq\n");
788 		return ret;
789 	}
790 
791 	platform_set_drvdata(pdev, saif);
792 
793 	/* We only support saif0 being tx and clock master */
794 	if (saif->id == 0) {
795 		ret = mxs_saif_mclk_init(pdev);
796 		if (ret)
797 			dev_warn(&pdev->dev, "failed to init clocks\n");
798 	}
799 
800 	ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component,
801 					      &mxs_saif_dai, 1);
802 	if (ret) {
803 		dev_err(&pdev->dev, "register DAI failed\n");
804 		return ret;
805 	}
806 
807 	ret = mxs_pcm_platform_register(&pdev->dev);
808 	if (ret) {
809 		dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
810 		return ret;
811 	}
812 
813 	return 0;
814 }
815 
816 static const struct of_device_id mxs_saif_dt_ids[] = {
817 	{ .compatible = "fsl,imx28-saif", },
818 	{ /* sentinel */ }
819 };
820 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
821 
822 static struct platform_driver mxs_saif_driver = {
823 	.probe = mxs_saif_probe,
824 
825 	.driver = {
826 		.name = "mxs-saif",
827 		.of_match_table = mxs_saif_dt_ids,
828 	},
829 };
830 
831 module_platform_driver(mxs_saif_driver);
832 
833 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
834 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
835 MODULE_LICENSE("GPL");
836 MODULE_ALIAS("platform:mxs-saif");
837