1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/slab.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/clk.h> 27 #include <linux/clk-provider.h> 28 #include <linux/delay.h> 29 #include <linux/time.h> 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/soc.h> 34 35 #include "mxs-saif.h" 36 37 #define MXS_SET_ADDR 0x4 38 #define MXS_CLR_ADDR 0x8 39 40 static struct mxs_saif *mxs_saif[2]; 41 42 /* 43 * SAIF is a little different with other normal SOC DAIs on clock using. 44 * 45 * For MXS, two SAIF modules are instantiated on-chip. 46 * Each SAIF has a set of clock pins and can be operating in master 47 * mode simultaneously if they are connected to different off-chip codecs. 48 * Also, one of the two SAIFs can master or drive the clock pins while the 49 * other SAIF, in slave mode, receives clocking from the master SAIF. 50 * This also means that both SAIFs must operate at the same sample rate. 51 * 52 * We abstract this as each saif has a master, the master could be 53 * itself or other saifs. In the generic saif driver, saif does not need 54 * to know the different clkmux. Saif only needs to know who is its master 55 * and operating its master to generate the proper clock rate for it. 56 * The master id is provided in mach-specific layer according to different 57 * clkmux setting. 58 */ 59 60 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 61 int clk_id, unsigned int freq, int dir) 62 { 63 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 64 65 switch (clk_id) { 66 case MXS_SAIF_MCLK: 67 saif->mclk = freq; 68 break; 69 default: 70 return -EINVAL; 71 } 72 return 0; 73 } 74 75 /* 76 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 77 * is provided by other SAIF, we provide a interface here to get its master 78 * from its master_id. 79 * Note that the master could be itself. 80 */ 81 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 82 { 83 return mxs_saif[saif->master_id]; 84 } 85 86 /* 87 * Set SAIF clock and MCLK 88 */ 89 static int mxs_saif_set_clk(struct mxs_saif *saif, 90 unsigned int mclk, 91 unsigned int rate) 92 { 93 u32 scr; 94 int ret; 95 struct mxs_saif *master_saif; 96 97 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 98 99 /* Set master saif to generate proper clock */ 100 master_saif = mxs_saif_get_master(saif); 101 if (!master_saif) 102 return -EINVAL; 103 104 dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 105 106 /* Checking if can playback and capture simutaneously */ 107 if (master_saif->ongoing && rate != master_saif->cur_rate) { 108 dev_err(saif->dev, 109 "can not change clock, master saif%d(rate %d) is ongoing\n", 110 master_saif->id, master_saif->cur_rate); 111 return -EINVAL; 112 } 113 114 scr = __raw_readl(master_saif->base + SAIF_CTRL); 115 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 116 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 117 118 /* 119 * Set SAIF clock 120 * 121 * The SAIF clock should be either 384*fs or 512*fs. 122 * If MCLK is used, the SAIF clk ratio needs to match mclk ratio. 123 * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs. 124 * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs. 125 * 126 * If MCLK is not used, we just set saif clk to 512*fs. 127 */ 128 clk_prepare_enable(master_saif->clk); 129 130 if (master_saif->mclk_in_use) { 131 switch (mclk / rate) { 132 case 32: 133 case 64: 134 case 128: 135 case 256: 136 case 512: 137 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 138 ret = clk_set_rate(master_saif->clk, 512 * rate); 139 break; 140 case 48: 141 case 96: 142 case 192: 143 case 384: 144 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 145 ret = clk_set_rate(master_saif->clk, 384 * rate); 146 break; 147 default: 148 /* SAIF MCLK should be a sub-rate of 512x or 384x */ 149 clk_disable_unprepare(master_saif->clk); 150 return -EINVAL; 151 } 152 } else { 153 ret = clk_set_rate(master_saif->clk, 512 * rate); 154 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 155 } 156 157 clk_disable_unprepare(master_saif->clk); 158 159 if (ret) 160 return ret; 161 162 master_saif->cur_rate = rate; 163 164 if (!master_saif->mclk_in_use) { 165 __raw_writel(scr, master_saif->base + SAIF_CTRL); 166 return 0; 167 } 168 169 /* 170 * Program the over-sample rate for MCLK output 171 * 172 * The available MCLK range is 32x, 48x... 512x. The rate 173 * could be from 8kHz to 192kH. 174 */ 175 switch (mclk / rate) { 176 case 32: 177 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 178 break; 179 case 64: 180 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 181 break; 182 case 128: 183 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 184 break; 185 case 256: 186 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 187 break; 188 case 512: 189 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 190 break; 191 case 48: 192 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 193 break; 194 case 96: 195 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 196 break; 197 case 192: 198 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 199 break; 200 case 384: 201 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 202 break; 203 default: 204 return -EINVAL; 205 } 206 207 __raw_writel(scr, master_saif->base + SAIF_CTRL); 208 209 return 0; 210 } 211 212 /* 213 * Put and disable MCLK. 214 */ 215 int mxs_saif_put_mclk(unsigned int saif_id) 216 { 217 struct mxs_saif *saif = mxs_saif[saif_id]; 218 u32 stat; 219 220 if (!saif) 221 return -EINVAL; 222 223 stat = __raw_readl(saif->base + SAIF_STAT); 224 if (stat & BM_SAIF_STAT_BUSY) { 225 dev_err(saif->dev, "error: busy\n"); 226 return -EBUSY; 227 } 228 229 clk_disable_unprepare(saif->clk); 230 231 /* disable MCLK output */ 232 __raw_writel(BM_SAIF_CTRL_CLKGATE, 233 saif->base + SAIF_CTRL + MXS_SET_ADDR); 234 __raw_writel(BM_SAIF_CTRL_RUN, 235 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 236 237 saif->mclk_in_use = 0; 238 return 0; 239 } 240 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); 241 242 /* 243 * Get MCLK and set clock rate, then enable it 244 * 245 * This interface is used for codecs who are using MCLK provided 246 * by saif. 247 */ 248 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 249 unsigned int rate) 250 { 251 struct mxs_saif *saif = mxs_saif[saif_id]; 252 u32 stat; 253 int ret; 254 struct mxs_saif *master_saif; 255 256 if (!saif) 257 return -EINVAL; 258 259 /* Clear Reset */ 260 __raw_writel(BM_SAIF_CTRL_SFTRST, 261 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 262 263 /* FIXME: need clear clk gate for register r/w */ 264 __raw_writel(BM_SAIF_CTRL_CLKGATE, 265 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 266 267 master_saif = mxs_saif_get_master(saif); 268 if (saif != master_saif) { 269 dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 270 return -EINVAL; 271 } 272 273 stat = __raw_readl(saif->base + SAIF_STAT); 274 if (stat & BM_SAIF_STAT_BUSY) { 275 dev_err(saif->dev, "error: busy\n"); 276 return -EBUSY; 277 } 278 279 saif->mclk_in_use = 1; 280 ret = mxs_saif_set_clk(saif, mclk, rate); 281 if (ret) 282 return ret; 283 284 ret = clk_prepare_enable(saif->clk); 285 if (ret) 286 return ret; 287 288 /* enable MCLK output */ 289 __raw_writel(BM_SAIF_CTRL_RUN, 290 saif->base + SAIF_CTRL + MXS_SET_ADDR); 291 292 return 0; 293 } 294 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); 295 296 /* 297 * SAIF DAI format configuration. 298 * Should only be called when port is inactive. 299 */ 300 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 301 { 302 u32 scr, stat; 303 u32 scr0; 304 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 305 306 stat = __raw_readl(saif->base + SAIF_STAT); 307 if (stat & BM_SAIF_STAT_BUSY) { 308 dev_err(cpu_dai->dev, "error: busy\n"); 309 return -EBUSY; 310 } 311 312 /* If SAIF1 is configured as slave, the clk gate needs to be cleared 313 * before the register can be written. 314 */ 315 if (saif->id != saif->master_id) { 316 __raw_writel(BM_SAIF_CTRL_SFTRST, 317 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 318 __raw_writel(BM_SAIF_CTRL_CLKGATE, 319 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 320 } 321 322 scr0 = __raw_readl(saif->base + SAIF_CTRL); 323 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 324 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 325 scr = 0; 326 327 /* DAI mode */ 328 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 329 case SND_SOC_DAIFMT_I2S: 330 /* data frame low 1clk before data */ 331 scr |= BM_SAIF_CTRL_DELAY; 332 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 333 break; 334 case SND_SOC_DAIFMT_LEFT_J: 335 /* data frame high with data */ 336 scr &= ~BM_SAIF_CTRL_DELAY; 337 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 338 scr &= ~BM_SAIF_CTRL_JUSTIFY; 339 break; 340 default: 341 return -EINVAL; 342 } 343 344 /* DAI clock inversion */ 345 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 346 case SND_SOC_DAIFMT_IB_IF: 347 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 348 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 349 break; 350 case SND_SOC_DAIFMT_IB_NF: 351 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 352 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 353 break; 354 case SND_SOC_DAIFMT_NB_IF: 355 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 356 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 357 break; 358 case SND_SOC_DAIFMT_NB_NF: 359 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 360 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 361 break; 362 } 363 364 /* 365 * Note: We simply just support master mode since SAIF TX can only 366 * work as master. 367 * Here the master is relative to codec side. 368 * Saif internally could be slave when working on EXTMASTER mode. 369 * We just hide this to machine driver. 370 */ 371 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 372 case SND_SOC_DAIFMT_CBS_CFS: 373 if (saif->id == saif->master_id) 374 scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 375 else 376 scr |= BM_SAIF_CTRL_SLAVE_MODE; 377 378 __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 379 break; 380 default: 381 return -EINVAL; 382 } 383 384 return 0; 385 } 386 387 static int mxs_saif_startup(struct snd_pcm_substream *substream, 388 struct snd_soc_dai *cpu_dai) 389 { 390 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 391 392 /* clear error status to 0 for each re-open */ 393 saif->fifo_underrun = 0; 394 saif->fifo_overrun = 0; 395 396 /* Clear Reset for normal operations */ 397 __raw_writel(BM_SAIF_CTRL_SFTRST, 398 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 399 400 /* clear clock gate */ 401 __raw_writel(BM_SAIF_CTRL_CLKGATE, 402 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 403 404 clk_prepare(saif->clk); 405 406 return 0; 407 } 408 409 static void mxs_saif_shutdown(struct snd_pcm_substream *substream, 410 struct snd_soc_dai *cpu_dai) 411 { 412 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 413 414 clk_unprepare(saif->clk); 415 } 416 417 /* 418 * Should only be called when port is inactive. 419 * although can be called multiple times by upper layers. 420 */ 421 static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 422 struct snd_pcm_hw_params *params, 423 struct snd_soc_dai *cpu_dai) 424 { 425 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 426 struct mxs_saif *master_saif; 427 u32 scr, stat; 428 int ret; 429 430 master_saif = mxs_saif_get_master(saif); 431 if (!master_saif) 432 return -EINVAL; 433 434 /* mclk should already be set */ 435 if (!saif->mclk && saif->mclk_in_use) { 436 dev_err(cpu_dai->dev, "set mclk first\n"); 437 return -EINVAL; 438 } 439 440 stat = __raw_readl(saif->base + SAIF_STAT); 441 if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) { 442 dev_err(cpu_dai->dev, "error: busy\n"); 443 return -EBUSY; 444 } 445 446 /* 447 * Set saif clk based on sample rate. 448 * If mclk is used, we also set mclk, if not, saif->mclk is 449 * default 0, means not used. 450 */ 451 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 452 if (ret) { 453 dev_err(cpu_dai->dev, "unable to get proper clk\n"); 454 return ret; 455 } 456 457 if (saif != master_saif) { 458 /* 459 * Set an initial clock rate for the saif internal logic to work 460 * properly. This is important when working in EXTMASTER mode 461 * that uses the other saif's BITCLK&LRCLK but it still needs a 462 * basic clock which should be fast enough for the internal 463 * logic. 464 */ 465 clk_enable(saif->clk); 466 ret = clk_set_rate(saif->clk, 24000000); 467 clk_disable(saif->clk); 468 if (ret) 469 return ret; 470 471 clk_prepare(master_saif->clk); 472 } 473 474 scr = __raw_readl(saif->base + SAIF_CTRL); 475 476 scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 477 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 478 switch (params_format(params)) { 479 case SNDRV_PCM_FORMAT_S16_LE: 480 scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 481 break; 482 case SNDRV_PCM_FORMAT_S20_3LE: 483 scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 484 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 485 break; 486 case SNDRV_PCM_FORMAT_S24_LE: 487 scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 488 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 489 break; 490 default: 491 return -EINVAL; 492 } 493 494 /* Tx/Rx config */ 495 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 496 /* enable TX mode */ 497 scr &= ~BM_SAIF_CTRL_READ_MODE; 498 } else { 499 /* enable RX mode */ 500 scr |= BM_SAIF_CTRL_READ_MODE; 501 } 502 503 __raw_writel(scr, saif->base + SAIF_CTRL); 504 return 0; 505 } 506 507 static int mxs_saif_prepare(struct snd_pcm_substream *substream, 508 struct snd_soc_dai *cpu_dai) 509 { 510 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 511 512 /* enable FIFO error irqs */ 513 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 514 saif->base + SAIF_CTRL + MXS_SET_ADDR); 515 516 return 0; 517 } 518 519 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 520 struct snd_soc_dai *cpu_dai) 521 { 522 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 523 struct mxs_saif *master_saif; 524 u32 delay; 525 int ret; 526 527 master_saif = mxs_saif_get_master(saif); 528 if (!master_saif) 529 return -EINVAL; 530 531 switch (cmd) { 532 case SNDRV_PCM_TRIGGER_START: 533 case SNDRV_PCM_TRIGGER_RESUME: 534 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 535 if (saif->state == MXS_SAIF_STATE_RUNNING) 536 return 0; 537 538 dev_dbg(cpu_dai->dev, "start\n"); 539 540 ret = clk_enable(master_saif->clk); 541 if (ret) { 542 dev_err(saif->dev, "Failed to enable master clock\n"); 543 return ret; 544 } 545 546 /* 547 * If the saif's master is not itself, we also need to enable 548 * itself clk for its internal basic logic to work. 549 */ 550 if (saif != master_saif) { 551 ret = clk_enable(saif->clk); 552 if (ret) { 553 dev_err(saif->dev, "Failed to enable master clock\n"); 554 clk_disable(master_saif->clk); 555 return ret; 556 } 557 558 __raw_writel(BM_SAIF_CTRL_RUN, 559 saif->base + SAIF_CTRL + MXS_SET_ADDR); 560 } 561 562 if (!master_saif->mclk_in_use) 563 __raw_writel(BM_SAIF_CTRL_RUN, 564 master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 565 566 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 567 /* 568 * write data to saif data register to trigger 569 * the transfer. 570 * For 24-bit format the 32-bit FIFO register stores 571 * only one channel, so we need to write twice. 572 * This is also safe for the other non 24-bit formats. 573 */ 574 __raw_writel(0, saif->base + SAIF_DATA); 575 __raw_writel(0, saif->base + SAIF_DATA); 576 } else { 577 /* 578 * read data from saif data register to trigger 579 * the receive. 580 * For 24-bit format the 32-bit FIFO register stores 581 * only one channel, so we need to read twice. 582 * This is also safe for the other non 24-bit formats. 583 */ 584 __raw_readl(saif->base + SAIF_DATA); 585 __raw_readl(saif->base + SAIF_DATA); 586 } 587 588 master_saif->ongoing = 1; 589 saif->state = MXS_SAIF_STATE_RUNNING; 590 591 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 592 __raw_readl(saif->base + SAIF_CTRL), 593 __raw_readl(saif->base + SAIF_STAT)); 594 595 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 596 __raw_readl(master_saif->base + SAIF_CTRL), 597 __raw_readl(master_saif->base + SAIF_STAT)); 598 break; 599 case SNDRV_PCM_TRIGGER_SUSPEND: 600 case SNDRV_PCM_TRIGGER_STOP: 601 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 602 if (saif->state == MXS_SAIF_STATE_STOPPED) 603 return 0; 604 605 dev_dbg(cpu_dai->dev, "stop\n"); 606 607 /* wait a while for the current sample to complete */ 608 delay = USEC_PER_SEC / master_saif->cur_rate; 609 610 if (!master_saif->mclk_in_use) { 611 __raw_writel(BM_SAIF_CTRL_RUN, 612 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 613 udelay(delay); 614 } 615 clk_disable(master_saif->clk); 616 617 if (saif != master_saif) { 618 __raw_writel(BM_SAIF_CTRL_RUN, 619 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 620 udelay(delay); 621 clk_disable(saif->clk); 622 } 623 624 master_saif->ongoing = 0; 625 saif->state = MXS_SAIF_STATE_STOPPED; 626 627 break; 628 default: 629 return -EINVAL; 630 } 631 632 return 0; 633 } 634 635 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 636 #define MXS_SAIF_FORMATS \ 637 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 638 SNDRV_PCM_FMTBIT_S24_LE) 639 640 static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 641 .startup = mxs_saif_startup, 642 .shutdown = mxs_saif_shutdown, 643 .trigger = mxs_saif_trigger, 644 .prepare = mxs_saif_prepare, 645 .hw_params = mxs_saif_hw_params, 646 .set_sysclk = mxs_saif_set_dai_sysclk, 647 .set_fmt = mxs_saif_set_dai_fmt, 648 }; 649 650 static int mxs_saif_dai_probe(struct snd_soc_dai *dai) 651 { 652 struct mxs_saif *saif = dev_get_drvdata(dai->dev); 653 654 snd_soc_dai_set_drvdata(dai, saif); 655 656 return 0; 657 } 658 659 static struct snd_soc_dai_driver mxs_saif_dai = { 660 .name = "mxs-saif", 661 .probe = mxs_saif_dai_probe, 662 .playback = { 663 .channels_min = 2, 664 .channels_max = 2, 665 .rates = MXS_SAIF_RATES, 666 .formats = MXS_SAIF_FORMATS, 667 }, 668 .capture = { 669 .channels_min = 2, 670 .channels_max = 2, 671 .rates = MXS_SAIF_RATES, 672 .formats = MXS_SAIF_FORMATS, 673 }, 674 .ops = &mxs_saif_dai_ops, 675 }; 676 677 static const struct snd_soc_component_driver mxs_saif_component = { 678 .name = "mxs-saif", 679 }; 680 681 static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 682 { 683 struct mxs_saif *saif = dev_id; 684 unsigned int stat; 685 686 stat = __raw_readl(saif->base + SAIF_STAT); 687 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 688 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 689 return IRQ_NONE; 690 691 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 692 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 693 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 694 saif->base + SAIF_STAT + MXS_CLR_ADDR); 695 } 696 697 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 698 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 699 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 700 saif->base + SAIF_STAT + MXS_CLR_ADDR); 701 } 702 703 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 704 __raw_readl(saif->base + SAIF_CTRL), 705 __raw_readl(saif->base + SAIF_STAT)); 706 707 return IRQ_HANDLED; 708 } 709 710 static int mxs_saif_mclk_init(struct platform_device *pdev) 711 { 712 struct mxs_saif *saif = platform_get_drvdata(pdev); 713 struct device_node *np = pdev->dev.of_node; 714 struct clk *clk; 715 int ret; 716 717 clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk", 718 __clk_get_name(saif->clk), 0, 719 saif->base + SAIF_CTRL, 720 BP_SAIF_CTRL_BITCLK_MULT_RATE, 3, 721 0, NULL); 722 if (IS_ERR(clk)) { 723 ret = PTR_ERR(clk); 724 if (ret == -EEXIST) 725 return 0; 726 dev_err(&pdev->dev, "failed to register mclk: %d\n", ret); 727 return PTR_ERR(clk); 728 } 729 730 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); 731 if (ret) 732 return ret; 733 734 return 0; 735 } 736 737 static int mxs_saif_probe(struct platform_device *pdev) 738 { 739 struct device_node *np = pdev->dev.of_node; 740 struct resource *iores; 741 struct mxs_saif *saif; 742 int irq, ret = 0; 743 struct device_node *master; 744 745 if (!np) 746 return -EINVAL; 747 748 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 749 if (!saif) 750 return -ENOMEM; 751 752 ret = of_alias_get_id(np, "saif"); 753 if (ret < 0) 754 return ret; 755 else 756 saif->id = ret; 757 758 if (saif->id >= ARRAY_SIZE(mxs_saif)) { 759 dev_err(&pdev->dev, "get wrong saif id\n"); 760 return -EINVAL; 761 } 762 763 /* 764 * If there is no "fsl,saif-master" phandle, it's a saif 765 * master. Otherwise, it's a slave and its phandle points 766 * to the master. 767 */ 768 master = of_parse_phandle(np, "fsl,saif-master", 0); 769 if (!master) { 770 saif->master_id = saif->id; 771 } else { 772 ret = of_alias_get_id(master, "saif"); 773 if (ret < 0) 774 return ret; 775 else 776 saif->master_id = ret; 777 778 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) { 779 dev_err(&pdev->dev, "get wrong master id\n"); 780 return -EINVAL; 781 } 782 } 783 784 mxs_saif[saif->id] = saif; 785 786 saif->clk = devm_clk_get(&pdev->dev, NULL); 787 if (IS_ERR(saif->clk)) { 788 ret = PTR_ERR(saif->clk); 789 dev_err(&pdev->dev, "Cannot get the clock: %d\n", 790 ret); 791 return ret; 792 } 793 794 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 795 796 saif->base = devm_ioremap_resource(&pdev->dev, iores); 797 if (IS_ERR(saif->base)) 798 return PTR_ERR(saif->base); 799 800 irq = platform_get_irq(pdev, 0); 801 if (irq < 0) { 802 ret = irq; 803 dev_err(&pdev->dev, "failed to get irq resource: %d\n", 804 ret); 805 return ret; 806 } 807 808 saif->dev = &pdev->dev; 809 ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0, 810 dev_name(&pdev->dev), saif); 811 if (ret) { 812 dev_err(&pdev->dev, "failed to request irq\n"); 813 return ret; 814 } 815 816 platform_set_drvdata(pdev, saif); 817 818 /* We only support saif0 being tx and clock master */ 819 if (saif->id == 0) { 820 ret = mxs_saif_mclk_init(pdev); 821 if (ret) 822 dev_warn(&pdev->dev, "failed to init clocks\n"); 823 } 824 825 ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component, 826 &mxs_saif_dai, 1); 827 if (ret) { 828 dev_err(&pdev->dev, "register DAI failed\n"); 829 return ret; 830 } 831 832 ret = mxs_pcm_platform_register(&pdev->dev); 833 if (ret) { 834 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 835 return ret; 836 } 837 838 return 0; 839 } 840 841 static const struct of_device_id mxs_saif_dt_ids[] = { 842 { .compatible = "fsl,imx28-saif", }, 843 { /* sentinel */ } 844 }; 845 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 846 847 static struct platform_driver mxs_saif_driver = { 848 .probe = mxs_saif_probe, 849 850 .driver = { 851 .name = "mxs-saif", 852 .of_match_table = mxs_saif_dt_ids, 853 }, 854 }; 855 856 module_platform_driver(mxs_saif_driver); 857 858 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 859 MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 860 MODULE_LICENSE("GPL"); 861 MODULE_ALIAS("platform:mxs-saif"); 862