1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/slab.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/clk.h> 27 #include <linux/clk-provider.h> 28 #include <linux/delay.h> 29 #include <linux/time.h> 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/soc.h> 34 #include <asm/mach-types.h> 35 36 #include "mxs-saif.h" 37 38 #define MXS_SET_ADDR 0x4 39 #define MXS_CLR_ADDR 0x8 40 41 static struct mxs_saif *mxs_saif[2]; 42 43 /* 44 * SAIF is a little different with other normal SOC DAIs on clock using. 45 * 46 * For MXS, two SAIF modules are instantiated on-chip. 47 * Each SAIF has a set of clock pins and can be operating in master 48 * mode simultaneously if they are connected to different off-chip codecs. 49 * Also, one of the two SAIFs can master or drive the clock pins while the 50 * other SAIF, in slave mode, receives clocking from the master SAIF. 51 * This also means that both SAIFs must operate at the same sample rate. 52 * 53 * We abstract this as each saif has a master, the master could be 54 * himself or other saifs. In the generic saif driver, saif does not need 55 * to know the different clkmux. Saif only needs to know who is his master 56 * and operating his master to generate the proper clock rate for him. 57 * The master id is provided in mach-specific layer according to different 58 * clkmux setting. 59 */ 60 61 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 62 int clk_id, unsigned int freq, int dir) 63 { 64 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 65 66 switch (clk_id) { 67 case MXS_SAIF_MCLK: 68 saif->mclk = freq; 69 break; 70 default: 71 return -EINVAL; 72 } 73 return 0; 74 } 75 76 /* 77 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 78 * is provided by other SAIF, we provide a interface here to get its master 79 * from its master_id. 80 * Note that the master could be himself. 81 */ 82 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 83 { 84 return mxs_saif[saif->master_id]; 85 } 86 87 /* 88 * Set SAIF clock and MCLK 89 */ 90 static int mxs_saif_set_clk(struct mxs_saif *saif, 91 unsigned int mclk, 92 unsigned int rate) 93 { 94 u32 scr; 95 int ret; 96 struct mxs_saif *master_saif; 97 98 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 99 100 /* Set master saif to generate proper clock */ 101 master_saif = mxs_saif_get_master(saif); 102 if (!master_saif) 103 return -EINVAL; 104 105 dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 106 107 /* Checking if can playback and capture simutaneously */ 108 if (master_saif->ongoing && rate != master_saif->cur_rate) { 109 dev_err(saif->dev, 110 "can not change clock, master saif%d(rate %d) is ongoing\n", 111 master_saif->id, master_saif->cur_rate); 112 return -EINVAL; 113 } 114 115 scr = __raw_readl(master_saif->base + SAIF_CTRL); 116 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 117 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 118 119 /* 120 * Set SAIF clock 121 * 122 * The SAIF clock should be either 384*fs or 512*fs. 123 * If MCLK is used, the SAIF clk ratio need to match mclk ratio. 124 * For 32x mclk, set saif clk as 512*fs. 125 * For 48x mclk, set saif clk as 384*fs. 126 * 127 * If MCLK is not used, we just set saif clk to 512*fs. 128 */ 129 clk_prepare_enable(master_saif->clk); 130 131 if (master_saif->mclk_in_use) { 132 if (mclk % 32 == 0) { 133 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 134 ret = clk_set_rate(master_saif->clk, 512 * rate); 135 } else if (mclk % 48 == 0) { 136 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 137 ret = clk_set_rate(master_saif->clk, 384 * rate); 138 } else { 139 /* SAIF MCLK should be either 32x or 48x */ 140 clk_disable_unprepare(master_saif->clk); 141 return -EINVAL; 142 } 143 } else { 144 ret = clk_set_rate(master_saif->clk, 512 * rate); 145 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 146 } 147 148 clk_disable_unprepare(master_saif->clk); 149 150 if (ret) 151 return ret; 152 153 master_saif->cur_rate = rate; 154 155 if (!master_saif->mclk_in_use) { 156 __raw_writel(scr, master_saif->base + SAIF_CTRL); 157 return 0; 158 } 159 160 /* 161 * Program the over-sample rate for MCLK output 162 * 163 * The available MCLK range is 32x, 48x... 512x. The rate 164 * could be from 8kHz to 192kH. 165 */ 166 switch (mclk / rate) { 167 case 32: 168 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 169 break; 170 case 64: 171 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 172 break; 173 case 128: 174 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 175 break; 176 case 256: 177 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 178 break; 179 case 512: 180 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 181 break; 182 case 48: 183 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 184 break; 185 case 96: 186 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 187 break; 188 case 192: 189 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 190 break; 191 case 384: 192 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 193 break; 194 default: 195 return -EINVAL; 196 } 197 198 __raw_writel(scr, master_saif->base + SAIF_CTRL); 199 200 return 0; 201 } 202 203 /* 204 * Put and disable MCLK. 205 */ 206 int mxs_saif_put_mclk(unsigned int saif_id) 207 { 208 struct mxs_saif *saif = mxs_saif[saif_id]; 209 u32 stat; 210 211 if (!saif) 212 return -EINVAL; 213 214 stat = __raw_readl(saif->base + SAIF_STAT); 215 if (stat & BM_SAIF_STAT_BUSY) { 216 dev_err(saif->dev, "error: busy\n"); 217 return -EBUSY; 218 } 219 220 clk_disable_unprepare(saif->clk); 221 222 /* disable MCLK output */ 223 __raw_writel(BM_SAIF_CTRL_CLKGATE, 224 saif->base + SAIF_CTRL + MXS_SET_ADDR); 225 __raw_writel(BM_SAIF_CTRL_RUN, 226 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 227 228 saif->mclk_in_use = 0; 229 return 0; 230 } 231 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); 232 233 /* 234 * Get MCLK and set clock rate, then enable it 235 * 236 * This interface is used for codecs who are using MCLK provided 237 * by saif. 238 */ 239 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 240 unsigned int rate) 241 { 242 struct mxs_saif *saif = mxs_saif[saif_id]; 243 u32 stat; 244 int ret; 245 struct mxs_saif *master_saif; 246 247 if (!saif) 248 return -EINVAL; 249 250 /* Clear Reset */ 251 __raw_writel(BM_SAIF_CTRL_SFTRST, 252 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 253 254 /* FIXME: need clear clk gate for register r/w */ 255 __raw_writel(BM_SAIF_CTRL_CLKGATE, 256 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 257 258 master_saif = mxs_saif_get_master(saif); 259 if (saif != master_saif) { 260 dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 261 return -EINVAL; 262 } 263 264 stat = __raw_readl(saif->base + SAIF_STAT); 265 if (stat & BM_SAIF_STAT_BUSY) { 266 dev_err(saif->dev, "error: busy\n"); 267 return -EBUSY; 268 } 269 270 saif->mclk_in_use = 1; 271 ret = mxs_saif_set_clk(saif, mclk, rate); 272 if (ret) 273 return ret; 274 275 ret = clk_prepare_enable(saif->clk); 276 if (ret) 277 return ret; 278 279 /* enable MCLK output */ 280 __raw_writel(BM_SAIF_CTRL_RUN, 281 saif->base + SAIF_CTRL + MXS_SET_ADDR); 282 283 return 0; 284 } 285 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); 286 287 /* 288 * SAIF DAI format configuration. 289 * Should only be called when port is inactive. 290 */ 291 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 292 { 293 u32 scr, stat; 294 u32 scr0; 295 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 296 297 stat = __raw_readl(saif->base + SAIF_STAT); 298 if (stat & BM_SAIF_STAT_BUSY) { 299 dev_err(cpu_dai->dev, "error: busy\n"); 300 return -EBUSY; 301 } 302 303 scr0 = __raw_readl(saif->base + SAIF_CTRL); 304 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 305 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 306 scr = 0; 307 308 /* DAI mode */ 309 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 310 case SND_SOC_DAIFMT_I2S: 311 /* data frame low 1clk before data */ 312 scr |= BM_SAIF_CTRL_DELAY; 313 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 314 break; 315 case SND_SOC_DAIFMT_LEFT_J: 316 /* data frame high with data */ 317 scr &= ~BM_SAIF_CTRL_DELAY; 318 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 319 scr &= ~BM_SAIF_CTRL_JUSTIFY; 320 break; 321 default: 322 return -EINVAL; 323 } 324 325 /* DAI clock inversion */ 326 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 327 case SND_SOC_DAIFMT_IB_IF: 328 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 329 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 330 break; 331 case SND_SOC_DAIFMT_IB_NF: 332 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 333 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 334 break; 335 case SND_SOC_DAIFMT_NB_IF: 336 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 337 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 338 break; 339 case SND_SOC_DAIFMT_NB_NF: 340 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 341 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 342 break; 343 } 344 345 /* 346 * Note: We simply just support master mode since SAIF TX can only 347 * work as master. 348 * Here the master is relative to codec side. 349 * Saif internally could be slave when working on EXTMASTER mode. 350 * We just hide this to machine driver. 351 */ 352 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 353 case SND_SOC_DAIFMT_CBS_CFS: 354 if (saif->id == saif->master_id) 355 scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 356 else 357 scr |= BM_SAIF_CTRL_SLAVE_MODE; 358 359 __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 360 break; 361 default: 362 return -EINVAL; 363 } 364 365 return 0; 366 } 367 368 static int mxs_saif_startup(struct snd_pcm_substream *substream, 369 struct snd_soc_dai *cpu_dai) 370 { 371 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 372 373 /* clear error status to 0 for each re-open */ 374 saif->fifo_underrun = 0; 375 saif->fifo_overrun = 0; 376 377 /* Clear Reset for normal operations */ 378 __raw_writel(BM_SAIF_CTRL_SFTRST, 379 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 380 381 /* clear clock gate */ 382 __raw_writel(BM_SAIF_CTRL_CLKGATE, 383 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 384 385 return 0; 386 } 387 388 /* 389 * Should only be called when port is inactive. 390 * although can be called multiple times by upper layers. 391 */ 392 static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 393 struct snd_pcm_hw_params *params, 394 struct snd_soc_dai *cpu_dai) 395 { 396 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 397 struct mxs_saif *master_saif; 398 u32 scr, stat; 399 int ret; 400 401 master_saif = mxs_saif_get_master(saif); 402 if (!master_saif) 403 return -EINVAL; 404 405 /* mclk should already be set */ 406 if (!saif->mclk && saif->mclk_in_use) { 407 dev_err(cpu_dai->dev, "set mclk first\n"); 408 return -EINVAL; 409 } 410 411 stat = __raw_readl(saif->base + SAIF_STAT); 412 if (stat & BM_SAIF_STAT_BUSY) { 413 dev_err(cpu_dai->dev, "error: busy\n"); 414 return -EBUSY; 415 } 416 417 /* 418 * Set saif clk based on sample rate. 419 * If mclk is used, we also set mclk, if not, saif->mclk is 420 * default 0, means not used. 421 */ 422 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 423 if (ret) { 424 dev_err(cpu_dai->dev, "unable to get proper clk\n"); 425 return ret; 426 } 427 428 /* prepare clk in hw_param, enable in trigger */ 429 clk_prepare(saif->clk); 430 if (saif != master_saif) { 431 /* 432 * Set an initial clock rate for the saif internal logic to work 433 * properly. This is important when working in EXTMASTER mode 434 * that uses the other saif's BITCLK&LRCLK but it still needs a 435 * basic clock which should be fast enough for the internal 436 * logic. 437 */ 438 clk_enable(saif->clk); 439 ret = clk_set_rate(saif->clk, 24000000); 440 clk_disable(saif->clk); 441 if (ret) 442 return ret; 443 444 clk_prepare(master_saif->clk); 445 } 446 447 scr = __raw_readl(saif->base + SAIF_CTRL); 448 449 scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 450 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 451 switch (params_format(params)) { 452 case SNDRV_PCM_FORMAT_S16_LE: 453 scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 454 break; 455 case SNDRV_PCM_FORMAT_S20_3LE: 456 scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 457 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 458 break; 459 case SNDRV_PCM_FORMAT_S24_LE: 460 scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 461 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 462 break; 463 default: 464 return -EINVAL; 465 } 466 467 /* Tx/Rx config */ 468 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 469 /* enable TX mode */ 470 scr &= ~BM_SAIF_CTRL_READ_MODE; 471 } else { 472 /* enable RX mode */ 473 scr |= BM_SAIF_CTRL_READ_MODE; 474 } 475 476 __raw_writel(scr, saif->base + SAIF_CTRL); 477 return 0; 478 } 479 480 static int mxs_saif_prepare(struct snd_pcm_substream *substream, 481 struct snd_soc_dai *cpu_dai) 482 { 483 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 484 485 /* enable FIFO error irqs */ 486 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 487 saif->base + SAIF_CTRL + MXS_SET_ADDR); 488 489 return 0; 490 } 491 492 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 493 struct snd_soc_dai *cpu_dai) 494 { 495 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 496 struct mxs_saif *master_saif; 497 u32 delay; 498 499 master_saif = mxs_saif_get_master(saif); 500 if (!master_saif) 501 return -EINVAL; 502 503 switch (cmd) { 504 case SNDRV_PCM_TRIGGER_START: 505 case SNDRV_PCM_TRIGGER_RESUME: 506 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 507 dev_dbg(cpu_dai->dev, "start\n"); 508 509 clk_enable(master_saif->clk); 510 if (!master_saif->mclk_in_use) 511 __raw_writel(BM_SAIF_CTRL_RUN, 512 master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 513 514 /* 515 * If the saif's master is not himself, we also need to enable 516 * itself clk for its internal basic logic to work. 517 */ 518 if (saif != master_saif) { 519 clk_enable(saif->clk); 520 __raw_writel(BM_SAIF_CTRL_RUN, 521 saif->base + SAIF_CTRL + MXS_SET_ADDR); 522 } 523 524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 525 /* 526 * write data to saif data register to trigger 527 * the transfer. 528 * For 24-bit format the 32-bit FIFO register stores 529 * only one channel, so we need to write twice. 530 * This is also safe for the other non 24-bit formats. 531 */ 532 __raw_writel(0, saif->base + SAIF_DATA); 533 __raw_writel(0, saif->base + SAIF_DATA); 534 } else { 535 /* 536 * read data from saif data register to trigger 537 * the receive. 538 * For 24-bit format the 32-bit FIFO register stores 539 * only one channel, so we need to read twice. 540 * This is also safe for the other non 24-bit formats. 541 */ 542 __raw_readl(saif->base + SAIF_DATA); 543 __raw_readl(saif->base + SAIF_DATA); 544 } 545 546 master_saif->ongoing = 1; 547 548 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 549 __raw_readl(saif->base + SAIF_CTRL), 550 __raw_readl(saif->base + SAIF_STAT)); 551 552 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 553 __raw_readl(master_saif->base + SAIF_CTRL), 554 __raw_readl(master_saif->base + SAIF_STAT)); 555 break; 556 case SNDRV_PCM_TRIGGER_SUSPEND: 557 case SNDRV_PCM_TRIGGER_STOP: 558 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 559 dev_dbg(cpu_dai->dev, "stop\n"); 560 561 /* wait a while for the current sample to complete */ 562 delay = USEC_PER_SEC / master_saif->cur_rate; 563 564 if (!master_saif->mclk_in_use) { 565 __raw_writel(BM_SAIF_CTRL_RUN, 566 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 567 udelay(delay); 568 } 569 clk_disable(master_saif->clk); 570 571 if (saif != master_saif) { 572 __raw_writel(BM_SAIF_CTRL_RUN, 573 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 574 udelay(delay); 575 clk_disable(saif->clk); 576 } 577 578 master_saif->ongoing = 0; 579 580 break; 581 default: 582 return -EINVAL; 583 } 584 585 return 0; 586 } 587 588 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 589 #define MXS_SAIF_FORMATS \ 590 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 591 SNDRV_PCM_FMTBIT_S24_LE) 592 593 static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 594 .startup = mxs_saif_startup, 595 .trigger = mxs_saif_trigger, 596 .prepare = mxs_saif_prepare, 597 .hw_params = mxs_saif_hw_params, 598 .set_sysclk = mxs_saif_set_dai_sysclk, 599 .set_fmt = mxs_saif_set_dai_fmt, 600 }; 601 602 static int mxs_saif_dai_probe(struct snd_soc_dai *dai) 603 { 604 struct mxs_saif *saif = dev_get_drvdata(dai->dev); 605 606 snd_soc_dai_set_drvdata(dai, saif); 607 608 return 0; 609 } 610 611 static struct snd_soc_dai_driver mxs_saif_dai = { 612 .name = "mxs-saif", 613 .probe = mxs_saif_dai_probe, 614 .playback = { 615 .channels_min = 2, 616 .channels_max = 2, 617 .rates = MXS_SAIF_RATES, 618 .formats = MXS_SAIF_FORMATS, 619 }, 620 .capture = { 621 .channels_min = 2, 622 .channels_max = 2, 623 .rates = MXS_SAIF_RATES, 624 .formats = MXS_SAIF_FORMATS, 625 }, 626 .ops = &mxs_saif_dai_ops, 627 }; 628 629 static const struct snd_soc_component_driver mxs_saif_component = { 630 .name = "mxs-saif", 631 }; 632 633 static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 634 { 635 struct mxs_saif *saif = dev_id; 636 unsigned int stat; 637 638 stat = __raw_readl(saif->base + SAIF_STAT); 639 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 640 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 641 return IRQ_NONE; 642 643 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 644 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 645 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 646 saif->base + SAIF_STAT + MXS_CLR_ADDR); 647 } 648 649 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 650 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 651 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 652 saif->base + SAIF_STAT + MXS_CLR_ADDR); 653 } 654 655 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 656 __raw_readl(saif->base + SAIF_CTRL), 657 __raw_readl(saif->base + SAIF_STAT)); 658 659 return IRQ_HANDLED; 660 } 661 662 static int mxs_saif_mclk_init(struct platform_device *pdev) 663 { 664 struct mxs_saif *saif = platform_get_drvdata(pdev); 665 struct device_node *np = pdev->dev.of_node; 666 struct clk *clk; 667 int ret; 668 669 clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk", 670 __clk_get_name(saif->clk), 0, 671 saif->base + SAIF_CTRL, 672 BP_SAIF_CTRL_BITCLK_MULT_RATE, 3, 673 0, NULL); 674 if (IS_ERR(clk)) { 675 ret = PTR_ERR(clk); 676 if (ret == -EEXIST) 677 return 0; 678 dev_err(&pdev->dev, "failed to register mclk: %d\n", ret); 679 return PTR_ERR(clk); 680 } 681 682 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); 683 if (ret) 684 return ret; 685 686 return 0; 687 } 688 689 static int mxs_saif_probe(struct platform_device *pdev) 690 { 691 struct device_node *np = pdev->dev.of_node; 692 struct resource *iores; 693 struct mxs_saif *saif; 694 int ret = 0; 695 struct device_node *master; 696 697 if (!np) 698 return -EINVAL; 699 700 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 701 if (!saif) 702 return -ENOMEM; 703 704 ret = of_alias_get_id(np, "saif"); 705 if (ret < 0) 706 return ret; 707 else 708 saif->id = ret; 709 710 /* 711 * If there is no "fsl,saif-master" phandle, it's a saif 712 * master. Otherwise, it's a slave and its phandle points 713 * to the master. 714 */ 715 master = of_parse_phandle(np, "fsl,saif-master", 0); 716 if (!master) { 717 saif->master_id = saif->id; 718 } else { 719 ret = of_alias_get_id(master, "saif"); 720 if (ret < 0) 721 return ret; 722 else 723 saif->master_id = ret; 724 } 725 726 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) { 727 dev_err(&pdev->dev, "get wrong master id\n"); 728 return -EINVAL; 729 } 730 731 mxs_saif[saif->id] = saif; 732 733 saif->clk = devm_clk_get(&pdev->dev, NULL); 734 if (IS_ERR(saif->clk)) { 735 ret = PTR_ERR(saif->clk); 736 dev_err(&pdev->dev, "Cannot get the clock: %d\n", 737 ret); 738 return ret; 739 } 740 741 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 742 743 saif->base = devm_ioremap_resource(&pdev->dev, iores); 744 if (IS_ERR(saif->base)) 745 return PTR_ERR(saif->base); 746 747 saif->irq = platform_get_irq(pdev, 0); 748 if (saif->irq < 0) { 749 ret = saif->irq; 750 dev_err(&pdev->dev, "failed to get irq resource: %d\n", 751 ret); 752 return ret; 753 } 754 755 saif->dev = &pdev->dev; 756 ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0, 757 "mxs-saif", saif); 758 if (ret) { 759 dev_err(&pdev->dev, "failed to request irq\n"); 760 return ret; 761 } 762 763 platform_set_drvdata(pdev, saif); 764 765 /* We only support saif0 being tx and clock master */ 766 if (saif->id == 0) { 767 ret = mxs_saif_mclk_init(pdev); 768 if (ret) 769 dev_warn(&pdev->dev, "failed to init clocks\n"); 770 } 771 772 ret = snd_soc_register_component(&pdev->dev, &mxs_saif_component, 773 &mxs_saif_dai, 1); 774 if (ret) { 775 dev_err(&pdev->dev, "register DAI failed\n"); 776 return ret; 777 } 778 779 ret = mxs_pcm_platform_register(&pdev->dev); 780 if (ret) { 781 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 782 goto failed_pdev_alloc; 783 } 784 785 return 0; 786 787 failed_pdev_alloc: 788 snd_soc_unregister_component(&pdev->dev); 789 790 return ret; 791 } 792 793 static int mxs_saif_remove(struct platform_device *pdev) 794 { 795 mxs_pcm_platform_unregister(&pdev->dev); 796 snd_soc_unregister_component(&pdev->dev); 797 798 return 0; 799 } 800 801 static const struct of_device_id mxs_saif_dt_ids[] = { 802 { .compatible = "fsl,imx28-saif", }, 803 { /* sentinel */ } 804 }; 805 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 806 807 static struct platform_driver mxs_saif_driver = { 808 .probe = mxs_saif_probe, 809 .remove = mxs_saif_remove, 810 811 .driver = { 812 .name = "mxs-saif", 813 .owner = THIS_MODULE, 814 .of_match_table = mxs_saif_dt_ids, 815 }, 816 }; 817 818 module_platform_driver(mxs_saif_driver); 819 820 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 821 MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 822 MODULE_LICENSE("GPL"); 823 MODULE_ALIAS("platform:mxs-saif"); 824