1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/slab.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/clk.h> 27 #include <linux/clk-provider.h> 28 #include <linux/delay.h> 29 #include <linux/io.h> 30 #include <linux/time.h> 31 #include <sound/core.h> 32 #include <sound/pcm.h> 33 #include <sound/pcm_params.h> 34 #include <sound/soc.h> 35 36 #include "mxs-saif.h" 37 38 #define MXS_SET_ADDR 0x4 39 #define MXS_CLR_ADDR 0x8 40 41 static struct mxs_saif *mxs_saif[2]; 42 43 /* 44 * SAIF is a little different with other normal SOC DAIs on clock using. 45 * 46 * For MXS, two SAIF modules are instantiated on-chip. 47 * Each SAIF has a set of clock pins and can be operating in master 48 * mode simultaneously if they are connected to different off-chip codecs. 49 * Also, one of the two SAIFs can master or drive the clock pins while the 50 * other SAIF, in slave mode, receives clocking from the master SAIF. 51 * This also means that both SAIFs must operate at the same sample rate. 52 * 53 * We abstract this as each saif has a master, the master could be 54 * itself or other saifs. In the generic saif driver, saif does not need 55 * to know the different clkmux. Saif only needs to know who is its master 56 * and operating its master to generate the proper clock rate for it. 57 * The master id is provided in mach-specific layer according to different 58 * clkmux setting. 59 */ 60 61 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 62 int clk_id, unsigned int freq, int dir) 63 { 64 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 65 66 switch (clk_id) { 67 case MXS_SAIF_MCLK: 68 saif->mclk = freq; 69 break; 70 default: 71 return -EINVAL; 72 } 73 return 0; 74 } 75 76 /* 77 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 78 * is provided by other SAIF, we provide a interface here to get its master 79 * from its master_id. 80 * Note that the master could be itself. 81 */ 82 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 83 { 84 return mxs_saif[saif->master_id]; 85 } 86 87 /* 88 * Set SAIF clock and MCLK 89 */ 90 static int mxs_saif_set_clk(struct mxs_saif *saif, 91 unsigned int mclk, 92 unsigned int rate) 93 { 94 u32 scr; 95 int ret; 96 struct mxs_saif *master_saif; 97 98 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 99 100 /* Set master saif to generate proper clock */ 101 master_saif = mxs_saif_get_master(saif); 102 if (!master_saif) 103 return -EINVAL; 104 105 dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 106 107 /* Checking if can playback and capture simutaneously */ 108 if (master_saif->ongoing && rate != master_saif->cur_rate) { 109 dev_err(saif->dev, 110 "can not change clock, master saif%d(rate %d) is ongoing\n", 111 master_saif->id, master_saif->cur_rate); 112 return -EINVAL; 113 } 114 115 scr = __raw_readl(master_saif->base + SAIF_CTRL); 116 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 117 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 118 119 /* 120 * Set SAIF clock 121 * 122 * The SAIF clock should be either 384*fs or 512*fs. 123 * If MCLK is used, the SAIF clk ratio needs to match mclk ratio. 124 * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs. 125 * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs. 126 * 127 * If MCLK is not used, we just set saif clk to 512*fs. 128 */ 129 ret = clk_prepare_enable(master_saif->clk); 130 if (ret) 131 return ret; 132 133 if (master_saif->mclk_in_use) { 134 switch (mclk / rate) { 135 case 32: 136 case 64: 137 case 128: 138 case 256: 139 case 512: 140 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 141 ret = clk_set_rate(master_saif->clk, 512 * rate); 142 break; 143 case 48: 144 case 96: 145 case 192: 146 case 384: 147 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 148 ret = clk_set_rate(master_saif->clk, 384 * rate); 149 break; 150 default: 151 /* SAIF MCLK should be a sub-rate of 512x or 384x */ 152 clk_disable_unprepare(master_saif->clk); 153 return -EINVAL; 154 } 155 } else { 156 ret = clk_set_rate(master_saif->clk, 512 * rate); 157 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 158 } 159 160 clk_disable_unprepare(master_saif->clk); 161 162 if (ret) 163 return ret; 164 165 master_saif->cur_rate = rate; 166 167 if (!master_saif->mclk_in_use) { 168 __raw_writel(scr, master_saif->base + SAIF_CTRL); 169 return 0; 170 } 171 172 /* 173 * Program the over-sample rate for MCLK output 174 * 175 * The available MCLK range is 32x, 48x... 512x. The rate 176 * could be from 8kHz to 192kH. 177 */ 178 switch (mclk / rate) { 179 case 32: 180 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 181 break; 182 case 64: 183 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 184 break; 185 case 128: 186 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 187 break; 188 case 256: 189 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 190 break; 191 case 512: 192 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 193 break; 194 case 48: 195 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 196 break; 197 case 96: 198 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 199 break; 200 case 192: 201 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 202 break; 203 case 384: 204 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 205 break; 206 default: 207 return -EINVAL; 208 } 209 210 __raw_writel(scr, master_saif->base + SAIF_CTRL); 211 212 return 0; 213 } 214 215 /* 216 * Put and disable MCLK. 217 */ 218 int mxs_saif_put_mclk(unsigned int saif_id) 219 { 220 struct mxs_saif *saif = mxs_saif[saif_id]; 221 u32 stat; 222 223 if (!saif) 224 return -EINVAL; 225 226 stat = __raw_readl(saif->base + SAIF_STAT); 227 if (stat & BM_SAIF_STAT_BUSY) { 228 dev_err(saif->dev, "error: busy\n"); 229 return -EBUSY; 230 } 231 232 clk_disable_unprepare(saif->clk); 233 234 /* disable MCLK output */ 235 __raw_writel(BM_SAIF_CTRL_CLKGATE, 236 saif->base + SAIF_CTRL + MXS_SET_ADDR); 237 __raw_writel(BM_SAIF_CTRL_RUN, 238 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 239 240 saif->mclk_in_use = 0; 241 return 0; 242 } 243 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); 244 245 /* 246 * Get MCLK and set clock rate, then enable it 247 * 248 * This interface is used for codecs who are using MCLK provided 249 * by saif. 250 */ 251 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 252 unsigned int rate) 253 { 254 struct mxs_saif *saif = mxs_saif[saif_id]; 255 u32 stat; 256 int ret; 257 struct mxs_saif *master_saif; 258 259 if (!saif) 260 return -EINVAL; 261 262 /* Clear Reset */ 263 __raw_writel(BM_SAIF_CTRL_SFTRST, 264 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 265 266 /* FIXME: need clear clk gate for register r/w */ 267 __raw_writel(BM_SAIF_CTRL_CLKGATE, 268 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 269 270 master_saif = mxs_saif_get_master(saif); 271 if (saif != master_saif) { 272 dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 273 return -EINVAL; 274 } 275 276 stat = __raw_readl(saif->base + SAIF_STAT); 277 if (stat & BM_SAIF_STAT_BUSY) { 278 dev_err(saif->dev, "error: busy\n"); 279 return -EBUSY; 280 } 281 282 saif->mclk_in_use = 1; 283 ret = mxs_saif_set_clk(saif, mclk, rate); 284 if (ret) 285 return ret; 286 287 ret = clk_prepare_enable(saif->clk); 288 if (ret) 289 return ret; 290 291 /* enable MCLK output */ 292 __raw_writel(BM_SAIF_CTRL_RUN, 293 saif->base + SAIF_CTRL + MXS_SET_ADDR); 294 295 return 0; 296 } 297 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); 298 299 /* 300 * SAIF DAI format configuration. 301 * Should only be called when port is inactive. 302 */ 303 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 304 { 305 u32 scr, stat; 306 u32 scr0; 307 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 308 309 stat = __raw_readl(saif->base + SAIF_STAT); 310 if (stat & BM_SAIF_STAT_BUSY) { 311 dev_err(cpu_dai->dev, "error: busy\n"); 312 return -EBUSY; 313 } 314 315 /* If SAIF1 is configured as slave, the clk gate needs to be cleared 316 * before the register can be written. 317 */ 318 if (saif->id != saif->master_id) { 319 __raw_writel(BM_SAIF_CTRL_SFTRST, 320 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 321 __raw_writel(BM_SAIF_CTRL_CLKGATE, 322 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 323 } 324 325 scr0 = __raw_readl(saif->base + SAIF_CTRL); 326 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 327 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 328 scr = 0; 329 330 /* DAI mode */ 331 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 332 case SND_SOC_DAIFMT_I2S: 333 /* data frame low 1clk before data */ 334 scr |= BM_SAIF_CTRL_DELAY; 335 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 336 break; 337 case SND_SOC_DAIFMT_LEFT_J: 338 /* data frame high with data */ 339 scr &= ~BM_SAIF_CTRL_DELAY; 340 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 341 scr &= ~BM_SAIF_CTRL_JUSTIFY; 342 break; 343 default: 344 return -EINVAL; 345 } 346 347 /* DAI clock inversion */ 348 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 349 case SND_SOC_DAIFMT_IB_IF: 350 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 351 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 352 break; 353 case SND_SOC_DAIFMT_IB_NF: 354 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 355 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 356 break; 357 case SND_SOC_DAIFMT_NB_IF: 358 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 359 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 360 break; 361 case SND_SOC_DAIFMT_NB_NF: 362 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 363 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 364 break; 365 } 366 367 /* 368 * Note: We simply just support master mode since SAIF TX can only 369 * work as master. 370 * Here the master is relative to codec side. 371 * Saif internally could be slave when working on EXTMASTER mode. 372 * We just hide this to machine driver. 373 */ 374 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 375 case SND_SOC_DAIFMT_CBS_CFS: 376 if (saif->id == saif->master_id) 377 scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 378 else 379 scr |= BM_SAIF_CTRL_SLAVE_MODE; 380 381 __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 382 break; 383 default: 384 return -EINVAL; 385 } 386 387 return 0; 388 } 389 390 static int mxs_saif_startup(struct snd_pcm_substream *substream, 391 struct snd_soc_dai *cpu_dai) 392 { 393 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 394 int ret; 395 396 /* clear error status to 0 for each re-open */ 397 saif->fifo_underrun = 0; 398 saif->fifo_overrun = 0; 399 400 /* Clear Reset for normal operations */ 401 __raw_writel(BM_SAIF_CTRL_SFTRST, 402 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 403 404 /* clear clock gate */ 405 __raw_writel(BM_SAIF_CTRL_CLKGATE, 406 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 407 408 ret = clk_prepare(saif->clk); 409 if (ret) 410 return ret; 411 412 return 0; 413 } 414 415 static void mxs_saif_shutdown(struct snd_pcm_substream *substream, 416 struct snd_soc_dai *cpu_dai) 417 { 418 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 419 420 clk_unprepare(saif->clk); 421 } 422 423 /* 424 * Should only be called when port is inactive. 425 * although can be called multiple times by upper layers. 426 */ 427 static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 428 struct snd_pcm_hw_params *params, 429 struct snd_soc_dai *cpu_dai) 430 { 431 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 432 struct mxs_saif *master_saif; 433 u32 scr, stat; 434 int ret; 435 436 master_saif = mxs_saif_get_master(saif); 437 if (!master_saif) 438 return -EINVAL; 439 440 /* mclk should already be set */ 441 if (!saif->mclk && saif->mclk_in_use) { 442 dev_err(cpu_dai->dev, "set mclk first\n"); 443 return -EINVAL; 444 } 445 446 stat = __raw_readl(saif->base + SAIF_STAT); 447 if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) { 448 dev_err(cpu_dai->dev, "error: busy\n"); 449 return -EBUSY; 450 } 451 452 /* 453 * Set saif clk based on sample rate. 454 * If mclk is used, we also set mclk, if not, saif->mclk is 455 * default 0, means not used. 456 */ 457 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 458 if (ret) { 459 dev_err(cpu_dai->dev, "unable to get proper clk\n"); 460 return ret; 461 } 462 463 if (saif != master_saif) { 464 /* 465 * Set an initial clock rate for the saif internal logic to work 466 * properly. This is important when working in EXTMASTER mode 467 * that uses the other saif's BITCLK&LRCLK but it still needs a 468 * basic clock which should be fast enough for the internal 469 * logic. 470 */ 471 clk_enable(saif->clk); 472 ret = clk_set_rate(saif->clk, 24000000); 473 clk_disable(saif->clk); 474 if (ret) 475 return ret; 476 477 ret = clk_prepare(master_saif->clk); 478 if (ret) 479 return ret; 480 } 481 482 scr = __raw_readl(saif->base + SAIF_CTRL); 483 484 scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 485 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 486 switch (params_format(params)) { 487 case SNDRV_PCM_FORMAT_S16_LE: 488 scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 489 break; 490 case SNDRV_PCM_FORMAT_S20_3LE: 491 scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 492 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 493 break; 494 case SNDRV_PCM_FORMAT_S24_LE: 495 scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 496 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 497 break; 498 default: 499 return -EINVAL; 500 } 501 502 /* Tx/Rx config */ 503 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 504 /* enable TX mode */ 505 scr &= ~BM_SAIF_CTRL_READ_MODE; 506 } else { 507 /* enable RX mode */ 508 scr |= BM_SAIF_CTRL_READ_MODE; 509 } 510 511 __raw_writel(scr, saif->base + SAIF_CTRL); 512 return 0; 513 } 514 515 static int mxs_saif_prepare(struct snd_pcm_substream *substream, 516 struct snd_soc_dai *cpu_dai) 517 { 518 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 519 520 /* enable FIFO error irqs */ 521 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 522 saif->base + SAIF_CTRL + MXS_SET_ADDR); 523 524 return 0; 525 } 526 527 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 528 struct snd_soc_dai *cpu_dai) 529 { 530 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 531 struct mxs_saif *master_saif; 532 u32 delay; 533 int ret; 534 535 master_saif = mxs_saif_get_master(saif); 536 if (!master_saif) 537 return -EINVAL; 538 539 switch (cmd) { 540 case SNDRV_PCM_TRIGGER_START: 541 case SNDRV_PCM_TRIGGER_RESUME: 542 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 543 if (saif->state == MXS_SAIF_STATE_RUNNING) 544 return 0; 545 546 dev_dbg(cpu_dai->dev, "start\n"); 547 548 ret = clk_enable(master_saif->clk); 549 if (ret) { 550 dev_err(saif->dev, "Failed to enable master clock\n"); 551 return ret; 552 } 553 554 /* 555 * If the saif's master is not itself, we also need to enable 556 * itself clk for its internal basic logic to work. 557 */ 558 if (saif != master_saif) { 559 ret = clk_enable(saif->clk); 560 if (ret) { 561 dev_err(saif->dev, "Failed to enable master clock\n"); 562 clk_disable(master_saif->clk); 563 return ret; 564 } 565 566 __raw_writel(BM_SAIF_CTRL_RUN, 567 saif->base + SAIF_CTRL + MXS_SET_ADDR); 568 } 569 570 if (!master_saif->mclk_in_use) 571 __raw_writel(BM_SAIF_CTRL_RUN, 572 master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 573 574 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 575 /* 576 * write data to saif data register to trigger 577 * the transfer. 578 * For 24-bit format the 32-bit FIFO register stores 579 * only one channel, so we need to write twice. 580 * This is also safe for the other non 24-bit formats. 581 */ 582 __raw_writel(0, saif->base + SAIF_DATA); 583 __raw_writel(0, saif->base + SAIF_DATA); 584 } else { 585 /* 586 * read data from saif data register to trigger 587 * the receive. 588 * For 24-bit format the 32-bit FIFO register stores 589 * only one channel, so we need to read twice. 590 * This is also safe for the other non 24-bit formats. 591 */ 592 __raw_readl(saif->base + SAIF_DATA); 593 __raw_readl(saif->base + SAIF_DATA); 594 } 595 596 master_saif->ongoing = 1; 597 saif->state = MXS_SAIF_STATE_RUNNING; 598 599 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 600 __raw_readl(saif->base + SAIF_CTRL), 601 __raw_readl(saif->base + SAIF_STAT)); 602 603 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 604 __raw_readl(master_saif->base + SAIF_CTRL), 605 __raw_readl(master_saif->base + SAIF_STAT)); 606 break; 607 case SNDRV_PCM_TRIGGER_SUSPEND: 608 case SNDRV_PCM_TRIGGER_STOP: 609 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 610 if (saif->state == MXS_SAIF_STATE_STOPPED) 611 return 0; 612 613 dev_dbg(cpu_dai->dev, "stop\n"); 614 615 /* wait a while for the current sample to complete */ 616 delay = USEC_PER_SEC / master_saif->cur_rate; 617 618 if (!master_saif->mclk_in_use) { 619 __raw_writel(BM_SAIF_CTRL_RUN, 620 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 621 udelay(delay); 622 } 623 clk_disable(master_saif->clk); 624 625 if (saif != master_saif) { 626 __raw_writel(BM_SAIF_CTRL_RUN, 627 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 628 udelay(delay); 629 clk_disable(saif->clk); 630 } 631 632 master_saif->ongoing = 0; 633 saif->state = MXS_SAIF_STATE_STOPPED; 634 635 break; 636 default: 637 return -EINVAL; 638 } 639 640 return 0; 641 } 642 643 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 644 #define MXS_SAIF_FORMATS \ 645 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 646 SNDRV_PCM_FMTBIT_S24_LE) 647 648 static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 649 .startup = mxs_saif_startup, 650 .shutdown = mxs_saif_shutdown, 651 .trigger = mxs_saif_trigger, 652 .prepare = mxs_saif_prepare, 653 .hw_params = mxs_saif_hw_params, 654 .set_sysclk = mxs_saif_set_dai_sysclk, 655 .set_fmt = mxs_saif_set_dai_fmt, 656 }; 657 658 static int mxs_saif_dai_probe(struct snd_soc_dai *dai) 659 { 660 struct mxs_saif *saif = dev_get_drvdata(dai->dev); 661 662 snd_soc_dai_set_drvdata(dai, saif); 663 664 return 0; 665 } 666 667 static struct snd_soc_dai_driver mxs_saif_dai = { 668 .name = "mxs-saif", 669 .probe = mxs_saif_dai_probe, 670 .playback = { 671 .channels_min = 2, 672 .channels_max = 2, 673 .rates = MXS_SAIF_RATES, 674 .formats = MXS_SAIF_FORMATS, 675 }, 676 .capture = { 677 .channels_min = 2, 678 .channels_max = 2, 679 .rates = MXS_SAIF_RATES, 680 .formats = MXS_SAIF_FORMATS, 681 }, 682 .ops = &mxs_saif_dai_ops, 683 }; 684 685 static const struct snd_soc_component_driver mxs_saif_component = { 686 .name = "mxs-saif", 687 }; 688 689 static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 690 { 691 struct mxs_saif *saif = dev_id; 692 unsigned int stat; 693 694 stat = __raw_readl(saif->base + SAIF_STAT); 695 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 696 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 697 return IRQ_NONE; 698 699 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 700 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 701 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 702 saif->base + SAIF_STAT + MXS_CLR_ADDR); 703 } 704 705 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 706 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 707 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 708 saif->base + SAIF_STAT + MXS_CLR_ADDR); 709 } 710 711 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 712 __raw_readl(saif->base + SAIF_CTRL), 713 __raw_readl(saif->base + SAIF_STAT)); 714 715 return IRQ_HANDLED; 716 } 717 718 static int mxs_saif_mclk_init(struct platform_device *pdev) 719 { 720 struct mxs_saif *saif = platform_get_drvdata(pdev); 721 struct device_node *np = pdev->dev.of_node; 722 struct clk *clk; 723 int ret; 724 725 clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk", 726 __clk_get_name(saif->clk), 0, 727 saif->base + SAIF_CTRL, 728 BP_SAIF_CTRL_BITCLK_MULT_RATE, 3, 729 0, NULL); 730 if (IS_ERR(clk)) { 731 ret = PTR_ERR(clk); 732 if (ret == -EEXIST) 733 return 0; 734 dev_err(&pdev->dev, "failed to register mclk: %d\n", ret); 735 return PTR_ERR(clk); 736 } 737 738 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); 739 if (ret) 740 return ret; 741 742 return 0; 743 } 744 745 static int mxs_saif_probe(struct platform_device *pdev) 746 { 747 struct device_node *np = pdev->dev.of_node; 748 struct resource *iores; 749 struct mxs_saif *saif; 750 int irq, ret = 0; 751 struct device_node *master; 752 753 if (!np) 754 return -EINVAL; 755 756 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 757 if (!saif) 758 return -ENOMEM; 759 760 ret = of_alias_get_id(np, "saif"); 761 if (ret < 0) 762 return ret; 763 else 764 saif->id = ret; 765 766 if (saif->id >= ARRAY_SIZE(mxs_saif)) { 767 dev_err(&pdev->dev, "get wrong saif id\n"); 768 return -EINVAL; 769 } 770 771 /* 772 * If there is no "fsl,saif-master" phandle, it's a saif 773 * master. Otherwise, it's a slave and its phandle points 774 * to the master. 775 */ 776 master = of_parse_phandle(np, "fsl,saif-master", 0); 777 if (!master) { 778 saif->master_id = saif->id; 779 } else { 780 ret = of_alias_get_id(master, "saif"); 781 if (ret < 0) 782 return ret; 783 else 784 saif->master_id = ret; 785 786 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) { 787 dev_err(&pdev->dev, "get wrong master id\n"); 788 return -EINVAL; 789 } 790 } 791 792 mxs_saif[saif->id] = saif; 793 794 saif->clk = devm_clk_get(&pdev->dev, NULL); 795 if (IS_ERR(saif->clk)) { 796 ret = PTR_ERR(saif->clk); 797 dev_err(&pdev->dev, "Cannot get the clock: %d\n", 798 ret); 799 return ret; 800 } 801 802 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 803 804 saif->base = devm_ioremap_resource(&pdev->dev, iores); 805 if (IS_ERR(saif->base)) 806 return PTR_ERR(saif->base); 807 808 irq = platform_get_irq(pdev, 0); 809 if (irq < 0) { 810 ret = irq; 811 dev_err(&pdev->dev, "failed to get irq resource: %d\n", 812 ret); 813 return ret; 814 } 815 816 saif->dev = &pdev->dev; 817 ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0, 818 dev_name(&pdev->dev), saif); 819 if (ret) { 820 dev_err(&pdev->dev, "failed to request irq\n"); 821 return ret; 822 } 823 824 platform_set_drvdata(pdev, saif); 825 826 /* We only support saif0 being tx and clock master */ 827 if (saif->id == 0) { 828 ret = mxs_saif_mclk_init(pdev); 829 if (ret) 830 dev_warn(&pdev->dev, "failed to init clocks\n"); 831 } 832 833 ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component, 834 &mxs_saif_dai, 1); 835 if (ret) { 836 dev_err(&pdev->dev, "register DAI failed\n"); 837 return ret; 838 } 839 840 ret = mxs_pcm_platform_register(&pdev->dev); 841 if (ret) { 842 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 843 return ret; 844 } 845 846 return 0; 847 } 848 849 static const struct of_device_id mxs_saif_dt_ids[] = { 850 { .compatible = "fsl,imx28-saif", }, 851 { /* sentinel */ } 852 }; 853 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 854 855 static struct platform_driver mxs_saif_driver = { 856 .probe = mxs_saif_probe, 857 858 .driver = { 859 .name = "mxs-saif", 860 .of_match_table = mxs_saif_dt_ids, 861 }, 862 }; 863 864 module_platform_driver(mxs_saif_driver); 865 866 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 867 MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 868 MODULE_LICENSE("GPL"); 869 MODULE_ALIAS("platform:mxs-saif"); 870