1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/clk.h> 25 #include <linux/delay.h> 26 #include <linux/time.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/saif.h> 32 #include <mach/dma.h> 33 #include <asm/mach-types.h> 34 #include <mach/hardware.h> 35 #include <mach/mxs.h> 36 37 #include "mxs-saif.h" 38 39 static struct mxs_saif *mxs_saif[2]; 40 41 /* 42 * SAIF is a little different with other normal SOC DAIs on clock using. 43 * 44 * For MXS, two SAIF modules are instantiated on-chip. 45 * Each SAIF has a set of clock pins and can be operating in master 46 * mode simultaneously if they are connected to different off-chip codecs. 47 * Also, one of the two SAIFs can master or drive the clock pins while the 48 * other SAIF, in slave mode, receives clocking from the master SAIF. 49 * This also means that both SAIFs must operate at the same sample rate. 50 * 51 * We abstract this as each saif has a master, the master could be 52 * himself or other saifs. In the generic saif driver, saif does not need 53 * to know the different clkmux. Saif only needs to know who is his master 54 * and operating his master to generate the proper clock rate for him. 55 * The master id is provided in mach-specific layer according to different 56 * clkmux setting. 57 */ 58 59 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 60 int clk_id, unsigned int freq, int dir) 61 { 62 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 63 64 switch (clk_id) { 65 case MXS_SAIF_MCLK: 66 saif->mclk = freq; 67 break; 68 default: 69 return -EINVAL; 70 } 71 return 0; 72 } 73 74 /* 75 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 76 * is provided by other SAIF, we provide a interface here to get its master 77 * from its master_id. 78 * Note that the master could be himself. 79 */ 80 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 81 { 82 return mxs_saif[saif->master_id]; 83 } 84 85 /* 86 * Set SAIF clock and MCLK 87 */ 88 static int mxs_saif_set_clk(struct mxs_saif *saif, 89 unsigned int mclk, 90 unsigned int rate) 91 { 92 u32 scr; 93 int ret; 94 struct mxs_saif *master_saif; 95 96 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 97 98 /* Set master saif to generate proper clock */ 99 master_saif = mxs_saif_get_master(saif); 100 if (!master_saif) 101 return -EINVAL; 102 103 dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 104 105 /* Checking if can playback and capture simutaneously */ 106 if (master_saif->ongoing && rate != master_saif->cur_rate) { 107 dev_err(saif->dev, 108 "can not change clock, master saif%d(rate %d) is ongoing\n", 109 master_saif->id, master_saif->cur_rate); 110 return -EINVAL; 111 } 112 113 scr = __raw_readl(master_saif->base + SAIF_CTRL); 114 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 115 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 116 117 /* 118 * Set SAIF clock 119 * 120 * The SAIF clock should be either 384*fs or 512*fs. 121 * If MCLK is used, the SAIF clk ratio need to match mclk ratio. 122 * For 32x mclk, set saif clk as 512*fs. 123 * For 48x mclk, set saif clk as 384*fs. 124 * 125 * If MCLK is not used, we just set saif clk to 512*fs. 126 */ 127 clk_prepare_enable(master_saif->clk); 128 129 if (master_saif->mclk_in_use) { 130 if (mclk % 32 == 0) { 131 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 132 ret = clk_set_rate(master_saif->clk, 512 * rate); 133 } else if (mclk % 48 == 0) { 134 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 135 ret = clk_set_rate(master_saif->clk, 384 * rate); 136 } else { 137 /* SAIF MCLK should be either 32x or 48x */ 138 clk_disable_unprepare(master_saif->clk); 139 return -EINVAL; 140 } 141 } else { 142 ret = clk_set_rate(master_saif->clk, 512 * rate); 143 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 144 } 145 146 clk_disable_unprepare(master_saif->clk); 147 148 if (ret) 149 return ret; 150 151 master_saif->cur_rate = rate; 152 153 if (!master_saif->mclk_in_use) { 154 __raw_writel(scr, master_saif->base + SAIF_CTRL); 155 return 0; 156 } 157 158 /* 159 * Program the over-sample rate for MCLK output 160 * 161 * The available MCLK range is 32x, 48x... 512x. The rate 162 * could be from 8kHz to 192kH. 163 */ 164 switch (mclk / rate) { 165 case 32: 166 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 167 break; 168 case 64: 169 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 170 break; 171 case 128: 172 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 173 break; 174 case 256: 175 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 176 break; 177 case 512: 178 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 179 break; 180 case 48: 181 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 182 break; 183 case 96: 184 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 185 break; 186 case 192: 187 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 188 break; 189 case 384: 190 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 191 break; 192 default: 193 return -EINVAL; 194 } 195 196 __raw_writel(scr, master_saif->base + SAIF_CTRL); 197 198 return 0; 199 } 200 201 /* 202 * Put and disable MCLK. 203 */ 204 int mxs_saif_put_mclk(unsigned int saif_id) 205 { 206 struct mxs_saif *saif = mxs_saif[saif_id]; 207 u32 stat; 208 209 if (!saif) 210 return -EINVAL; 211 212 stat = __raw_readl(saif->base + SAIF_STAT); 213 if (stat & BM_SAIF_STAT_BUSY) { 214 dev_err(saif->dev, "error: busy\n"); 215 return -EBUSY; 216 } 217 218 clk_disable_unprepare(saif->clk); 219 220 /* disable MCLK output */ 221 __raw_writel(BM_SAIF_CTRL_CLKGATE, 222 saif->base + SAIF_CTRL + MXS_SET_ADDR); 223 __raw_writel(BM_SAIF_CTRL_RUN, 224 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 225 226 saif->mclk_in_use = 0; 227 return 0; 228 } 229 230 /* 231 * Get MCLK and set clock rate, then enable it 232 * 233 * This interface is used for codecs who are using MCLK provided 234 * by saif. 235 */ 236 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 237 unsigned int rate) 238 { 239 struct mxs_saif *saif = mxs_saif[saif_id]; 240 u32 stat; 241 int ret; 242 struct mxs_saif *master_saif; 243 244 if (!saif) 245 return -EINVAL; 246 247 /* Clear Reset */ 248 __raw_writel(BM_SAIF_CTRL_SFTRST, 249 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 250 251 /* FIXME: need clear clk gate for register r/w */ 252 __raw_writel(BM_SAIF_CTRL_CLKGATE, 253 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 254 255 master_saif = mxs_saif_get_master(saif); 256 if (saif != master_saif) { 257 dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 258 return -EINVAL; 259 } 260 261 stat = __raw_readl(saif->base + SAIF_STAT); 262 if (stat & BM_SAIF_STAT_BUSY) { 263 dev_err(saif->dev, "error: busy\n"); 264 return -EBUSY; 265 } 266 267 saif->mclk_in_use = 1; 268 ret = mxs_saif_set_clk(saif, mclk, rate); 269 if (ret) 270 return ret; 271 272 ret = clk_prepare_enable(saif->clk); 273 if (ret) 274 return ret; 275 276 /* enable MCLK output */ 277 __raw_writel(BM_SAIF_CTRL_RUN, 278 saif->base + SAIF_CTRL + MXS_SET_ADDR); 279 280 return 0; 281 } 282 283 /* 284 * SAIF DAI format configuration. 285 * Should only be called when port is inactive. 286 */ 287 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 288 { 289 u32 scr, stat; 290 u32 scr0; 291 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 292 293 stat = __raw_readl(saif->base + SAIF_STAT); 294 if (stat & BM_SAIF_STAT_BUSY) { 295 dev_err(cpu_dai->dev, "error: busy\n"); 296 return -EBUSY; 297 } 298 299 scr0 = __raw_readl(saif->base + SAIF_CTRL); 300 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 301 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 302 scr = 0; 303 304 /* DAI mode */ 305 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 306 case SND_SOC_DAIFMT_I2S: 307 /* data frame low 1clk before data */ 308 scr |= BM_SAIF_CTRL_DELAY; 309 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 310 break; 311 case SND_SOC_DAIFMT_LEFT_J: 312 /* data frame high with data */ 313 scr &= ~BM_SAIF_CTRL_DELAY; 314 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 315 scr &= ~BM_SAIF_CTRL_JUSTIFY; 316 break; 317 default: 318 return -EINVAL; 319 } 320 321 /* DAI clock inversion */ 322 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 323 case SND_SOC_DAIFMT_IB_IF: 324 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 325 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 326 break; 327 case SND_SOC_DAIFMT_IB_NF: 328 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 329 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 330 break; 331 case SND_SOC_DAIFMT_NB_IF: 332 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 333 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 334 break; 335 case SND_SOC_DAIFMT_NB_NF: 336 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 337 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 338 break; 339 } 340 341 /* 342 * Note: We simply just support master mode since SAIF TX can only 343 * work as master. 344 * Here the master is relative to codec side. 345 * Saif internally could be slave when working on EXTMASTER mode. 346 * We just hide this to machine driver. 347 */ 348 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 349 case SND_SOC_DAIFMT_CBS_CFS: 350 if (saif->id == saif->master_id) 351 scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 352 else 353 scr |= BM_SAIF_CTRL_SLAVE_MODE; 354 355 __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 356 break; 357 default: 358 return -EINVAL; 359 } 360 361 return 0; 362 } 363 364 static int mxs_saif_startup(struct snd_pcm_substream *substream, 365 struct snd_soc_dai *cpu_dai) 366 { 367 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 368 snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param); 369 370 /* clear error status to 0 for each re-open */ 371 saif->fifo_underrun = 0; 372 saif->fifo_overrun = 0; 373 374 /* Clear Reset for normal operations */ 375 __raw_writel(BM_SAIF_CTRL_SFTRST, 376 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 377 378 /* clear clock gate */ 379 __raw_writel(BM_SAIF_CTRL_CLKGATE, 380 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 381 382 return 0; 383 } 384 385 /* 386 * Should only be called when port is inactive. 387 * although can be called multiple times by upper layers. 388 */ 389 static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 390 struct snd_pcm_hw_params *params, 391 struct snd_soc_dai *cpu_dai) 392 { 393 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 394 u32 scr, stat; 395 int ret; 396 397 /* mclk should already be set */ 398 if (!saif->mclk && saif->mclk_in_use) { 399 dev_err(cpu_dai->dev, "set mclk first\n"); 400 return -EINVAL; 401 } 402 403 stat = __raw_readl(saif->base + SAIF_STAT); 404 if (stat & BM_SAIF_STAT_BUSY) { 405 dev_err(cpu_dai->dev, "error: busy\n"); 406 return -EBUSY; 407 } 408 409 /* 410 * Set saif clk based on sample rate. 411 * If mclk is used, we also set mclk, if not, saif->mclk is 412 * default 0, means not used. 413 */ 414 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 415 if (ret) { 416 dev_err(cpu_dai->dev, "unable to get proper clk\n"); 417 return ret; 418 } 419 420 scr = __raw_readl(saif->base + SAIF_CTRL); 421 422 scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 423 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 424 switch (params_format(params)) { 425 case SNDRV_PCM_FORMAT_S16_LE: 426 scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 427 break; 428 case SNDRV_PCM_FORMAT_S20_3LE: 429 scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 430 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 431 break; 432 case SNDRV_PCM_FORMAT_S24_LE: 433 scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 434 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 435 break; 436 default: 437 return -EINVAL; 438 } 439 440 /* Tx/Rx config */ 441 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 442 /* enable TX mode */ 443 scr &= ~BM_SAIF_CTRL_READ_MODE; 444 } else { 445 /* enable RX mode */ 446 scr |= BM_SAIF_CTRL_READ_MODE; 447 } 448 449 __raw_writel(scr, saif->base + SAIF_CTRL); 450 return 0; 451 } 452 453 static int mxs_saif_prepare(struct snd_pcm_substream *substream, 454 struct snd_soc_dai *cpu_dai) 455 { 456 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 457 458 /* enable FIFO error irqs */ 459 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 460 saif->base + SAIF_CTRL + MXS_SET_ADDR); 461 462 return 0; 463 } 464 465 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 466 struct snd_soc_dai *cpu_dai) 467 { 468 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 469 struct mxs_saif *master_saif; 470 u32 delay; 471 472 master_saif = mxs_saif_get_master(saif); 473 if (!master_saif) 474 return -EINVAL; 475 476 switch (cmd) { 477 case SNDRV_PCM_TRIGGER_START: 478 case SNDRV_PCM_TRIGGER_RESUME: 479 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 480 dev_dbg(cpu_dai->dev, "start\n"); 481 482 clk_enable(master_saif->clk); 483 if (!master_saif->mclk_in_use) 484 __raw_writel(BM_SAIF_CTRL_RUN, 485 master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 486 487 /* 488 * If the saif's master is not himself, we also need to enable 489 * itself clk for its internal basic logic to work. 490 */ 491 if (saif != master_saif) { 492 clk_enable(saif->clk); 493 __raw_writel(BM_SAIF_CTRL_RUN, 494 saif->base + SAIF_CTRL + MXS_SET_ADDR); 495 } 496 497 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 498 /* 499 * write a data to saif data register to trigger 500 * the transfer 501 */ 502 __raw_writel(0, saif->base + SAIF_DATA); 503 } else { 504 /* 505 * read a data from saif data register to trigger 506 * the receive 507 */ 508 __raw_readl(saif->base + SAIF_DATA); 509 } 510 511 master_saif->ongoing = 1; 512 513 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 514 __raw_readl(saif->base + SAIF_CTRL), 515 __raw_readl(saif->base + SAIF_STAT)); 516 517 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 518 __raw_readl(master_saif->base + SAIF_CTRL), 519 __raw_readl(master_saif->base + SAIF_STAT)); 520 break; 521 case SNDRV_PCM_TRIGGER_SUSPEND: 522 case SNDRV_PCM_TRIGGER_STOP: 523 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 524 dev_dbg(cpu_dai->dev, "stop\n"); 525 526 /* wait a while for the current sample to complete */ 527 delay = USEC_PER_SEC / master_saif->cur_rate; 528 529 if (!master_saif->mclk_in_use) { 530 __raw_writel(BM_SAIF_CTRL_RUN, 531 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 532 udelay(delay); 533 } 534 clk_disable(master_saif->clk); 535 536 if (saif != master_saif) { 537 __raw_writel(BM_SAIF_CTRL_RUN, 538 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 539 udelay(delay); 540 clk_disable(saif->clk); 541 } 542 543 master_saif->ongoing = 0; 544 545 break; 546 default: 547 return -EINVAL; 548 } 549 550 return 0; 551 } 552 553 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 554 #define MXS_SAIF_FORMATS \ 555 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 556 SNDRV_PCM_FMTBIT_S24_LE) 557 558 static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 559 .startup = mxs_saif_startup, 560 .trigger = mxs_saif_trigger, 561 .prepare = mxs_saif_prepare, 562 .hw_params = mxs_saif_hw_params, 563 .set_sysclk = mxs_saif_set_dai_sysclk, 564 .set_fmt = mxs_saif_set_dai_fmt, 565 }; 566 567 static int mxs_saif_dai_probe(struct snd_soc_dai *dai) 568 { 569 struct mxs_saif *saif = dev_get_drvdata(dai->dev); 570 571 snd_soc_dai_set_drvdata(dai, saif); 572 573 return 0; 574 } 575 576 static struct snd_soc_dai_driver mxs_saif_dai = { 577 .name = "mxs-saif", 578 .probe = mxs_saif_dai_probe, 579 .playback = { 580 .channels_min = 2, 581 .channels_max = 2, 582 .rates = MXS_SAIF_RATES, 583 .formats = MXS_SAIF_FORMATS, 584 }, 585 .capture = { 586 .channels_min = 2, 587 .channels_max = 2, 588 .rates = MXS_SAIF_RATES, 589 .formats = MXS_SAIF_FORMATS, 590 }, 591 .ops = &mxs_saif_dai_ops, 592 }; 593 594 static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 595 { 596 struct mxs_saif *saif = dev_id; 597 unsigned int stat; 598 599 stat = __raw_readl(saif->base + SAIF_STAT); 600 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 601 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 602 return IRQ_NONE; 603 604 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 605 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 606 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 607 saif->base + SAIF_STAT + MXS_CLR_ADDR); 608 } 609 610 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 611 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 612 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 613 saif->base + SAIF_STAT + MXS_CLR_ADDR); 614 } 615 616 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 617 __raw_readl(saif->base + SAIF_CTRL), 618 __raw_readl(saif->base + SAIF_STAT)); 619 620 return IRQ_HANDLED; 621 } 622 623 static int mxs_saif_probe(struct platform_device *pdev) 624 { 625 struct resource *iores, *dmares; 626 struct mxs_saif *saif; 627 struct mxs_saif_platform_data *pdata; 628 int ret = 0; 629 630 if (pdev->id >= ARRAY_SIZE(mxs_saif)) 631 return -EINVAL; 632 633 saif = kzalloc(sizeof(*saif), GFP_KERNEL); 634 if (!saif) 635 return -ENOMEM; 636 637 mxs_saif[pdev->id] = saif; 638 saif->id = pdev->id; 639 640 pdata = pdev->dev.platform_data; 641 if (pdata && !pdata->master_mode) { 642 saif->master_id = pdata->master_id; 643 if (saif->master_id < 0 || 644 saif->master_id >= ARRAY_SIZE(mxs_saif) || 645 saif->master_id == saif->id) { 646 dev_err(&pdev->dev, "get wrong master id\n"); 647 return -EINVAL; 648 } 649 } else { 650 saif->master_id = saif->id; 651 } 652 653 saif->clk = clk_get(&pdev->dev, NULL); 654 if (IS_ERR(saif->clk)) { 655 ret = PTR_ERR(saif->clk); 656 dev_err(&pdev->dev, "Cannot get the clock: %d\n", 657 ret); 658 goto failed_clk; 659 } 660 661 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 662 if (!iores) { 663 ret = -ENODEV; 664 dev_err(&pdev->dev, "failed to get io resource: %d\n", 665 ret); 666 goto failed_get_resource; 667 } 668 669 if (!request_mem_region(iores->start, resource_size(iores), 670 "mxs-saif")) { 671 dev_err(&pdev->dev, "request_mem_region failed\n"); 672 ret = -EBUSY; 673 goto failed_get_resource; 674 } 675 676 saif->base = ioremap(iores->start, resource_size(iores)); 677 if (!saif->base) { 678 dev_err(&pdev->dev, "ioremap failed\n"); 679 ret = -ENODEV; 680 goto failed_ioremap; 681 } 682 683 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 684 if (!dmares) { 685 ret = -ENODEV; 686 dev_err(&pdev->dev, "failed to get dma resource: %d\n", 687 ret); 688 goto failed_ioremap; 689 } 690 saif->dma_param.chan_num = dmares->start; 691 692 saif->irq = platform_get_irq(pdev, 0); 693 if (saif->irq < 0) { 694 ret = saif->irq; 695 dev_err(&pdev->dev, "failed to get irq resource: %d\n", 696 ret); 697 goto failed_get_irq1; 698 } 699 700 saif->dev = &pdev->dev; 701 ret = request_irq(saif->irq, mxs_saif_irq, 0, "mxs-saif", saif); 702 if (ret) { 703 dev_err(&pdev->dev, "failed to request irq\n"); 704 goto failed_get_irq1; 705 } 706 707 saif->dma_param.chan_irq = platform_get_irq(pdev, 1); 708 if (saif->dma_param.chan_irq < 0) { 709 ret = saif->dma_param.chan_irq; 710 dev_err(&pdev->dev, "failed to get dma irq resource: %d\n", 711 ret); 712 goto failed_get_irq2; 713 } 714 715 platform_set_drvdata(pdev, saif); 716 717 ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai); 718 if (ret) { 719 dev_err(&pdev->dev, "register DAI failed\n"); 720 goto failed_register; 721 } 722 723 saif->soc_platform_pdev = platform_device_alloc( 724 "mxs-pcm-audio", pdev->id); 725 if (!saif->soc_platform_pdev) { 726 ret = -ENOMEM; 727 goto failed_pdev_alloc; 728 } 729 730 platform_set_drvdata(saif->soc_platform_pdev, saif); 731 ret = platform_device_add(saif->soc_platform_pdev); 732 if (ret) { 733 dev_err(&pdev->dev, "failed to add soc platform device\n"); 734 goto failed_pdev_add; 735 } 736 737 return 0; 738 739 failed_pdev_add: 740 platform_device_put(saif->soc_platform_pdev); 741 failed_pdev_alloc: 742 snd_soc_unregister_dai(&pdev->dev); 743 failed_register: 744 failed_get_irq2: 745 free_irq(saif->irq, saif); 746 failed_get_irq1: 747 iounmap(saif->base); 748 failed_ioremap: 749 release_mem_region(iores->start, resource_size(iores)); 750 failed_get_resource: 751 clk_put(saif->clk); 752 failed_clk: 753 kfree(saif); 754 755 return ret; 756 } 757 758 static int __devexit mxs_saif_remove(struct platform_device *pdev) 759 { 760 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 761 struct mxs_saif *saif = platform_get_drvdata(pdev); 762 763 platform_device_unregister(saif->soc_platform_pdev); 764 765 snd_soc_unregister_dai(&pdev->dev); 766 767 iounmap(saif->base); 768 release_mem_region(res->start, resource_size(res)); 769 free_irq(saif->irq, saif); 770 771 clk_put(saif->clk); 772 kfree(saif); 773 774 return 0; 775 } 776 777 static struct platform_driver mxs_saif_driver = { 778 .probe = mxs_saif_probe, 779 .remove = __devexit_p(mxs_saif_remove), 780 781 .driver = { 782 .name = "mxs-saif", 783 .owner = THIS_MODULE, 784 }, 785 }; 786 787 module_platform_driver(mxs_saif_driver); 788 789 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 790 MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 791 MODULE_LICENSE("GPL"); 792