12a24f2ceSDong Aisheng /* 22a24f2ceSDong Aisheng * Copyright 2011 Freescale Semiconductor, Inc. 32a24f2ceSDong Aisheng * 42a24f2ceSDong Aisheng * This program is free software; you can redistribute it and/or modify 52a24f2ceSDong Aisheng * it under the terms of the GNU General Public License as published by 62a24f2ceSDong Aisheng * the Free Software Foundation; either version 2 of the License, or 72a24f2ceSDong Aisheng * (at your option) any later version. 82a24f2ceSDong Aisheng * 92a24f2ceSDong Aisheng * This program is distributed in the hope that it will be useful, 102a24f2ceSDong Aisheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 112a24f2ceSDong Aisheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122a24f2ceSDong Aisheng * GNU General Public License for more details. 132a24f2ceSDong Aisheng * 142a24f2ceSDong Aisheng * You should have received a copy of the GNU General Public License along 152a24f2ceSDong Aisheng * with this program; if not, write to the Free Software Foundation, Inc., 162a24f2ceSDong Aisheng * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 172a24f2ceSDong Aisheng */ 182a24f2ceSDong Aisheng 192a24f2ceSDong Aisheng #include <linux/module.h> 202a24f2ceSDong Aisheng #include <linux/init.h> 2108641c7cSShawn Guo #include <linux/of.h> 2208641c7cSShawn Guo #include <linux/of_device.h> 232a24f2ceSDong Aisheng #include <linux/platform_device.h> 242a24f2ceSDong Aisheng #include <linux/slab.h> 252a24f2ceSDong Aisheng #include <linux/dma-mapping.h> 262a24f2ceSDong Aisheng #include <linux/clk.h> 272a24f2ceSDong Aisheng #include <linux/delay.h> 2876067540SDong Aisheng #include <linux/time.h> 2939468604SHuang Shijie #include <linux/fsl/mxs-dma.h> 30f755865fSShawn Guo #include <linux/pinctrl/consumer.h> 312a24f2ceSDong Aisheng #include <sound/core.h> 322a24f2ceSDong Aisheng #include <sound/pcm.h> 332a24f2ceSDong Aisheng #include <sound/pcm_params.h> 342a24f2ceSDong Aisheng #include <sound/soc.h> 3576067540SDong Aisheng #include <sound/saif.h> 362a24f2ceSDong Aisheng #include <asm/mach-types.h> 372a24f2ceSDong Aisheng #include <mach/hardware.h> 382a24f2ceSDong Aisheng #include <mach/mxs.h> 392a24f2ceSDong Aisheng 402a24f2ceSDong Aisheng #include "mxs-saif.h" 412a24f2ceSDong Aisheng 422a24f2ceSDong Aisheng static struct mxs_saif *mxs_saif[2]; 432a24f2ceSDong Aisheng 4476067540SDong Aisheng /* 4576067540SDong Aisheng * SAIF is a little different with other normal SOC DAIs on clock using. 4676067540SDong Aisheng * 4776067540SDong Aisheng * For MXS, two SAIF modules are instantiated on-chip. 4876067540SDong Aisheng * Each SAIF has a set of clock pins and can be operating in master 4976067540SDong Aisheng * mode simultaneously if they are connected to different off-chip codecs. 5076067540SDong Aisheng * Also, one of the two SAIFs can master or drive the clock pins while the 5176067540SDong Aisheng * other SAIF, in slave mode, receives clocking from the master SAIF. 5276067540SDong Aisheng * This also means that both SAIFs must operate at the same sample rate. 5376067540SDong Aisheng * 5476067540SDong Aisheng * We abstract this as each saif has a master, the master could be 5576067540SDong Aisheng * himself or other saifs. In the generic saif driver, saif does not need 5676067540SDong Aisheng * to know the different clkmux. Saif only needs to know who is his master 5776067540SDong Aisheng * and operating his master to generate the proper clock rate for him. 5876067540SDong Aisheng * The master id is provided in mach-specific layer according to different 5976067540SDong Aisheng * clkmux setting. 6076067540SDong Aisheng */ 6176067540SDong Aisheng 622a24f2ceSDong Aisheng static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 632a24f2ceSDong Aisheng int clk_id, unsigned int freq, int dir) 642a24f2ceSDong Aisheng { 652a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 662a24f2ceSDong Aisheng 672a24f2ceSDong Aisheng switch (clk_id) { 682a24f2ceSDong Aisheng case MXS_SAIF_MCLK: 692a24f2ceSDong Aisheng saif->mclk = freq; 702a24f2ceSDong Aisheng break; 712a24f2ceSDong Aisheng default: 722a24f2ceSDong Aisheng return -EINVAL; 732a24f2ceSDong Aisheng } 742a24f2ceSDong Aisheng return 0; 752a24f2ceSDong Aisheng } 762a24f2ceSDong Aisheng 772a24f2ceSDong Aisheng /* 7876067540SDong Aisheng * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 7976067540SDong Aisheng * is provided by other SAIF, we provide a interface here to get its master 8076067540SDong Aisheng * from its master_id. 8176067540SDong Aisheng * Note that the master could be himself. 8276067540SDong Aisheng */ 8376067540SDong Aisheng static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 8476067540SDong Aisheng { 8576067540SDong Aisheng return mxs_saif[saif->master_id]; 8676067540SDong Aisheng } 8776067540SDong Aisheng 8876067540SDong Aisheng /* 892a24f2ceSDong Aisheng * Set SAIF clock and MCLK 902a24f2ceSDong Aisheng */ 912a24f2ceSDong Aisheng static int mxs_saif_set_clk(struct mxs_saif *saif, 922a24f2ceSDong Aisheng unsigned int mclk, 932a24f2ceSDong Aisheng unsigned int rate) 942a24f2ceSDong Aisheng { 952a24f2ceSDong Aisheng u32 scr; 962a24f2ceSDong Aisheng int ret; 9776067540SDong Aisheng struct mxs_saif *master_saif; 982a24f2ceSDong Aisheng 9976067540SDong Aisheng dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 10076067540SDong Aisheng 10176067540SDong Aisheng /* Set master saif to generate proper clock */ 10276067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 10376067540SDong Aisheng if (!master_saif) 10476067540SDong Aisheng return -EINVAL; 10576067540SDong Aisheng 10676067540SDong Aisheng dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 10776067540SDong Aisheng 10876067540SDong Aisheng /* Checking if can playback and capture simutaneously */ 10976067540SDong Aisheng if (master_saif->ongoing && rate != master_saif->cur_rate) { 11076067540SDong Aisheng dev_err(saif->dev, 11176067540SDong Aisheng "can not change clock, master saif%d(rate %d) is ongoing\n", 11276067540SDong Aisheng master_saif->id, master_saif->cur_rate); 11376067540SDong Aisheng return -EINVAL; 11476067540SDong Aisheng } 11576067540SDong Aisheng 11676067540SDong Aisheng scr = __raw_readl(master_saif->base + SAIF_CTRL); 1172a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 1182a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 1192a24f2ceSDong Aisheng 1202a24f2ceSDong Aisheng /* 1212a24f2ceSDong Aisheng * Set SAIF clock 1222a24f2ceSDong Aisheng * 1232a24f2ceSDong Aisheng * The SAIF clock should be either 384*fs or 512*fs. 1242a24f2ceSDong Aisheng * If MCLK is used, the SAIF clk ratio need to match mclk ratio. 1252a24f2ceSDong Aisheng * For 32x mclk, set saif clk as 512*fs. 1262a24f2ceSDong Aisheng * For 48x mclk, set saif clk as 384*fs. 1272a24f2ceSDong Aisheng * 1282a24f2ceSDong Aisheng * If MCLK is not used, we just set saif clk to 512*fs. 1292a24f2ceSDong Aisheng */ 1306b35f924SFabio Estevam clk_prepare_enable(master_saif->clk); 1316b35f924SFabio Estevam 13276067540SDong Aisheng if (master_saif->mclk_in_use) { 1332a24f2ceSDong Aisheng if (mclk % 32 == 0) { 1342a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 13576067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 512 * rate); 1362a24f2ceSDong Aisheng } else if (mclk % 48 == 0) { 1372a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 13876067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 384 * rate); 1392a24f2ceSDong Aisheng } else { 1402a24f2ceSDong Aisheng /* SAIF MCLK should be either 32x or 48x */ 1416b35f924SFabio Estevam clk_disable_unprepare(master_saif->clk); 1422a24f2ceSDong Aisheng return -EINVAL; 1432a24f2ceSDong Aisheng } 1442a24f2ceSDong Aisheng } else { 14576067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 512 * rate); 1462a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 1472a24f2ceSDong Aisheng } 1482a24f2ceSDong Aisheng 1496b35f924SFabio Estevam clk_disable_unprepare(master_saif->clk); 1506b35f924SFabio Estevam 1512a24f2ceSDong Aisheng if (ret) 1522a24f2ceSDong Aisheng return ret; 1532a24f2ceSDong Aisheng 15476067540SDong Aisheng master_saif->cur_rate = rate; 15576067540SDong Aisheng 15676067540SDong Aisheng if (!master_saif->mclk_in_use) { 15776067540SDong Aisheng __raw_writel(scr, master_saif->base + SAIF_CTRL); 1582a24f2ceSDong Aisheng return 0; 1592a24f2ceSDong Aisheng } 1602a24f2ceSDong Aisheng 1612a24f2ceSDong Aisheng /* 1622a24f2ceSDong Aisheng * Program the over-sample rate for MCLK output 1632a24f2ceSDong Aisheng * 1642a24f2ceSDong Aisheng * The available MCLK range is 32x, 48x... 512x. The rate 1652a24f2ceSDong Aisheng * could be from 8kHz to 192kH. 1662a24f2ceSDong Aisheng */ 1672a24f2ceSDong Aisheng switch (mclk / rate) { 1682a24f2ceSDong Aisheng case 32: 1692a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 1702a24f2ceSDong Aisheng break; 1712a24f2ceSDong Aisheng case 64: 1722a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 1732a24f2ceSDong Aisheng break; 1742a24f2ceSDong Aisheng case 128: 1752a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 1762a24f2ceSDong Aisheng break; 1772a24f2ceSDong Aisheng case 256: 1782a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 1792a24f2ceSDong Aisheng break; 1802a24f2ceSDong Aisheng case 512: 1812a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 1822a24f2ceSDong Aisheng break; 1832a24f2ceSDong Aisheng case 48: 1842a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 1852a24f2ceSDong Aisheng break; 1862a24f2ceSDong Aisheng case 96: 1872a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 1882a24f2ceSDong Aisheng break; 1892a24f2ceSDong Aisheng case 192: 1902a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 1912a24f2ceSDong Aisheng break; 1922a24f2ceSDong Aisheng case 384: 1932a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 1942a24f2ceSDong Aisheng break; 1952a24f2ceSDong Aisheng default: 1962a24f2ceSDong Aisheng return -EINVAL; 1972a24f2ceSDong Aisheng } 1982a24f2ceSDong Aisheng 19976067540SDong Aisheng __raw_writel(scr, master_saif->base + SAIF_CTRL); 2002a24f2ceSDong Aisheng 2012a24f2ceSDong Aisheng return 0; 2022a24f2ceSDong Aisheng } 2032a24f2ceSDong Aisheng 2042a24f2ceSDong Aisheng /* 2052a24f2ceSDong Aisheng * Put and disable MCLK. 2062a24f2ceSDong Aisheng */ 2072a24f2ceSDong Aisheng int mxs_saif_put_mclk(unsigned int saif_id) 2082a24f2ceSDong Aisheng { 2092a24f2ceSDong Aisheng struct mxs_saif *saif = mxs_saif[saif_id]; 2102a24f2ceSDong Aisheng u32 stat; 2112a24f2ceSDong Aisheng 2122a24f2ceSDong Aisheng if (!saif) 2132a24f2ceSDong Aisheng return -EINVAL; 2142a24f2ceSDong Aisheng 2152a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2162a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2172a24f2ceSDong Aisheng dev_err(saif->dev, "error: busy\n"); 2182a24f2ceSDong Aisheng return -EBUSY; 2192a24f2ceSDong Aisheng } 2202a24f2ceSDong Aisheng 22167939b22SShawn Guo clk_disable_unprepare(saif->clk); 2222a24f2ceSDong Aisheng 2232a24f2ceSDong Aisheng /* disable MCLK output */ 2242a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 2252a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 2262a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 2272a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 2282a24f2ceSDong Aisheng 2292a24f2ceSDong Aisheng saif->mclk_in_use = 0; 2302a24f2ceSDong Aisheng return 0; 2312a24f2ceSDong Aisheng } 232cf7d0f09SLothar Waßmann EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); 2332a24f2ceSDong Aisheng 2342a24f2ceSDong Aisheng /* 2352a24f2ceSDong Aisheng * Get MCLK and set clock rate, then enable it 2362a24f2ceSDong Aisheng * 2372a24f2ceSDong Aisheng * This interface is used for codecs who are using MCLK provided 2382a24f2ceSDong Aisheng * by saif. 2392a24f2ceSDong Aisheng */ 2402a24f2ceSDong Aisheng int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 2412a24f2ceSDong Aisheng unsigned int rate) 2422a24f2ceSDong Aisheng { 2432a24f2ceSDong Aisheng struct mxs_saif *saif = mxs_saif[saif_id]; 2442a24f2ceSDong Aisheng u32 stat; 2452a24f2ceSDong Aisheng int ret; 24676067540SDong Aisheng struct mxs_saif *master_saif; 2472a24f2ceSDong Aisheng 2482a24f2ceSDong Aisheng if (!saif) 2492a24f2ceSDong Aisheng return -EINVAL; 2502a24f2ceSDong Aisheng 251bbe8ff5eSDong Aisheng /* Clear Reset */ 252bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_SFTRST, 253bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 254bbe8ff5eSDong Aisheng 255bbe8ff5eSDong Aisheng /* FIXME: need clear clk gate for register r/w */ 256bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 257bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 258bbe8ff5eSDong Aisheng 25976067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 26076067540SDong Aisheng if (saif != master_saif) { 26176067540SDong Aisheng dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 26276067540SDong Aisheng return -EINVAL; 26376067540SDong Aisheng } 26476067540SDong Aisheng 2652a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2662a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2672a24f2ceSDong Aisheng dev_err(saif->dev, "error: busy\n"); 2682a24f2ceSDong Aisheng return -EBUSY; 2692a24f2ceSDong Aisheng } 2702a24f2ceSDong Aisheng 2712a24f2ceSDong Aisheng saif->mclk_in_use = 1; 2722a24f2ceSDong Aisheng ret = mxs_saif_set_clk(saif, mclk, rate); 2732a24f2ceSDong Aisheng if (ret) 2742a24f2ceSDong Aisheng return ret; 2752a24f2ceSDong Aisheng 27667939b22SShawn Guo ret = clk_prepare_enable(saif->clk); 2772a24f2ceSDong Aisheng if (ret) 2782a24f2ceSDong Aisheng return ret; 2792a24f2ceSDong Aisheng 2802a24f2ceSDong Aisheng /* enable MCLK output */ 2812a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 2822a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 2832a24f2ceSDong Aisheng 2842a24f2ceSDong Aisheng return 0; 2852a24f2ceSDong Aisheng } 286cf7d0f09SLothar Waßmann EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); 2872a24f2ceSDong Aisheng 2882a24f2ceSDong Aisheng /* 2892a24f2ceSDong Aisheng * SAIF DAI format configuration. 2902a24f2ceSDong Aisheng * Should only be called when port is inactive. 2912a24f2ceSDong Aisheng */ 2922a24f2ceSDong Aisheng static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 2932a24f2ceSDong Aisheng { 2942a24f2ceSDong Aisheng u32 scr, stat; 2952a24f2ceSDong Aisheng u32 scr0; 2962a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 2972a24f2ceSDong Aisheng 2982a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2992a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 3002a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "error: busy\n"); 3012a24f2ceSDong Aisheng return -EBUSY; 3022a24f2ceSDong Aisheng } 3032a24f2ceSDong Aisheng 3042a24f2ceSDong Aisheng scr0 = __raw_readl(saif->base + SAIF_CTRL); 3052a24f2ceSDong Aisheng scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 3062a24f2ceSDong Aisheng & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 3072a24f2ceSDong Aisheng scr = 0; 3082a24f2ceSDong Aisheng 3092a24f2ceSDong Aisheng /* DAI mode */ 3102a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3112a24f2ceSDong Aisheng case SND_SOC_DAIFMT_I2S: 3122a24f2ceSDong Aisheng /* data frame low 1clk before data */ 3132a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_DELAY; 3142a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3152a24f2ceSDong Aisheng break; 3162a24f2ceSDong Aisheng case SND_SOC_DAIFMT_LEFT_J: 3172a24f2ceSDong Aisheng /* data frame high with data */ 3182a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_DELAY; 3192a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3202a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_JUSTIFY; 3212a24f2ceSDong Aisheng break; 3222a24f2ceSDong Aisheng default: 3232a24f2ceSDong Aisheng return -EINVAL; 3242a24f2ceSDong Aisheng } 3252a24f2ceSDong Aisheng 3262a24f2ceSDong Aisheng /* DAI clock inversion */ 3272a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3282a24f2ceSDong Aisheng case SND_SOC_DAIFMT_IB_IF: 3292a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_EDGE; 3302a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 3312a24f2ceSDong Aisheng break; 3322a24f2ceSDong Aisheng case SND_SOC_DAIFMT_IB_NF: 3332a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_EDGE; 3342a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3352a24f2ceSDong Aisheng break; 3362a24f2ceSDong Aisheng case SND_SOC_DAIFMT_NB_IF: 3372a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 3382a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 3392a24f2ceSDong Aisheng break; 3402a24f2ceSDong Aisheng case SND_SOC_DAIFMT_NB_NF: 3412a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 3422a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3432a24f2ceSDong Aisheng break; 3442a24f2ceSDong Aisheng } 3452a24f2ceSDong Aisheng 3462a24f2ceSDong Aisheng /* 3472a24f2ceSDong Aisheng * Note: We simply just support master mode since SAIF TX can only 3482a24f2ceSDong Aisheng * work as master. 34976067540SDong Aisheng * Here the master is relative to codec side. 35076067540SDong Aisheng * Saif internally could be slave when working on EXTMASTER mode. 35176067540SDong Aisheng * We just hide this to machine driver. 3522a24f2ceSDong Aisheng */ 3532a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3542a24f2ceSDong Aisheng case SND_SOC_DAIFMT_CBS_CFS: 35576067540SDong Aisheng if (saif->id == saif->master_id) 3562a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 35776067540SDong Aisheng else 35876067540SDong Aisheng scr |= BM_SAIF_CTRL_SLAVE_MODE; 35976067540SDong Aisheng 3602a24f2ceSDong Aisheng __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 3612a24f2ceSDong Aisheng break; 3622a24f2ceSDong Aisheng default: 3632a24f2ceSDong Aisheng return -EINVAL; 3642a24f2ceSDong Aisheng } 3652a24f2ceSDong Aisheng 3662a24f2ceSDong Aisheng return 0; 3672a24f2ceSDong Aisheng } 3682a24f2ceSDong Aisheng 3692a24f2ceSDong Aisheng static int mxs_saif_startup(struct snd_pcm_substream *substream, 3702a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 3712a24f2ceSDong Aisheng { 3722a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 3732a24f2ceSDong Aisheng snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param); 3742a24f2ceSDong Aisheng 3752a24f2ceSDong Aisheng /* clear error status to 0 for each re-open */ 3762a24f2ceSDong Aisheng saif->fifo_underrun = 0; 3772a24f2ceSDong Aisheng saif->fifo_overrun = 0; 3782a24f2ceSDong Aisheng 3792a24f2ceSDong Aisheng /* Clear Reset for normal operations */ 3802a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_SFTRST, 3812a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 3822a24f2ceSDong Aisheng 383bbe8ff5eSDong Aisheng /* clear clock gate */ 384bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 385bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 386bbe8ff5eSDong Aisheng 3872a24f2ceSDong Aisheng return 0; 3882a24f2ceSDong Aisheng } 3892a24f2ceSDong Aisheng 3902a24f2ceSDong Aisheng /* 3912a24f2ceSDong Aisheng * Should only be called when port is inactive. 3922a24f2ceSDong Aisheng * although can be called multiple times by upper layers. 3932a24f2ceSDong Aisheng */ 3942a24f2ceSDong Aisheng static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 3952a24f2ceSDong Aisheng struct snd_pcm_hw_params *params, 3962a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 3972a24f2ceSDong Aisheng { 3982a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 399c2e1d907SDong Aisheng struct mxs_saif *master_saif; 4002a24f2ceSDong Aisheng u32 scr, stat; 4012a24f2ceSDong Aisheng int ret; 4022a24f2ceSDong Aisheng 403c2e1d907SDong Aisheng master_saif = mxs_saif_get_master(saif); 404c2e1d907SDong Aisheng if (!master_saif) 405c2e1d907SDong Aisheng return -EINVAL; 406c2e1d907SDong Aisheng 4072a24f2ceSDong Aisheng /* mclk should already be set */ 4082a24f2ceSDong Aisheng if (!saif->mclk && saif->mclk_in_use) { 4092a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "set mclk first\n"); 4102a24f2ceSDong Aisheng return -EINVAL; 4112a24f2ceSDong Aisheng } 4122a24f2ceSDong Aisheng 4132a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 4142a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 4152a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "error: busy\n"); 4162a24f2ceSDong Aisheng return -EBUSY; 4172a24f2ceSDong Aisheng } 4182a24f2ceSDong Aisheng 4192a24f2ceSDong Aisheng /* 4202a24f2ceSDong Aisheng * Set saif clk based on sample rate. 4212a24f2ceSDong Aisheng * If mclk is used, we also set mclk, if not, saif->mclk is 4222a24f2ceSDong Aisheng * default 0, means not used. 4232a24f2ceSDong Aisheng */ 4242a24f2ceSDong Aisheng ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 4252a24f2ceSDong Aisheng if (ret) { 4262a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "unable to get proper clk\n"); 4272a24f2ceSDong Aisheng return ret; 4282a24f2ceSDong Aisheng } 4292a24f2ceSDong Aisheng 430c2e1d907SDong Aisheng /* prepare clk in hw_param, enable in trigger */ 431c2e1d907SDong Aisheng clk_prepare(saif->clk); 432d0ba4c01SDong Aisheng if (saif != master_saif) { 433d0ba4c01SDong Aisheng /* 434d0ba4c01SDong Aisheng * Set an initial clock rate for the saif internal logic to work 435d0ba4c01SDong Aisheng * properly. This is important when working in EXTMASTER mode 436d0ba4c01SDong Aisheng * that uses the other saif's BITCLK&LRCLK but it still needs a 437d0ba4c01SDong Aisheng * basic clock which should be fast enough for the internal 438d0ba4c01SDong Aisheng * logic. 439d0ba4c01SDong Aisheng */ 440d0ba4c01SDong Aisheng clk_enable(saif->clk); 441d0ba4c01SDong Aisheng ret = clk_set_rate(saif->clk, 24000000); 442d0ba4c01SDong Aisheng clk_disable(saif->clk); 443d0ba4c01SDong Aisheng if (ret) 444d0ba4c01SDong Aisheng return ret; 445d0ba4c01SDong Aisheng 446c2e1d907SDong Aisheng clk_prepare(master_saif->clk); 447d0ba4c01SDong Aisheng } 448c2e1d907SDong Aisheng 4492a24f2ceSDong Aisheng scr = __raw_readl(saif->base + SAIF_CTRL); 4502a24f2ceSDong Aisheng 4512a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 4522a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4532a24f2ceSDong Aisheng switch (params_format(params)) { 4542a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S16_LE: 4552a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 4562a24f2ceSDong Aisheng break; 4572a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S20_3LE: 4582a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 4592a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4602a24f2ceSDong Aisheng break; 4612a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S24_LE: 4622a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 4632a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4642a24f2ceSDong Aisheng break; 4652a24f2ceSDong Aisheng default: 4662a24f2ceSDong Aisheng return -EINVAL; 4672a24f2ceSDong Aisheng } 4682a24f2ceSDong Aisheng 4692a24f2ceSDong Aisheng /* Tx/Rx config */ 4702a24f2ceSDong Aisheng if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 4712a24f2ceSDong Aisheng /* enable TX mode */ 4722a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_READ_MODE; 4732a24f2ceSDong Aisheng } else { 4742a24f2ceSDong Aisheng /* enable RX mode */ 4752a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_READ_MODE; 4762a24f2ceSDong Aisheng } 4772a24f2ceSDong Aisheng 4782a24f2ceSDong Aisheng __raw_writel(scr, saif->base + SAIF_CTRL); 4792a24f2ceSDong Aisheng return 0; 4802a24f2ceSDong Aisheng } 4812a24f2ceSDong Aisheng 4822a24f2ceSDong Aisheng static int mxs_saif_prepare(struct snd_pcm_substream *substream, 4832a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 4842a24f2ceSDong Aisheng { 4852a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 4862a24f2ceSDong Aisheng 4872a24f2ceSDong Aisheng /* enable FIFO error irqs */ 4882a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 4892a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 4902a24f2ceSDong Aisheng 4912a24f2ceSDong Aisheng return 0; 4922a24f2ceSDong Aisheng } 4932a24f2ceSDong Aisheng 4942a24f2ceSDong Aisheng static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 4952a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 4962a24f2ceSDong Aisheng { 4972a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 49876067540SDong Aisheng struct mxs_saif *master_saif; 49976067540SDong Aisheng u32 delay; 50076067540SDong Aisheng 50176067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 50276067540SDong Aisheng if (!master_saif) 50376067540SDong Aisheng return -EINVAL; 5042a24f2ceSDong Aisheng 5052a24f2ceSDong Aisheng switch (cmd) { 5062a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_START: 5072a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_RESUME: 5082a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 5092a24f2ceSDong Aisheng dev_dbg(cpu_dai->dev, "start\n"); 5102a24f2ceSDong Aisheng 51176067540SDong Aisheng clk_enable(master_saif->clk); 51276067540SDong Aisheng if (!master_saif->mclk_in_use) 51376067540SDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 51476067540SDong Aisheng master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 51576067540SDong Aisheng 51676067540SDong Aisheng /* 51776067540SDong Aisheng * If the saif's master is not himself, we also need to enable 51876067540SDong Aisheng * itself clk for its internal basic logic to work. 51976067540SDong Aisheng */ 52076067540SDong Aisheng if (saif != master_saif) { 5212a24f2ceSDong Aisheng clk_enable(saif->clk); 5222a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 5232a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 52476067540SDong Aisheng } 5252a24f2ceSDong Aisheng 5262a24f2ceSDong Aisheng if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5272a24f2ceSDong Aisheng /* 528f55f1475SFabio Estevam * write data to saif data register to trigger 529f55f1475SFabio Estevam * the transfer. 530f55f1475SFabio Estevam * For 24-bit format the 32-bit FIFO register stores 531f55f1475SFabio Estevam * only one channel, so we need to write twice. 532f55f1475SFabio Estevam * This is also safe for the other non 24-bit formats. 5332a24f2ceSDong Aisheng */ 5342a24f2ceSDong Aisheng __raw_writel(0, saif->base + SAIF_DATA); 535f55f1475SFabio Estevam __raw_writel(0, saif->base + SAIF_DATA); 5362a24f2ceSDong Aisheng } else { 5372a24f2ceSDong Aisheng /* 538f55f1475SFabio Estevam * read data from saif data register to trigger 539f55f1475SFabio Estevam * the receive. 540f55f1475SFabio Estevam * For 24-bit format the 32-bit FIFO register stores 541f55f1475SFabio Estevam * only one channel, so we need to read twice. 542f55f1475SFabio Estevam * This is also safe for the other non 24-bit formats. 5432a24f2ceSDong Aisheng */ 5442a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_DATA); 545f55f1475SFabio Estevam __raw_readl(saif->base + SAIF_DATA); 5462a24f2ceSDong Aisheng } 5472a24f2ceSDong Aisheng 54876067540SDong Aisheng master_saif->ongoing = 1; 54976067540SDong Aisheng 55076067540SDong Aisheng dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 5512a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_CTRL), 5522a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_STAT)); 5532a24f2ceSDong Aisheng 55476067540SDong Aisheng dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 55576067540SDong Aisheng __raw_readl(master_saif->base + SAIF_CTRL), 55676067540SDong Aisheng __raw_readl(master_saif->base + SAIF_STAT)); 5572a24f2ceSDong Aisheng break; 5582a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_SUSPEND: 5592a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_STOP: 5602a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 5612a24f2ceSDong Aisheng dev_dbg(cpu_dai->dev, "stop\n"); 5622a24f2ceSDong Aisheng 56376067540SDong Aisheng /* wait a while for the current sample to complete */ 56476067540SDong Aisheng delay = USEC_PER_SEC / master_saif->cur_rate; 56576067540SDong Aisheng 56676067540SDong Aisheng if (!master_saif->mclk_in_use) { 56776067540SDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 56876067540SDong Aisheng master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 56976067540SDong Aisheng udelay(delay); 57076067540SDong Aisheng } 57176067540SDong Aisheng clk_disable(master_saif->clk); 57276067540SDong Aisheng 57376067540SDong Aisheng if (saif != master_saif) { 5742a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 5752a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 57676067540SDong Aisheng udelay(delay); 57776067540SDong Aisheng clk_disable(saif->clk); 57876067540SDong Aisheng } 57976067540SDong Aisheng 58076067540SDong Aisheng master_saif->ongoing = 0; 5812a24f2ceSDong Aisheng 5822a24f2ceSDong Aisheng break; 5832a24f2ceSDong Aisheng default: 5842a24f2ceSDong Aisheng return -EINVAL; 5852a24f2ceSDong Aisheng } 5862a24f2ceSDong Aisheng 5872a24f2ceSDong Aisheng return 0; 5882a24f2ceSDong Aisheng } 5892a24f2ceSDong Aisheng 5902a24f2ceSDong Aisheng #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 5912a24f2ceSDong Aisheng #define MXS_SAIF_FORMATS \ 5922a24f2ceSDong Aisheng (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 5932a24f2ceSDong Aisheng SNDRV_PCM_FMTBIT_S24_LE) 5942a24f2ceSDong Aisheng 59585e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 5962a24f2ceSDong Aisheng .startup = mxs_saif_startup, 5972a24f2ceSDong Aisheng .trigger = mxs_saif_trigger, 5982a24f2ceSDong Aisheng .prepare = mxs_saif_prepare, 5992a24f2ceSDong Aisheng .hw_params = mxs_saif_hw_params, 6002a24f2ceSDong Aisheng .set_sysclk = mxs_saif_set_dai_sysclk, 6012a24f2ceSDong Aisheng .set_fmt = mxs_saif_set_dai_fmt, 6022a24f2ceSDong Aisheng }; 6032a24f2ceSDong Aisheng 6042a24f2ceSDong Aisheng static int mxs_saif_dai_probe(struct snd_soc_dai *dai) 6052a24f2ceSDong Aisheng { 6062a24f2ceSDong Aisheng struct mxs_saif *saif = dev_get_drvdata(dai->dev); 6072a24f2ceSDong Aisheng 6082a24f2ceSDong Aisheng snd_soc_dai_set_drvdata(dai, saif); 6092a24f2ceSDong Aisheng 6102a24f2ceSDong Aisheng return 0; 6112a24f2ceSDong Aisheng } 6122a24f2ceSDong Aisheng 6132a24f2ceSDong Aisheng static struct snd_soc_dai_driver mxs_saif_dai = { 6142a24f2ceSDong Aisheng .name = "mxs-saif", 6152a24f2ceSDong Aisheng .probe = mxs_saif_dai_probe, 6162a24f2ceSDong Aisheng .playback = { 6172a24f2ceSDong Aisheng .channels_min = 2, 6182a24f2ceSDong Aisheng .channels_max = 2, 6192a24f2ceSDong Aisheng .rates = MXS_SAIF_RATES, 6202a24f2ceSDong Aisheng .formats = MXS_SAIF_FORMATS, 6212a24f2ceSDong Aisheng }, 6222a24f2ceSDong Aisheng .capture = { 6232a24f2ceSDong Aisheng .channels_min = 2, 6242a24f2ceSDong Aisheng .channels_max = 2, 6252a24f2ceSDong Aisheng .rates = MXS_SAIF_RATES, 6262a24f2ceSDong Aisheng .formats = MXS_SAIF_FORMATS, 6272a24f2ceSDong Aisheng }, 6282a24f2ceSDong Aisheng .ops = &mxs_saif_dai_ops, 6292a24f2ceSDong Aisheng }; 6302a24f2ceSDong Aisheng 6312a24f2ceSDong Aisheng static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 6322a24f2ceSDong Aisheng { 6332a24f2ceSDong Aisheng struct mxs_saif *saif = dev_id; 6342a24f2ceSDong Aisheng unsigned int stat; 6352a24f2ceSDong Aisheng 6362a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 6372a24f2ceSDong Aisheng if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 6382a24f2ceSDong Aisheng BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 6392a24f2ceSDong Aisheng return IRQ_NONE; 6402a24f2ceSDong Aisheng 6412a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 6422a24f2ceSDong Aisheng dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 6432a24f2ceSDong Aisheng __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 6442a24f2ceSDong Aisheng saif->base + SAIF_STAT + MXS_CLR_ADDR); 6452a24f2ceSDong Aisheng } 6462a24f2ceSDong Aisheng 6472a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 6482a24f2ceSDong Aisheng dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 6492a24f2ceSDong Aisheng __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 6502a24f2ceSDong Aisheng saif->base + SAIF_STAT + MXS_CLR_ADDR); 6512a24f2ceSDong Aisheng } 6522a24f2ceSDong Aisheng 6532a24f2ceSDong Aisheng dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 6542a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_CTRL), 6552a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_STAT)); 6562a24f2ceSDong Aisheng 6572a24f2ceSDong Aisheng return IRQ_HANDLED; 6582a24f2ceSDong Aisheng } 6592a24f2ceSDong Aisheng 660fd582736SBill Pemberton static int mxs_saif_probe(struct platform_device *pdev) 6612a24f2ceSDong Aisheng { 66208641c7cSShawn Guo struct device_node *np = pdev->dev.of_node; 663226d0f22SJulia Lawall struct resource *iores, *dmares; 6642a24f2ceSDong Aisheng struct mxs_saif *saif; 66576067540SDong Aisheng struct mxs_saif_platform_data *pdata; 666f755865fSShawn Guo struct pinctrl *pinctrl; 6672a24f2ceSDong Aisheng int ret = 0; 6682a24f2ceSDong Aisheng 66908641c7cSShawn Guo 67008641c7cSShawn Guo if (!np && pdev->id >= ARRAY_SIZE(mxs_saif)) 6710bb98ba2SJulia Lawall return -EINVAL; 6720bb98ba2SJulia Lawall 673830eb876SJulia Lawall saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 6742a24f2ceSDong Aisheng if (!saif) 6752a24f2ceSDong Aisheng return -ENOMEM; 6762a24f2ceSDong Aisheng 67708641c7cSShawn Guo if (np) { 67808641c7cSShawn Guo struct device_node *master; 67908641c7cSShawn Guo saif->id = of_alias_get_id(np, "saif"); 68008641c7cSShawn Guo if (saif->id < 0) 68108641c7cSShawn Guo return saif->id; 68208641c7cSShawn Guo /* 68308641c7cSShawn Guo * If there is no "fsl,saif-master" phandle, it's a saif 68408641c7cSShawn Guo * master. Otherwise, it's a slave and its phandle points 68508641c7cSShawn Guo * to the master. 68608641c7cSShawn Guo */ 68708641c7cSShawn Guo master = of_parse_phandle(np, "fsl,saif-master", 0); 68808641c7cSShawn Guo if (!master) { 68908641c7cSShawn Guo saif->master_id = saif->id; 69008641c7cSShawn Guo } else { 69108641c7cSShawn Guo saif->master_id = of_alias_get_id(master, "saif"); 69208641c7cSShawn Guo if (saif->master_id < 0) 69308641c7cSShawn Guo return saif->master_id; 69408641c7cSShawn Guo } 69508641c7cSShawn Guo } else { 69676067540SDong Aisheng saif->id = pdev->id; 69777882580SDong Aisheng pdata = pdev->dev.platform_data; 69808641c7cSShawn Guo if (pdata && !pdata->master_mode) 69977882580SDong Aisheng saif->master_id = pdata->master_id; 70008641c7cSShawn Guo else 70108641c7cSShawn Guo saif->master_id = saif->id; 70208641c7cSShawn Guo } 70308641c7cSShawn Guo 70408641c7cSShawn Guo if (saif->master_id < 0 || saif->master_id >= ARRAY_SIZE(mxs_saif)) { 70577882580SDong Aisheng dev_err(&pdev->dev, "get wrong master id\n"); 70676067540SDong Aisheng return -EINVAL; 70776067540SDong Aisheng } 70808641c7cSShawn Guo 70908641c7cSShawn Guo mxs_saif[saif->id] = saif; 7102a24f2ceSDong Aisheng 711f755865fSShawn Guo pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 712f755865fSShawn Guo if (IS_ERR(pinctrl)) { 713f755865fSShawn Guo ret = PTR_ERR(pinctrl); 714f755865fSShawn Guo return ret; 715f755865fSShawn Guo } 716f755865fSShawn Guo 717730963f8SFabio Estevam saif->clk = devm_clk_get(&pdev->dev, NULL); 7182a24f2ceSDong Aisheng if (IS_ERR(saif->clk)) { 7192a24f2ceSDong Aisheng ret = PTR_ERR(saif->clk); 7202a24f2ceSDong Aisheng dev_err(&pdev->dev, "Cannot get the clock: %d\n", 7212a24f2ceSDong Aisheng ret); 722830eb876SJulia Lawall return ret; 7232a24f2ceSDong Aisheng } 7242a24f2ceSDong Aisheng 725226d0f22SJulia Lawall iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 7262a24f2ceSDong Aisheng 727830eb876SJulia Lawall saif->base = devm_request_and_ioremap(&pdev->dev, iores); 7282a24f2ceSDong Aisheng if (!saif->base) { 7292a24f2ceSDong Aisheng dev_err(&pdev->dev, "ioremap failed\n"); 730730963f8SFabio Estevam return -ENODEV; 7312a24f2ceSDong Aisheng } 7322a24f2ceSDong Aisheng 733226d0f22SJulia Lawall dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 734226d0f22SJulia Lawall if (!dmares) { 73508641c7cSShawn Guo /* 73608641c7cSShawn Guo * TODO: This is a temporary solution and should be changed 73708641c7cSShawn Guo * to use generic DMA binding later when the helplers get in. 73808641c7cSShawn Guo */ 73908641c7cSShawn Guo ret = of_property_read_u32(np, "fsl,saif-dma-channel", 74008641c7cSShawn Guo &saif->dma_param.chan_num); 74108641c7cSShawn Guo if (ret) { 74208641c7cSShawn Guo dev_err(&pdev->dev, "failed to get dma channel\n"); 743730963f8SFabio Estevam return ret; 7442a24f2ceSDong Aisheng } 74508641c7cSShawn Guo } else { 746226d0f22SJulia Lawall saif->dma_param.chan_num = dmares->start; 74708641c7cSShawn Guo } 7482a24f2ceSDong Aisheng 7492a24f2ceSDong Aisheng saif->irq = platform_get_irq(pdev, 0); 7502a24f2ceSDong Aisheng if (saif->irq < 0) { 7512a24f2ceSDong Aisheng ret = saif->irq; 7522a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to get irq resource: %d\n", 7532a24f2ceSDong Aisheng ret); 754730963f8SFabio Estevam return ret; 7552a24f2ceSDong Aisheng } 7562a24f2ceSDong Aisheng 7572a24f2ceSDong Aisheng saif->dev = &pdev->dev; 758830eb876SJulia Lawall ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0, 759830eb876SJulia Lawall "mxs-saif", saif); 7602a24f2ceSDong Aisheng if (ret) { 7612a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to request irq\n"); 762730963f8SFabio Estevam return ret; 7632a24f2ceSDong Aisheng } 7642a24f2ceSDong Aisheng 7652a24f2ceSDong Aisheng saif->dma_param.chan_irq = platform_get_irq(pdev, 1); 7662a24f2ceSDong Aisheng if (saif->dma_param.chan_irq < 0) { 7672a24f2ceSDong Aisheng ret = saif->dma_param.chan_irq; 7682a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to get dma irq resource: %d\n", 7692a24f2ceSDong Aisheng ret); 770730963f8SFabio Estevam return ret; 7712a24f2ceSDong Aisheng } 7722a24f2ceSDong Aisheng 7732a24f2ceSDong Aisheng platform_set_drvdata(pdev, saif); 7742a24f2ceSDong Aisheng 7752a24f2ceSDong Aisheng ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai); 7762a24f2ceSDong Aisheng if (ret) { 7772a24f2ceSDong Aisheng dev_err(&pdev->dev, "register DAI failed\n"); 778730963f8SFabio Estevam return ret; 7792a24f2ceSDong Aisheng } 7802a24f2ceSDong Aisheng 7814da3fe78SShawn Guo ret = mxs_pcm_platform_register(&pdev->dev); 7822a24f2ceSDong Aisheng if (ret) { 7834da3fe78SShawn Guo dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 7844da3fe78SShawn Guo goto failed_pdev_alloc; 7852a24f2ceSDong Aisheng } 7862a24f2ceSDong Aisheng 7872a24f2ceSDong Aisheng return 0; 7882a24f2ceSDong Aisheng 7892a24f2ceSDong Aisheng failed_pdev_alloc: 7902a24f2ceSDong Aisheng snd_soc_unregister_dai(&pdev->dev); 7912a24f2ceSDong Aisheng 7922a24f2ceSDong Aisheng return ret; 7932a24f2ceSDong Aisheng } 7942a24f2ceSDong Aisheng 795fd582736SBill Pemberton static int mxs_saif_remove(struct platform_device *pdev) 7962a24f2ceSDong Aisheng { 7974da3fe78SShawn Guo mxs_pcm_platform_unregister(&pdev->dev); 7982a24f2ceSDong Aisheng snd_soc_unregister_dai(&pdev->dev); 7992a24f2ceSDong Aisheng 8002a24f2ceSDong Aisheng return 0; 8012a24f2ceSDong Aisheng } 8022a24f2ceSDong Aisheng 80308641c7cSShawn Guo static const struct of_device_id mxs_saif_dt_ids[] = { 80408641c7cSShawn Guo { .compatible = "fsl,imx28-saif", }, 80508641c7cSShawn Guo { /* sentinel */ } 80608641c7cSShawn Guo }; 80708641c7cSShawn Guo MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 80808641c7cSShawn Guo 8092a24f2ceSDong Aisheng static struct platform_driver mxs_saif_driver = { 8102a24f2ceSDong Aisheng .probe = mxs_saif_probe, 811fd582736SBill Pemberton .remove = mxs_saif_remove, 8122a24f2ceSDong Aisheng 8132a24f2ceSDong Aisheng .driver = { 8142a24f2ceSDong Aisheng .name = "mxs-saif", 8152a24f2ceSDong Aisheng .owner = THIS_MODULE, 81608641c7cSShawn Guo .of_match_table = mxs_saif_dt_ids, 8172a24f2ceSDong Aisheng }, 8182a24f2ceSDong Aisheng }; 8192a24f2ceSDong Aisheng 82085aa0960SAxel Lin module_platform_driver(mxs_saif_driver); 8212a24f2ceSDong Aisheng 8222a24f2ceSDong Aisheng MODULE_AUTHOR("Freescale Semiconductor, Inc."); 8232a24f2ceSDong Aisheng MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 8242a24f2ceSDong Aisheng MODULE_LICENSE("GPL"); 8259f4c3f1cSFabio Estevam MODULE_ALIAS("platform:mxs-saif"); 826