116216333SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 22a24f2ceSDong Aisheng /* 32a24f2ceSDong Aisheng * Copyright 2011 Freescale Semiconductor, Inc. 42a24f2ceSDong Aisheng */ 52a24f2ceSDong Aisheng 62a24f2ceSDong Aisheng #include <linux/module.h> 72a24f2ceSDong Aisheng #include <linux/init.h> 808641c7cSShawn Guo #include <linux/of.h> 908641c7cSShawn Guo #include <linux/of_device.h> 102a24f2ceSDong Aisheng #include <linux/platform_device.h> 112a24f2ceSDong Aisheng #include <linux/slab.h> 122a24f2ceSDong Aisheng #include <linux/dma-mapping.h> 132a24f2ceSDong Aisheng #include <linux/clk.h> 147c9e6150SShawn Guo #include <linux/clk-provider.h> 152a24f2ceSDong Aisheng #include <linux/delay.h> 1662e59c4eSStephen Boyd #include <linux/io.h> 1776067540SDong Aisheng #include <linux/time.h> 182a24f2ceSDong Aisheng #include <sound/core.h> 192a24f2ceSDong Aisheng #include <sound/pcm.h> 202a24f2ceSDong Aisheng #include <sound/pcm_params.h> 212a24f2ceSDong Aisheng #include <sound/soc.h> 222a24f2ceSDong Aisheng 232a24f2ceSDong Aisheng #include "mxs-saif.h" 242a24f2ceSDong Aisheng 25114fe75dSShawn Guo #define MXS_SET_ADDR 0x4 26114fe75dSShawn Guo #define MXS_CLR_ADDR 0x8 27114fe75dSShawn Guo 282a24f2ceSDong Aisheng static struct mxs_saif *mxs_saif[2]; 292a24f2ceSDong Aisheng 3076067540SDong Aisheng /* 3176067540SDong Aisheng * SAIF is a little different with other normal SOC DAIs on clock using. 3276067540SDong Aisheng * 3376067540SDong Aisheng * For MXS, two SAIF modules are instantiated on-chip. 3476067540SDong Aisheng * Each SAIF has a set of clock pins and can be operating in master 3576067540SDong Aisheng * mode simultaneously if they are connected to different off-chip codecs. 3676067540SDong Aisheng * Also, one of the two SAIFs can master or drive the clock pins while the 3776067540SDong Aisheng * other SAIF, in slave mode, receives clocking from the master SAIF. 3876067540SDong Aisheng * This also means that both SAIFs must operate at the same sample rate. 3976067540SDong Aisheng * 4076067540SDong Aisheng * We abstract this as each saif has a master, the master could be 4105004cb4SMatthew Garrett * itself or other saifs. In the generic saif driver, saif does not need 4205004cb4SMatthew Garrett * to know the different clkmux. Saif only needs to know who is its master 4305004cb4SMatthew Garrett * and operating its master to generate the proper clock rate for it. 4476067540SDong Aisheng * The master id is provided in mach-specific layer according to different 4576067540SDong Aisheng * clkmux setting. 4676067540SDong Aisheng */ 4776067540SDong Aisheng 482a24f2ceSDong Aisheng static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 492a24f2ceSDong Aisheng int clk_id, unsigned int freq, int dir) 502a24f2ceSDong Aisheng { 512a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 522a24f2ceSDong Aisheng 532a24f2ceSDong Aisheng switch (clk_id) { 542a24f2ceSDong Aisheng case MXS_SAIF_MCLK: 552a24f2ceSDong Aisheng saif->mclk = freq; 562a24f2ceSDong Aisheng break; 572a24f2ceSDong Aisheng default: 582a24f2ceSDong Aisheng return -EINVAL; 592a24f2ceSDong Aisheng } 602a24f2ceSDong Aisheng return 0; 612a24f2ceSDong Aisheng } 622a24f2ceSDong Aisheng 632a24f2ceSDong Aisheng /* 6476067540SDong Aisheng * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 6576067540SDong Aisheng * is provided by other SAIF, we provide a interface here to get its master 6676067540SDong Aisheng * from its master_id. 6705004cb4SMatthew Garrett * Note that the master could be itself. 6876067540SDong Aisheng */ 6976067540SDong Aisheng static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 7076067540SDong Aisheng { 7176067540SDong Aisheng return mxs_saif[saif->master_id]; 7276067540SDong Aisheng } 7376067540SDong Aisheng 7476067540SDong Aisheng /* 752a24f2ceSDong Aisheng * Set SAIF clock and MCLK 762a24f2ceSDong Aisheng */ 772a24f2ceSDong Aisheng static int mxs_saif_set_clk(struct mxs_saif *saif, 782a24f2ceSDong Aisheng unsigned int mclk, 792a24f2ceSDong Aisheng unsigned int rate) 802a24f2ceSDong Aisheng { 812a24f2ceSDong Aisheng u32 scr; 822a24f2ceSDong Aisheng int ret; 8376067540SDong Aisheng struct mxs_saif *master_saif; 842a24f2ceSDong Aisheng 8576067540SDong Aisheng dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 8676067540SDong Aisheng 8776067540SDong Aisheng /* Set master saif to generate proper clock */ 8876067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 8976067540SDong Aisheng if (!master_saif) 9076067540SDong Aisheng return -EINVAL; 9176067540SDong Aisheng 9276067540SDong Aisheng dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 9376067540SDong Aisheng 9476067540SDong Aisheng /* Checking if can playback and capture simutaneously */ 9576067540SDong Aisheng if (master_saif->ongoing && rate != master_saif->cur_rate) { 9676067540SDong Aisheng dev_err(saif->dev, 9776067540SDong Aisheng "can not change clock, master saif%d(rate %d) is ongoing\n", 9876067540SDong Aisheng master_saif->id, master_saif->cur_rate); 9976067540SDong Aisheng return -EINVAL; 10076067540SDong Aisheng } 10176067540SDong Aisheng 10276067540SDong Aisheng scr = __raw_readl(master_saif->base + SAIF_CTRL); 1032a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 1042a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 1052a24f2ceSDong Aisheng 1062a24f2ceSDong Aisheng /* 1072a24f2ceSDong Aisheng * Set SAIF clock 1082a24f2ceSDong Aisheng * 1092a24f2ceSDong Aisheng * The SAIF clock should be either 384*fs or 512*fs. 110bcb8c270SJörg Krause * If MCLK is used, the SAIF clk ratio needs to match mclk ratio. 111bcb8c270SJörg Krause * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs. 112bcb8c270SJörg Krause * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs. 1132a24f2ceSDong Aisheng * 1142a24f2ceSDong Aisheng * If MCLK is not used, we just set saif clk to 512*fs. 1152a24f2ceSDong Aisheng */ 1160d97ee86SArvind Yadav ret = clk_prepare_enable(master_saif->clk); 1170d97ee86SArvind Yadav if (ret) 1180d97ee86SArvind Yadav return ret; 1196b35f924SFabio Estevam 12076067540SDong Aisheng if (master_saif->mclk_in_use) { 121bcb8c270SJörg Krause switch (mclk / rate) { 122bcb8c270SJörg Krause case 32: 123bcb8c270SJörg Krause case 64: 124bcb8c270SJörg Krause case 128: 125bcb8c270SJörg Krause case 256: 126bcb8c270SJörg Krause case 512: 1272a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 12876067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 512 * rate); 129bcb8c270SJörg Krause break; 130bcb8c270SJörg Krause case 48: 131bcb8c270SJörg Krause case 96: 132bcb8c270SJörg Krause case 192: 133bcb8c270SJörg Krause case 384: 1342a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 13576067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 384 * rate); 136bcb8c270SJörg Krause break; 137bcb8c270SJörg Krause default: 138bcb8c270SJörg Krause /* SAIF MCLK should be a sub-rate of 512x or 384x */ 1396b35f924SFabio Estevam clk_disable_unprepare(master_saif->clk); 1402a24f2ceSDong Aisheng return -EINVAL; 1412a24f2ceSDong Aisheng } 1422a24f2ceSDong Aisheng } else { 14376067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 512 * rate); 1442a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 1452a24f2ceSDong Aisheng } 1462a24f2ceSDong Aisheng 1476b35f924SFabio Estevam clk_disable_unprepare(master_saif->clk); 1486b35f924SFabio Estevam 1492a24f2ceSDong Aisheng if (ret) 1502a24f2ceSDong Aisheng return ret; 1512a24f2ceSDong Aisheng 15276067540SDong Aisheng master_saif->cur_rate = rate; 15376067540SDong Aisheng 15476067540SDong Aisheng if (!master_saif->mclk_in_use) { 15576067540SDong Aisheng __raw_writel(scr, master_saif->base + SAIF_CTRL); 1562a24f2ceSDong Aisheng return 0; 1572a24f2ceSDong Aisheng } 1582a24f2ceSDong Aisheng 1592a24f2ceSDong Aisheng /* 1602a24f2ceSDong Aisheng * Program the over-sample rate for MCLK output 1612a24f2ceSDong Aisheng * 1622a24f2ceSDong Aisheng * The available MCLK range is 32x, 48x... 512x. The rate 1632a24f2ceSDong Aisheng * could be from 8kHz to 192kH. 1642a24f2ceSDong Aisheng */ 1652a24f2ceSDong Aisheng switch (mclk / rate) { 1662a24f2ceSDong Aisheng case 32: 1672a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 1682a24f2ceSDong Aisheng break; 1692a24f2ceSDong Aisheng case 64: 1702a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 1712a24f2ceSDong Aisheng break; 1722a24f2ceSDong Aisheng case 128: 1732a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 1742a24f2ceSDong Aisheng break; 1752a24f2ceSDong Aisheng case 256: 1762a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 1772a24f2ceSDong Aisheng break; 1782a24f2ceSDong Aisheng case 512: 1792a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 1802a24f2ceSDong Aisheng break; 1812a24f2ceSDong Aisheng case 48: 1822a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 1832a24f2ceSDong Aisheng break; 1842a24f2ceSDong Aisheng case 96: 1852a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 1862a24f2ceSDong Aisheng break; 1872a24f2ceSDong Aisheng case 192: 1882a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 1892a24f2ceSDong Aisheng break; 1902a24f2ceSDong Aisheng case 384: 1912a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 1922a24f2ceSDong Aisheng break; 1932a24f2ceSDong Aisheng default: 1942a24f2ceSDong Aisheng return -EINVAL; 1952a24f2ceSDong Aisheng } 1962a24f2ceSDong Aisheng 19776067540SDong Aisheng __raw_writel(scr, master_saif->base + SAIF_CTRL); 1982a24f2ceSDong Aisheng 1992a24f2ceSDong Aisheng return 0; 2002a24f2ceSDong Aisheng } 2012a24f2ceSDong Aisheng 2022a24f2ceSDong Aisheng /* 2032a24f2ceSDong Aisheng * Put and disable MCLK. 2042a24f2ceSDong Aisheng */ 2052a24f2ceSDong Aisheng int mxs_saif_put_mclk(unsigned int saif_id) 2062a24f2ceSDong Aisheng { 2072a24f2ceSDong Aisheng struct mxs_saif *saif = mxs_saif[saif_id]; 2082a24f2ceSDong Aisheng u32 stat; 2092a24f2ceSDong Aisheng 2102a24f2ceSDong Aisheng if (!saif) 2112a24f2ceSDong Aisheng return -EINVAL; 2122a24f2ceSDong Aisheng 2132a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2142a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2152a24f2ceSDong Aisheng dev_err(saif->dev, "error: busy\n"); 2162a24f2ceSDong Aisheng return -EBUSY; 2172a24f2ceSDong Aisheng } 2182a24f2ceSDong Aisheng 21967939b22SShawn Guo clk_disable_unprepare(saif->clk); 2202a24f2ceSDong Aisheng 2212a24f2ceSDong Aisheng /* disable MCLK output */ 2222a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 2232a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 2242a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 2252a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 2262a24f2ceSDong Aisheng 2272a24f2ceSDong Aisheng saif->mclk_in_use = 0; 2282a24f2ceSDong Aisheng return 0; 2292a24f2ceSDong Aisheng } 230cf7d0f09SLothar Waßmann EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); 2312a24f2ceSDong Aisheng 2322a24f2ceSDong Aisheng /* 2332a24f2ceSDong Aisheng * Get MCLK and set clock rate, then enable it 2342a24f2ceSDong Aisheng * 2352a24f2ceSDong Aisheng * This interface is used for codecs who are using MCLK provided 2362a24f2ceSDong Aisheng * by saif. 2372a24f2ceSDong Aisheng */ 2382a24f2ceSDong Aisheng int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 2392a24f2ceSDong Aisheng unsigned int rate) 2402a24f2ceSDong Aisheng { 2412a24f2ceSDong Aisheng struct mxs_saif *saif = mxs_saif[saif_id]; 2422a24f2ceSDong Aisheng u32 stat; 2432a24f2ceSDong Aisheng int ret; 24476067540SDong Aisheng struct mxs_saif *master_saif; 2452a24f2ceSDong Aisheng 2462a24f2ceSDong Aisheng if (!saif) 2472a24f2ceSDong Aisheng return -EINVAL; 2482a24f2ceSDong Aisheng 249bbe8ff5eSDong Aisheng /* Clear Reset */ 250bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_SFTRST, 251bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 252bbe8ff5eSDong Aisheng 253bbe8ff5eSDong Aisheng /* FIXME: need clear clk gate for register r/w */ 254bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 255bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 256bbe8ff5eSDong Aisheng 25776067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 25876067540SDong Aisheng if (saif != master_saif) { 25976067540SDong Aisheng dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 26076067540SDong Aisheng return -EINVAL; 26176067540SDong Aisheng } 26276067540SDong Aisheng 2632a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2642a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2652a24f2ceSDong Aisheng dev_err(saif->dev, "error: busy\n"); 2662a24f2ceSDong Aisheng return -EBUSY; 2672a24f2ceSDong Aisheng } 2682a24f2ceSDong Aisheng 2692a24f2ceSDong Aisheng saif->mclk_in_use = 1; 2702a24f2ceSDong Aisheng ret = mxs_saif_set_clk(saif, mclk, rate); 2712a24f2ceSDong Aisheng if (ret) 2722a24f2ceSDong Aisheng return ret; 2732a24f2ceSDong Aisheng 27467939b22SShawn Guo ret = clk_prepare_enable(saif->clk); 2752a24f2ceSDong Aisheng if (ret) 2762a24f2ceSDong Aisheng return ret; 2772a24f2ceSDong Aisheng 2782a24f2ceSDong Aisheng /* enable MCLK output */ 2792a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 2802a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 2812a24f2ceSDong Aisheng 2822a24f2ceSDong Aisheng return 0; 2832a24f2ceSDong Aisheng } 284cf7d0f09SLothar Waßmann EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); 2852a24f2ceSDong Aisheng 2862a24f2ceSDong Aisheng /* 2872a24f2ceSDong Aisheng * SAIF DAI format configuration. 2882a24f2ceSDong Aisheng * Should only be called when port is inactive. 2892a24f2ceSDong Aisheng */ 2902a24f2ceSDong Aisheng static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 2912a24f2ceSDong Aisheng { 2922a24f2ceSDong Aisheng u32 scr, stat; 2932a24f2ceSDong Aisheng u32 scr0; 2942a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 2952a24f2ceSDong Aisheng 2962a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2972a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2982a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "error: busy\n"); 2992a24f2ceSDong Aisheng return -EBUSY; 3002a24f2ceSDong Aisheng } 3012a24f2ceSDong Aisheng 302b25658edSJörg Krause /* If SAIF1 is configured as slave, the clk gate needs to be cleared 303b25658edSJörg Krause * before the register can be written. 304b25658edSJörg Krause */ 305b25658edSJörg Krause if (saif->id != saif->master_id) { 306b25658edSJörg Krause __raw_writel(BM_SAIF_CTRL_SFTRST, 307b25658edSJörg Krause saif->base + SAIF_CTRL + MXS_CLR_ADDR); 308b25658edSJörg Krause __raw_writel(BM_SAIF_CTRL_CLKGATE, 309b25658edSJörg Krause saif->base + SAIF_CTRL + MXS_CLR_ADDR); 310b25658edSJörg Krause } 311b25658edSJörg Krause 3122a24f2ceSDong Aisheng scr0 = __raw_readl(saif->base + SAIF_CTRL); 3132a24f2ceSDong Aisheng scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 3142a24f2ceSDong Aisheng & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 3152a24f2ceSDong Aisheng scr = 0; 3162a24f2ceSDong Aisheng 3172a24f2ceSDong Aisheng /* DAI mode */ 3182a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3192a24f2ceSDong Aisheng case SND_SOC_DAIFMT_I2S: 3202a24f2ceSDong Aisheng /* data frame low 1clk before data */ 3212a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_DELAY; 3222a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3232a24f2ceSDong Aisheng break; 3242a24f2ceSDong Aisheng case SND_SOC_DAIFMT_LEFT_J: 3252a24f2ceSDong Aisheng /* data frame high with data */ 3262a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_DELAY; 3272a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3282a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_JUSTIFY; 3292a24f2ceSDong Aisheng break; 3302a24f2ceSDong Aisheng default: 3312a24f2ceSDong Aisheng return -EINVAL; 3322a24f2ceSDong Aisheng } 3332a24f2ceSDong Aisheng 3342a24f2ceSDong Aisheng /* DAI clock inversion */ 3352a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3362a24f2ceSDong Aisheng case SND_SOC_DAIFMT_IB_IF: 3372a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_EDGE; 3382a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 3392a24f2ceSDong Aisheng break; 3402a24f2ceSDong Aisheng case SND_SOC_DAIFMT_IB_NF: 3412a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_EDGE; 3422a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3432a24f2ceSDong Aisheng break; 3442a24f2ceSDong Aisheng case SND_SOC_DAIFMT_NB_IF: 3452a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 3462a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 3472a24f2ceSDong Aisheng break; 3482a24f2ceSDong Aisheng case SND_SOC_DAIFMT_NB_NF: 3492a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 3502a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3512a24f2ceSDong Aisheng break; 3522a24f2ceSDong Aisheng } 3532a24f2ceSDong Aisheng 3542a24f2ceSDong Aisheng /* 3552a24f2ceSDong Aisheng * Note: We simply just support master mode since SAIF TX can only 3562a24f2ceSDong Aisheng * work as master. 35776067540SDong Aisheng * Here the master is relative to codec side. 35876067540SDong Aisheng * Saif internally could be slave when working on EXTMASTER mode. 35976067540SDong Aisheng * We just hide this to machine driver. 3602a24f2ceSDong Aisheng */ 361*f3c0064fSCharles Keepax switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 362*f3c0064fSCharles Keepax case SND_SOC_DAIFMT_BP_FP: 36376067540SDong Aisheng if (saif->id == saif->master_id) 3642a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 36576067540SDong Aisheng else 36676067540SDong Aisheng scr |= BM_SAIF_CTRL_SLAVE_MODE; 36776067540SDong Aisheng 3682a24f2ceSDong Aisheng __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 3692a24f2ceSDong Aisheng break; 3702a24f2ceSDong Aisheng default: 3712a24f2ceSDong Aisheng return -EINVAL; 3722a24f2ceSDong Aisheng } 3732a24f2ceSDong Aisheng 3742a24f2ceSDong Aisheng return 0; 3752a24f2ceSDong Aisheng } 3762a24f2ceSDong Aisheng 3772a24f2ceSDong Aisheng static int mxs_saif_startup(struct snd_pcm_substream *substream, 3782a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 3792a24f2ceSDong Aisheng { 3802a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 3810d97ee86SArvind Yadav int ret; 3822a24f2ceSDong Aisheng 3832a24f2ceSDong Aisheng /* clear error status to 0 for each re-open */ 3842a24f2ceSDong Aisheng saif->fifo_underrun = 0; 3852a24f2ceSDong Aisheng saif->fifo_overrun = 0; 3862a24f2ceSDong Aisheng 3872a24f2ceSDong Aisheng /* Clear Reset for normal operations */ 3882a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_SFTRST, 3892a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 3902a24f2ceSDong Aisheng 391bbe8ff5eSDong Aisheng /* clear clock gate */ 392bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 393bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 394bbe8ff5eSDong Aisheng 3950d97ee86SArvind Yadav ret = clk_prepare(saif->clk); 3960d97ee86SArvind Yadav if (ret) 3970d97ee86SArvind Yadav return ret; 398f212c6d8SMans Rullgard 3992a24f2ceSDong Aisheng return 0; 4002a24f2ceSDong Aisheng } 4012a24f2ceSDong Aisheng 402f212c6d8SMans Rullgard static void mxs_saif_shutdown(struct snd_pcm_substream *substream, 403f212c6d8SMans Rullgard struct snd_soc_dai *cpu_dai) 404f212c6d8SMans Rullgard { 405f212c6d8SMans Rullgard struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 406f212c6d8SMans Rullgard 407f212c6d8SMans Rullgard clk_unprepare(saif->clk); 408f212c6d8SMans Rullgard } 409f212c6d8SMans Rullgard 4102a24f2ceSDong Aisheng /* 4112a24f2ceSDong Aisheng * Should only be called when port is inactive. 4122a24f2ceSDong Aisheng * although can be called multiple times by upper layers. 4132a24f2ceSDong Aisheng */ 4142a24f2ceSDong Aisheng static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 4152a24f2ceSDong Aisheng struct snd_pcm_hw_params *params, 4162a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 4172a24f2ceSDong Aisheng { 4182a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 419c2e1d907SDong Aisheng struct mxs_saif *master_saif; 4202a24f2ceSDong Aisheng u32 scr, stat; 4212a24f2ceSDong Aisheng int ret; 4222a24f2ceSDong Aisheng 423c2e1d907SDong Aisheng master_saif = mxs_saif_get_master(saif); 424c2e1d907SDong Aisheng if (!master_saif) 425c2e1d907SDong Aisheng return -EINVAL; 426c2e1d907SDong Aisheng 4272a24f2ceSDong Aisheng /* mclk should already be set */ 4282a24f2ceSDong Aisheng if (!saif->mclk && saif->mclk_in_use) { 4292a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "set mclk first\n"); 4302a24f2ceSDong Aisheng return -EINVAL; 4312a24f2ceSDong Aisheng } 4322a24f2ceSDong Aisheng 4332a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 434436e056cSMans Rullgard if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) { 4352a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "error: busy\n"); 4362a24f2ceSDong Aisheng return -EBUSY; 4372a24f2ceSDong Aisheng } 4382a24f2ceSDong Aisheng 4392a24f2ceSDong Aisheng /* 4402a24f2ceSDong Aisheng * Set saif clk based on sample rate. 4412a24f2ceSDong Aisheng * If mclk is used, we also set mclk, if not, saif->mclk is 4422a24f2ceSDong Aisheng * default 0, means not used. 4432a24f2ceSDong Aisheng */ 4442a24f2ceSDong Aisheng ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 4452a24f2ceSDong Aisheng if (ret) { 4462a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "unable to get proper clk\n"); 4472a24f2ceSDong Aisheng return ret; 4482a24f2ceSDong Aisheng } 4492a24f2ceSDong Aisheng 450d0ba4c01SDong Aisheng if (saif != master_saif) { 451d0ba4c01SDong Aisheng /* 452d0ba4c01SDong Aisheng * Set an initial clock rate for the saif internal logic to work 453d0ba4c01SDong Aisheng * properly. This is important when working in EXTMASTER mode 454d0ba4c01SDong Aisheng * that uses the other saif's BITCLK&LRCLK but it still needs a 455d0ba4c01SDong Aisheng * basic clock which should be fast enough for the internal 456d0ba4c01SDong Aisheng * logic. 457d0ba4c01SDong Aisheng */ 4582ecf362dSJiasheng Jiang ret = clk_enable(saif->clk); 4592ecf362dSJiasheng Jiang if (ret) 4602ecf362dSJiasheng Jiang return ret; 4612ecf362dSJiasheng Jiang 462d0ba4c01SDong Aisheng ret = clk_set_rate(saif->clk, 24000000); 463d0ba4c01SDong Aisheng clk_disable(saif->clk); 464d0ba4c01SDong Aisheng if (ret) 465d0ba4c01SDong Aisheng return ret; 466d0ba4c01SDong Aisheng 4670d97ee86SArvind Yadav ret = clk_prepare(master_saif->clk); 4680d97ee86SArvind Yadav if (ret) 4690d97ee86SArvind Yadav return ret; 470d0ba4c01SDong Aisheng } 471c2e1d907SDong Aisheng 4722a24f2ceSDong Aisheng scr = __raw_readl(saif->base + SAIF_CTRL); 4732a24f2ceSDong Aisheng 4742a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 4752a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4762a24f2ceSDong Aisheng switch (params_format(params)) { 4772a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S16_LE: 4782a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 4792a24f2ceSDong Aisheng break; 4802a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S20_3LE: 4812a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 4822a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4832a24f2ceSDong Aisheng break; 4842a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S24_LE: 4852a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 4862a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4872a24f2ceSDong Aisheng break; 4882a24f2ceSDong Aisheng default: 4892a24f2ceSDong Aisheng return -EINVAL; 4902a24f2ceSDong Aisheng } 4912a24f2ceSDong Aisheng 4922a24f2ceSDong Aisheng /* Tx/Rx config */ 4932a24f2ceSDong Aisheng if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 4942a24f2ceSDong Aisheng /* enable TX mode */ 4952a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_READ_MODE; 4962a24f2ceSDong Aisheng } else { 4972a24f2ceSDong Aisheng /* enable RX mode */ 4982a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_READ_MODE; 4992a24f2ceSDong Aisheng } 5002a24f2ceSDong Aisheng 5012a24f2ceSDong Aisheng __raw_writel(scr, saif->base + SAIF_CTRL); 5022a24f2ceSDong Aisheng return 0; 5032a24f2ceSDong Aisheng } 5042a24f2ceSDong Aisheng 5052a24f2ceSDong Aisheng static int mxs_saif_prepare(struct snd_pcm_substream *substream, 5062a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 5072a24f2ceSDong Aisheng { 5082a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 5092a24f2ceSDong Aisheng 5102a24f2ceSDong Aisheng /* enable FIFO error irqs */ 5112a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 5122a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 5132a24f2ceSDong Aisheng 5142a24f2ceSDong Aisheng return 0; 5152a24f2ceSDong Aisheng } 5162a24f2ceSDong Aisheng 5172a24f2ceSDong Aisheng static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 5182a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 5192a24f2ceSDong Aisheng { 5202a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 52176067540SDong Aisheng struct mxs_saif *master_saif; 52276067540SDong Aisheng u32 delay; 523863ebddeSMarkus Pargmann int ret; 52476067540SDong Aisheng 52576067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 52676067540SDong Aisheng if (!master_saif) 52776067540SDong Aisheng return -EINVAL; 5282a24f2ceSDong Aisheng 5292a24f2ceSDong Aisheng switch (cmd) { 5302a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_START: 5312a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_RESUME: 5322a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 53388cf632aSMarkus Pargmann if (saif->state == MXS_SAIF_STATE_RUNNING) 53488cf632aSMarkus Pargmann return 0; 53588cf632aSMarkus Pargmann 5362a24f2ceSDong Aisheng dev_dbg(cpu_dai->dev, "start\n"); 5372a24f2ceSDong Aisheng 538863ebddeSMarkus Pargmann ret = clk_enable(master_saif->clk); 539863ebddeSMarkus Pargmann if (ret) { 540863ebddeSMarkus Pargmann dev_err(saif->dev, "Failed to enable master clock\n"); 541863ebddeSMarkus Pargmann return ret; 542863ebddeSMarkus Pargmann } 54376067540SDong Aisheng 54476067540SDong Aisheng /* 54505004cb4SMatthew Garrett * If the saif's master is not itself, we also need to enable 54676067540SDong Aisheng * itself clk for its internal basic logic to work. 54776067540SDong Aisheng */ 54876067540SDong Aisheng if (saif != master_saif) { 549863ebddeSMarkus Pargmann ret = clk_enable(saif->clk); 550863ebddeSMarkus Pargmann if (ret) { 551863ebddeSMarkus Pargmann dev_err(saif->dev, "Failed to enable master clock\n"); 552863ebddeSMarkus Pargmann clk_disable(master_saif->clk); 553863ebddeSMarkus Pargmann return ret; 554863ebddeSMarkus Pargmann } 555863ebddeSMarkus Pargmann 5562a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 5572a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 55876067540SDong Aisheng } 5592a24f2ceSDong Aisheng 560863ebddeSMarkus Pargmann if (!master_saif->mclk_in_use) 561863ebddeSMarkus Pargmann __raw_writel(BM_SAIF_CTRL_RUN, 562863ebddeSMarkus Pargmann master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 563863ebddeSMarkus Pargmann 5642a24f2ceSDong Aisheng if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5652a24f2ceSDong Aisheng /* 566f55f1475SFabio Estevam * write data to saif data register to trigger 567f55f1475SFabio Estevam * the transfer. 568f55f1475SFabio Estevam * For 24-bit format the 32-bit FIFO register stores 569f55f1475SFabio Estevam * only one channel, so we need to write twice. 570f55f1475SFabio Estevam * This is also safe for the other non 24-bit formats. 5712a24f2ceSDong Aisheng */ 5722a24f2ceSDong Aisheng __raw_writel(0, saif->base + SAIF_DATA); 573f55f1475SFabio Estevam __raw_writel(0, saif->base + SAIF_DATA); 5742a24f2ceSDong Aisheng } else { 5752a24f2ceSDong Aisheng /* 576f55f1475SFabio Estevam * read data from saif data register to trigger 577f55f1475SFabio Estevam * the receive. 578f55f1475SFabio Estevam * For 24-bit format the 32-bit FIFO register stores 579f55f1475SFabio Estevam * only one channel, so we need to read twice. 580f55f1475SFabio Estevam * This is also safe for the other non 24-bit formats. 5812a24f2ceSDong Aisheng */ 5822a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_DATA); 583f55f1475SFabio Estevam __raw_readl(saif->base + SAIF_DATA); 5842a24f2ceSDong Aisheng } 5852a24f2ceSDong Aisheng 58676067540SDong Aisheng master_saif->ongoing = 1; 58788cf632aSMarkus Pargmann saif->state = MXS_SAIF_STATE_RUNNING; 58876067540SDong Aisheng 58976067540SDong Aisheng dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 5902a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_CTRL), 5912a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_STAT)); 5922a24f2ceSDong Aisheng 59376067540SDong Aisheng dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 59476067540SDong Aisheng __raw_readl(master_saif->base + SAIF_CTRL), 59576067540SDong Aisheng __raw_readl(master_saif->base + SAIF_STAT)); 5962a24f2ceSDong Aisheng break; 5972a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_SUSPEND: 5982a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_STOP: 5992a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 60088cf632aSMarkus Pargmann if (saif->state == MXS_SAIF_STATE_STOPPED) 60188cf632aSMarkus Pargmann return 0; 60288cf632aSMarkus Pargmann 6032a24f2ceSDong Aisheng dev_dbg(cpu_dai->dev, "stop\n"); 6042a24f2ceSDong Aisheng 60576067540SDong Aisheng /* wait a while for the current sample to complete */ 60676067540SDong Aisheng delay = USEC_PER_SEC / master_saif->cur_rate; 60776067540SDong Aisheng 60876067540SDong Aisheng if (!master_saif->mclk_in_use) { 60976067540SDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 61076067540SDong Aisheng master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 61176067540SDong Aisheng udelay(delay); 61276067540SDong Aisheng } 61376067540SDong Aisheng clk_disable(master_saif->clk); 61476067540SDong Aisheng 61576067540SDong Aisheng if (saif != master_saif) { 6162a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 6172a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 61876067540SDong Aisheng udelay(delay); 61976067540SDong Aisheng clk_disable(saif->clk); 62076067540SDong Aisheng } 62176067540SDong Aisheng 62276067540SDong Aisheng master_saif->ongoing = 0; 62388cf632aSMarkus Pargmann saif->state = MXS_SAIF_STATE_STOPPED; 6242a24f2ceSDong Aisheng 6252a24f2ceSDong Aisheng break; 6262a24f2ceSDong Aisheng default: 6272a24f2ceSDong Aisheng return -EINVAL; 6282a24f2ceSDong Aisheng } 6292a24f2ceSDong Aisheng 6302a24f2ceSDong Aisheng return 0; 6312a24f2ceSDong Aisheng } 6322a24f2ceSDong Aisheng 6332a24f2ceSDong Aisheng #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 6342a24f2ceSDong Aisheng #define MXS_SAIF_FORMATS \ 6352a24f2ceSDong Aisheng (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 6362a24f2ceSDong Aisheng SNDRV_PCM_FMTBIT_S24_LE) 6372a24f2ceSDong Aisheng 63885e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 6392a24f2ceSDong Aisheng .startup = mxs_saif_startup, 640f212c6d8SMans Rullgard .shutdown = mxs_saif_shutdown, 6412a24f2ceSDong Aisheng .trigger = mxs_saif_trigger, 6422a24f2ceSDong Aisheng .prepare = mxs_saif_prepare, 6432a24f2ceSDong Aisheng .hw_params = mxs_saif_hw_params, 6442a24f2ceSDong Aisheng .set_sysclk = mxs_saif_set_dai_sysclk, 645*f3c0064fSCharles Keepax .set_fmt_new = mxs_saif_set_dai_fmt, 6462a24f2ceSDong Aisheng }; 6472a24f2ceSDong Aisheng 6482a24f2ceSDong Aisheng static struct snd_soc_dai_driver mxs_saif_dai = { 6492a24f2ceSDong Aisheng .name = "mxs-saif", 6502a24f2ceSDong Aisheng .playback = { 6512a24f2ceSDong Aisheng .channels_min = 2, 6522a24f2ceSDong Aisheng .channels_max = 2, 6532a24f2ceSDong Aisheng .rates = MXS_SAIF_RATES, 6542a24f2ceSDong Aisheng .formats = MXS_SAIF_FORMATS, 6552a24f2ceSDong Aisheng }, 6562a24f2ceSDong Aisheng .capture = { 6572a24f2ceSDong Aisheng .channels_min = 2, 6582a24f2ceSDong Aisheng .channels_max = 2, 6592a24f2ceSDong Aisheng .rates = MXS_SAIF_RATES, 6602a24f2ceSDong Aisheng .formats = MXS_SAIF_FORMATS, 6612a24f2ceSDong Aisheng }, 6622a24f2ceSDong Aisheng .ops = &mxs_saif_dai_ops, 6632a24f2ceSDong Aisheng }; 6642a24f2ceSDong Aisheng 665026240bbSKuninori Morimoto static const struct snd_soc_component_driver mxs_saif_component = { 666026240bbSKuninori Morimoto .name = "mxs-saif", 667026240bbSKuninori Morimoto }; 668026240bbSKuninori Morimoto 6692a24f2ceSDong Aisheng static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 6702a24f2ceSDong Aisheng { 6712a24f2ceSDong Aisheng struct mxs_saif *saif = dev_id; 6722a24f2ceSDong Aisheng unsigned int stat; 6732a24f2ceSDong Aisheng 6742a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 6752a24f2ceSDong Aisheng if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 6762a24f2ceSDong Aisheng BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 6772a24f2ceSDong Aisheng return IRQ_NONE; 6782a24f2ceSDong Aisheng 6792a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 6802a24f2ceSDong Aisheng dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 6812a24f2ceSDong Aisheng __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 6822a24f2ceSDong Aisheng saif->base + SAIF_STAT + MXS_CLR_ADDR); 6832a24f2ceSDong Aisheng } 6842a24f2ceSDong Aisheng 6852a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 6862a24f2ceSDong Aisheng dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 6872a24f2ceSDong Aisheng __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 6882a24f2ceSDong Aisheng saif->base + SAIF_STAT + MXS_CLR_ADDR); 6892a24f2ceSDong Aisheng } 6902a24f2ceSDong Aisheng 6912a24f2ceSDong Aisheng dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 6922a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_CTRL), 6932a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_STAT)); 6942a24f2ceSDong Aisheng 6952a24f2ceSDong Aisheng return IRQ_HANDLED; 6962a24f2ceSDong Aisheng } 6972a24f2ceSDong Aisheng 6987c9e6150SShawn Guo static int mxs_saif_mclk_init(struct platform_device *pdev) 6997c9e6150SShawn Guo { 7007c9e6150SShawn Guo struct mxs_saif *saif = platform_get_drvdata(pdev); 7017c9e6150SShawn Guo struct device_node *np = pdev->dev.of_node; 7027c9e6150SShawn Guo struct clk *clk; 7037c9e6150SShawn Guo int ret; 7047c9e6150SShawn Guo 7057c9e6150SShawn Guo clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk", 7067c9e6150SShawn Guo __clk_get_name(saif->clk), 0, 7077c9e6150SShawn Guo saif->base + SAIF_CTRL, 7087c9e6150SShawn Guo BP_SAIF_CTRL_BITCLK_MULT_RATE, 3, 7097c9e6150SShawn Guo 0, NULL); 7107c9e6150SShawn Guo if (IS_ERR(clk)) { 7117c9e6150SShawn Guo ret = PTR_ERR(clk); 7127c9e6150SShawn Guo if (ret == -EEXIST) 7137c9e6150SShawn Guo return 0; 7147c9e6150SShawn Guo dev_err(&pdev->dev, "failed to register mclk: %d\n", ret); 7157c9e6150SShawn Guo return PTR_ERR(clk); 7167c9e6150SShawn Guo } 7177c9e6150SShawn Guo 7187c9e6150SShawn Guo ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); 7197c9e6150SShawn Guo if (ret) 7207c9e6150SShawn Guo return ret; 7217c9e6150SShawn Guo 7227c9e6150SShawn Guo return 0; 7237c9e6150SShawn Guo } 7247c9e6150SShawn Guo 725fd582736SBill Pemberton static int mxs_saif_probe(struct platform_device *pdev) 7262a24f2ceSDong Aisheng { 72708641c7cSShawn Guo struct device_node *np = pdev->dev.of_node; 7282a24f2ceSDong Aisheng struct mxs_saif *saif; 729da33574fSTang Bin int irq, ret; 7304498a3caSFabio Estevam struct device_node *master; 7312a24f2ceSDong Aisheng 732830eb876SJulia Lawall saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 7332a24f2ceSDong Aisheng if (!saif) 7342a24f2ceSDong Aisheng return -ENOMEM; 7352a24f2ceSDong Aisheng 736324a7fb0SFabio Estevam ret = of_alias_get_id(np, "saif"); 737324a7fb0SFabio Estevam if (ret < 0) 738324a7fb0SFabio Estevam return ret; 739324a7fb0SFabio Estevam else 740324a7fb0SFabio Estevam saif->id = ret; 741324a7fb0SFabio Estevam 742e1b790a8SAlexey Khoroshilov if (saif->id >= ARRAY_SIZE(mxs_saif)) { 743e1b790a8SAlexey Khoroshilov dev_err(&pdev->dev, "get wrong saif id\n"); 744e1b790a8SAlexey Khoroshilov return -EINVAL; 745e1b790a8SAlexey Khoroshilov } 746e1b790a8SAlexey Khoroshilov 74708641c7cSShawn Guo /* 74808641c7cSShawn Guo * If there is no "fsl,saif-master" phandle, it's a saif 74908641c7cSShawn Guo * master. Otherwise, it's a slave and its phandle points 75008641c7cSShawn Guo * to the master. 75108641c7cSShawn Guo */ 75208641c7cSShawn Guo master = of_parse_phandle(np, "fsl,saif-master", 0); 75308641c7cSShawn Guo if (!master) { 75408641c7cSShawn Guo saif->master_id = saif->id; 75508641c7cSShawn Guo } else { 756324a7fb0SFabio Estevam ret = of_alias_get_id(master, "saif"); 7572be84f73SMiaoqian Lin of_node_put(master); 758324a7fb0SFabio Estevam if (ret < 0) 759324a7fb0SFabio Estevam return ret; 760324a7fb0SFabio Estevam else 761324a7fb0SFabio Estevam saif->master_id = ret; 76208641c7cSShawn Guo 763324a7fb0SFabio Estevam if (saif->master_id >= ARRAY_SIZE(mxs_saif)) { 76477882580SDong Aisheng dev_err(&pdev->dev, "get wrong master id\n"); 76576067540SDong Aisheng return -EINVAL; 76676067540SDong Aisheng } 767e1b790a8SAlexey Khoroshilov } 76808641c7cSShawn Guo 76908641c7cSShawn Guo mxs_saif[saif->id] = saif; 7702a24f2ceSDong Aisheng 771730963f8SFabio Estevam saif->clk = devm_clk_get(&pdev->dev, NULL); 7722a24f2ceSDong Aisheng if (IS_ERR(saif->clk)) { 7732a24f2ceSDong Aisheng ret = PTR_ERR(saif->clk); 7742a24f2ceSDong Aisheng dev_err(&pdev->dev, "Cannot get the clock: %d\n", 7752a24f2ceSDong Aisheng ret); 776830eb876SJulia Lawall return ret; 7772a24f2ceSDong Aisheng } 7782a24f2ceSDong Aisheng 7791327bfe2SYueHaibing saif->base = devm_platform_ioremap_resource(pdev, 0); 780b25b5aa0SThierry Reding if (IS_ERR(saif->base)) 781b25b5aa0SThierry Reding return PTR_ERR(saif->base); 7822a24f2ceSDong Aisheng 7835396ecf7SFabio Estevam irq = platform_get_irq(pdev, 0); 784cf9441adSStephen Boyd if (irq < 0) 785cf9441adSStephen Boyd return irq; 7862a24f2ceSDong Aisheng 7872a24f2ceSDong Aisheng saif->dev = &pdev->dev; 7885396ecf7SFabio Estevam ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0, 7898c2727f9SFabio Estevam dev_name(&pdev->dev), saif); 7902a24f2ceSDong Aisheng if (ret) { 7912a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to request irq\n"); 792730963f8SFabio Estevam return ret; 7932a24f2ceSDong Aisheng } 7942a24f2ceSDong Aisheng 7952a24f2ceSDong Aisheng platform_set_drvdata(pdev, saif); 7962a24f2ceSDong Aisheng 7977c9e6150SShawn Guo /* We only support saif0 being tx and clock master */ 7987c9e6150SShawn Guo if (saif->id == 0) { 7997c9e6150SShawn Guo ret = mxs_saif_mclk_init(pdev); 8007c9e6150SShawn Guo if (ret) 8017c9e6150SShawn Guo dev_warn(&pdev->dev, "failed to init clocks\n"); 8027c9e6150SShawn Guo } 8037c9e6150SShawn Guo 804fcd70eb5SSachin Kamat ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component, 805026240bbSKuninori Morimoto &mxs_saif_dai, 1); 8062a24f2ceSDong Aisheng if (ret) { 8072a24f2ceSDong Aisheng dev_err(&pdev->dev, "register DAI failed\n"); 808730963f8SFabio Estevam return ret; 8092a24f2ceSDong Aisheng } 8102a24f2ceSDong Aisheng 8114da3fe78SShawn Guo ret = mxs_pcm_platform_register(&pdev->dev); 8122a24f2ceSDong Aisheng if (ret) { 8134da3fe78SShawn Guo dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 814fcd70eb5SSachin Kamat return ret; 8152a24f2ceSDong Aisheng } 8162a24f2ceSDong Aisheng 8172a24f2ceSDong Aisheng return 0; 8182a24f2ceSDong Aisheng } 8192a24f2ceSDong Aisheng 82008641c7cSShawn Guo static const struct of_device_id mxs_saif_dt_ids[] = { 82108641c7cSShawn Guo { .compatible = "fsl,imx28-saif", }, 82208641c7cSShawn Guo { /* sentinel */ } 82308641c7cSShawn Guo }; 82408641c7cSShawn Guo MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 82508641c7cSShawn Guo 8262a24f2ceSDong Aisheng static struct platform_driver mxs_saif_driver = { 8272a24f2ceSDong Aisheng .probe = mxs_saif_probe, 8282a24f2ceSDong Aisheng 8292a24f2ceSDong Aisheng .driver = { 8302a24f2ceSDong Aisheng .name = "mxs-saif", 83108641c7cSShawn Guo .of_match_table = mxs_saif_dt_ids, 8322a24f2ceSDong Aisheng }, 8332a24f2ceSDong Aisheng }; 8342a24f2ceSDong Aisheng 83585aa0960SAxel Lin module_platform_driver(mxs_saif_driver); 8362a24f2ceSDong Aisheng 8372a24f2ceSDong Aisheng MODULE_AUTHOR("Freescale Semiconductor, Inc."); 8382a24f2ceSDong Aisheng MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 8392a24f2ceSDong Aisheng MODULE_LICENSE("GPL"); 8409f4c3f1cSFabio Estevam MODULE_ALIAS("platform:mxs-saif"); 841