12a24f2ceSDong Aisheng /* 22a24f2ceSDong Aisheng * Copyright 2011 Freescale Semiconductor, Inc. 32a24f2ceSDong Aisheng * 42a24f2ceSDong Aisheng * This program is free software; you can redistribute it and/or modify 52a24f2ceSDong Aisheng * it under the terms of the GNU General Public License as published by 62a24f2ceSDong Aisheng * the Free Software Foundation; either version 2 of the License, or 72a24f2ceSDong Aisheng * (at your option) any later version. 82a24f2ceSDong Aisheng * 92a24f2ceSDong Aisheng * This program is distributed in the hope that it will be useful, 102a24f2ceSDong Aisheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 112a24f2ceSDong Aisheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122a24f2ceSDong Aisheng * GNU General Public License for more details. 132a24f2ceSDong Aisheng * 142a24f2ceSDong Aisheng * You should have received a copy of the GNU General Public License along 152a24f2ceSDong Aisheng * with this program; if not, write to the Free Software Foundation, Inc., 162a24f2ceSDong Aisheng * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 172a24f2ceSDong Aisheng */ 182a24f2ceSDong Aisheng 192a24f2ceSDong Aisheng #include <linux/module.h> 202a24f2ceSDong Aisheng #include <linux/init.h> 2108641c7cSShawn Guo #include <linux/of.h> 2208641c7cSShawn Guo #include <linux/of_device.h> 232a24f2ceSDong Aisheng #include <linux/platform_device.h> 242a24f2ceSDong Aisheng #include <linux/slab.h> 252a24f2ceSDong Aisheng #include <linux/dma-mapping.h> 262a24f2ceSDong Aisheng #include <linux/clk.h> 272a24f2ceSDong Aisheng #include <linux/delay.h> 2876067540SDong Aisheng #include <linux/time.h> 2939468604SHuang Shijie #include <linux/fsl/mxs-dma.h> 30f755865fSShawn Guo #include <linux/pinctrl/consumer.h> 312a24f2ceSDong Aisheng #include <sound/core.h> 322a24f2ceSDong Aisheng #include <sound/pcm.h> 332a24f2ceSDong Aisheng #include <sound/pcm_params.h> 342a24f2ceSDong Aisheng #include <sound/soc.h> 3576067540SDong Aisheng #include <sound/saif.h> 362a24f2ceSDong Aisheng #include <asm/mach-types.h> 372a24f2ceSDong Aisheng #include <mach/hardware.h> 382a24f2ceSDong Aisheng #include <mach/mxs.h> 392a24f2ceSDong Aisheng 402a24f2ceSDong Aisheng #include "mxs-saif.h" 412a24f2ceSDong Aisheng 422a24f2ceSDong Aisheng static struct mxs_saif *mxs_saif[2]; 432a24f2ceSDong Aisheng 4476067540SDong Aisheng /* 4576067540SDong Aisheng * SAIF is a little different with other normal SOC DAIs on clock using. 4676067540SDong Aisheng * 4776067540SDong Aisheng * For MXS, two SAIF modules are instantiated on-chip. 4876067540SDong Aisheng * Each SAIF has a set of clock pins and can be operating in master 4976067540SDong Aisheng * mode simultaneously if they are connected to different off-chip codecs. 5076067540SDong Aisheng * Also, one of the two SAIFs can master or drive the clock pins while the 5176067540SDong Aisheng * other SAIF, in slave mode, receives clocking from the master SAIF. 5276067540SDong Aisheng * This also means that both SAIFs must operate at the same sample rate. 5376067540SDong Aisheng * 5476067540SDong Aisheng * We abstract this as each saif has a master, the master could be 5576067540SDong Aisheng * himself or other saifs. In the generic saif driver, saif does not need 5676067540SDong Aisheng * to know the different clkmux. Saif only needs to know who is his master 5776067540SDong Aisheng * and operating his master to generate the proper clock rate for him. 5876067540SDong Aisheng * The master id is provided in mach-specific layer according to different 5976067540SDong Aisheng * clkmux setting. 6076067540SDong Aisheng */ 6176067540SDong Aisheng 622a24f2ceSDong Aisheng static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 632a24f2ceSDong Aisheng int clk_id, unsigned int freq, int dir) 642a24f2ceSDong Aisheng { 652a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 662a24f2ceSDong Aisheng 672a24f2ceSDong Aisheng switch (clk_id) { 682a24f2ceSDong Aisheng case MXS_SAIF_MCLK: 692a24f2ceSDong Aisheng saif->mclk = freq; 702a24f2ceSDong Aisheng break; 712a24f2ceSDong Aisheng default: 722a24f2ceSDong Aisheng return -EINVAL; 732a24f2ceSDong Aisheng } 742a24f2ceSDong Aisheng return 0; 752a24f2ceSDong Aisheng } 762a24f2ceSDong Aisheng 772a24f2ceSDong Aisheng /* 7876067540SDong Aisheng * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 7976067540SDong Aisheng * is provided by other SAIF, we provide a interface here to get its master 8076067540SDong Aisheng * from its master_id. 8176067540SDong Aisheng * Note that the master could be himself. 8276067540SDong Aisheng */ 8376067540SDong Aisheng static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 8476067540SDong Aisheng { 8576067540SDong Aisheng return mxs_saif[saif->master_id]; 8676067540SDong Aisheng } 8776067540SDong Aisheng 8876067540SDong Aisheng /* 892a24f2ceSDong Aisheng * Set SAIF clock and MCLK 902a24f2ceSDong Aisheng */ 912a24f2ceSDong Aisheng static int mxs_saif_set_clk(struct mxs_saif *saif, 922a24f2ceSDong Aisheng unsigned int mclk, 932a24f2ceSDong Aisheng unsigned int rate) 942a24f2ceSDong Aisheng { 952a24f2ceSDong Aisheng u32 scr; 962a24f2ceSDong Aisheng int ret; 9776067540SDong Aisheng struct mxs_saif *master_saif; 982a24f2ceSDong Aisheng 9976067540SDong Aisheng dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 10076067540SDong Aisheng 10176067540SDong Aisheng /* Set master saif to generate proper clock */ 10276067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 10376067540SDong Aisheng if (!master_saif) 10476067540SDong Aisheng return -EINVAL; 10576067540SDong Aisheng 10676067540SDong Aisheng dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 10776067540SDong Aisheng 10876067540SDong Aisheng /* Checking if can playback and capture simutaneously */ 10976067540SDong Aisheng if (master_saif->ongoing && rate != master_saif->cur_rate) { 11076067540SDong Aisheng dev_err(saif->dev, 11176067540SDong Aisheng "can not change clock, master saif%d(rate %d) is ongoing\n", 11276067540SDong Aisheng master_saif->id, master_saif->cur_rate); 11376067540SDong Aisheng return -EINVAL; 11476067540SDong Aisheng } 11576067540SDong Aisheng 11676067540SDong Aisheng scr = __raw_readl(master_saif->base + SAIF_CTRL); 1172a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 1182a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 1192a24f2ceSDong Aisheng 1202a24f2ceSDong Aisheng /* 1212a24f2ceSDong Aisheng * Set SAIF clock 1222a24f2ceSDong Aisheng * 1232a24f2ceSDong Aisheng * The SAIF clock should be either 384*fs or 512*fs. 1242a24f2ceSDong Aisheng * If MCLK is used, the SAIF clk ratio need to match mclk ratio. 1252a24f2ceSDong Aisheng * For 32x mclk, set saif clk as 512*fs. 1262a24f2ceSDong Aisheng * For 48x mclk, set saif clk as 384*fs. 1272a24f2ceSDong Aisheng * 1282a24f2ceSDong Aisheng * If MCLK is not used, we just set saif clk to 512*fs. 1292a24f2ceSDong Aisheng */ 1306b35f924SFabio Estevam clk_prepare_enable(master_saif->clk); 1316b35f924SFabio Estevam 13276067540SDong Aisheng if (master_saif->mclk_in_use) { 1332a24f2ceSDong Aisheng if (mclk % 32 == 0) { 1342a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 13576067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 512 * rate); 1362a24f2ceSDong Aisheng } else if (mclk % 48 == 0) { 1372a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 13876067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 384 * rate); 1392a24f2ceSDong Aisheng } else { 1402a24f2ceSDong Aisheng /* SAIF MCLK should be either 32x or 48x */ 1416b35f924SFabio Estevam clk_disable_unprepare(master_saif->clk); 1422a24f2ceSDong Aisheng return -EINVAL; 1432a24f2ceSDong Aisheng } 1442a24f2ceSDong Aisheng } else { 14576067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 512 * rate); 1462a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 1472a24f2ceSDong Aisheng } 1482a24f2ceSDong Aisheng 1496b35f924SFabio Estevam clk_disable_unprepare(master_saif->clk); 1506b35f924SFabio Estevam 1512a24f2ceSDong Aisheng if (ret) 1522a24f2ceSDong Aisheng return ret; 1532a24f2ceSDong Aisheng 15476067540SDong Aisheng master_saif->cur_rate = rate; 15576067540SDong Aisheng 15676067540SDong Aisheng if (!master_saif->mclk_in_use) { 15776067540SDong Aisheng __raw_writel(scr, master_saif->base + SAIF_CTRL); 1582a24f2ceSDong Aisheng return 0; 1592a24f2ceSDong Aisheng } 1602a24f2ceSDong Aisheng 1612a24f2ceSDong Aisheng /* 1622a24f2ceSDong Aisheng * Program the over-sample rate for MCLK output 1632a24f2ceSDong Aisheng * 1642a24f2ceSDong Aisheng * The available MCLK range is 32x, 48x... 512x. The rate 1652a24f2ceSDong Aisheng * could be from 8kHz to 192kH. 1662a24f2ceSDong Aisheng */ 1672a24f2ceSDong Aisheng switch (mclk / rate) { 1682a24f2ceSDong Aisheng case 32: 1692a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 1702a24f2ceSDong Aisheng break; 1712a24f2ceSDong Aisheng case 64: 1722a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 1732a24f2ceSDong Aisheng break; 1742a24f2ceSDong Aisheng case 128: 1752a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 1762a24f2ceSDong Aisheng break; 1772a24f2ceSDong Aisheng case 256: 1782a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 1792a24f2ceSDong Aisheng break; 1802a24f2ceSDong Aisheng case 512: 1812a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 1822a24f2ceSDong Aisheng break; 1832a24f2ceSDong Aisheng case 48: 1842a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 1852a24f2ceSDong Aisheng break; 1862a24f2ceSDong Aisheng case 96: 1872a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 1882a24f2ceSDong Aisheng break; 1892a24f2ceSDong Aisheng case 192: 1902a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 1912a24f2ceSDong Aisheng break; 1922a24f2ceSDong Aisheng case 384: 1932a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 1942a24f2ceSDong Aisheng break; 1952a24f2ceSDong Aisheng default: 1962a24f2ceSDong Aisheng return -EINVAL; 1972a24f2ceSDong Aisheng } 1982a24f2ceSDong Aisheng 19976067540SDong Aisheng __raw_writel(scr, master_saif->base + SAIF_CTRL); 2002a24f2ceSDong Aisheng 2012a24f2ceSDong Aisheng return 0; 2022a24f2ceSDong Aisheng } 2032a24f2ceSDong Aisheng 2042a24f2ceSDong Aisheng /* 2052a24f2ceSDong Aisheng * Put and disable MCLK. 2062a24f2ceSDong Aisheng */ 2072a24f2ceSDong Aisheng int mxs_saif_put_mclk(unsigned int saif_id) 2082a24f2ceSDong Aisheng { 2092a24f2ceSDong Aisheng struct mxs_saif *saif = mxs_saif[saif_id]; 2102a24f2ceSDong Aisheng u32 stat; 2112a24f2ceSDong Aisheng 2122a24f2ceSDong Aisheng if (!saif) 2132a24f2ceSDong Aisheng return -EINVAL; 2142a24f2ceSDong Aisheng 2152a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2162a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2172a24f2ceSDong Aisheng dev_err(saif->dev, "error: busy\n"); 2182a24f2ceSDong Aisheng return -EBUSY; 2192a24f2ceSDong Aisheng } 2202a24f2ceSDong Aisheng 22167939b22SShawn Guo clk_disable_unprepare(saif->clk); 2222a24f2ceSDong Aisheng 2232a24f2ceSDong Aisheng /* disable MCLK output */ 2242a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 2252a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 2262a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 2272a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 2282a24f2ceSDong Aisheng 2292a24f2ceSDong Aisheng saif->mclk_in_use = 0; 2302a24f2ceSDong Aisheng return 0; 2312a24f2ceSDong Aisheng } 2322a24f2ceSDong Aisheng 2332a24f2ceSDong Aisheng /* 2342a24f2ceSDong Aisheng * Get MCLK and set clock rate, then enable it 2352a24f2ceSDong Aisheng * 2362a24f2ceSDong Aisheng * This interface is used for codecs who are using MCLK provided 2372a24f2ceSDong Aisheng * by saif. 2382a24f2ceSDong Aisheng */ 2392a24f2ceSDong Aisheng int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 2402a24f2ceSDong Aisheng unsigned int rate) 2412a24f2ceSDong Aisheng { 2422a24f2ceSDong Aisheng struct mxs_saif *saif = mxs_saif[saif_id]; 2432a24f2ceSDong Aisheng u32 stat; 2442a24f2ceSDong Aisheng int ret; 24576067540SDong Aisheng struct mxs_saif *master_saif; 2462a24f2ceSDong Aisheng 2472a24f2ceSDong Aisheng if (!saif) 2482a24f2ceSDong Aisheng return -EINVAL; 2492a24f2ceSDong Aisheng 250bbe8ff5eSDong Aisheng /* Clear Reset */ 251bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_SFTRST, 252bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 253bbe8ff5eSDong Aisheng 254bbe8ff5eSDong Aisheng /* FIXME: need clear clk gate for register r/w */ 255bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 256bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 257bbe8ff5eSDong Aisheng 25876067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 25976067540SDong Aisheng if (saif != master_saif) { 26076067540SDong Aisheng dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 26176067540SDong Aisheng return -EINVAL; 26276067540SDong Aisheng } 26376067540SDong Aisheng 2642a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2652a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2662a24f2ceSDong Aisheng dev_err(saif->dev, "error: busy\n"); 2672a24f2ceSDong Aisheng return -EBUSY; 2682a24f2ceSDong Aisheng } 2692a24f2ceSDong Aisheng 2702a24f2ceSDong Aisheng saif->mclk_in_use = 1; 2712a24f2ceSDong Aisheng ret = mxs_saif_set_clk(saif, mclk, rate); 2722a24f2ceSDong Aisheng if (ret) 2732a24f2ceSDong Aisheng return ret; 2742a24f2ceSDong Aisheng 27567939b22SShawn Guo ret = clk_prepare_enable(saif->clk); 2762a24f2ceSDong Aisheng if (ret) 2772a24f2ceSDong Aisheng return ret; 2782a24f2ceSDong Aisheng 2792a24f2ceSDong Aisheng /* enable MCLK output */ 2802a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 2812a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 2822a24f2ceSDong Aisheng 2832a24f2ceSDong Aisheng return 0; 2842a24f2ceSDong Aisheng } 2852a24f2ceSDong Aisheng 2862a24f2ceSDong Aisheng /* 2872a24f2ceSDong Aisheng * SAIF DAI format configuration. 2882a24f2ceSDong Aisheng * Should only be called when port is inactive. 2892a24f2ceSDong Aisheng */ 2902a24f2ceSDong Aisheng static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 2912a24f2ceSDong Aisheng { 2922a24f2ceSDong Aisheng u32 scr, stat; 2932a24f2ceSDong Aisheng u32 scr0; 2942a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 2952a24f2ceSDong Aisheng 2962a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2972a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2982a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "error: busy\n"); 2992a24f2ceSDong Aisheng return -EBUSY; 3002a24f2ceSDong Aisheng } 3012a24f2ceSDong Aisheng 3022a24f2ceSDong Aisheng scr0 = __raw_readl(saif->base + SAIF_CTRL); 3032a24f2ceSDong Aisheng scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 3042a24f2ceSDong Aisheng & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 3052a24f2ceSDong Aisheng scr = 0; 3062a24f2ceSDong Aisheng 3072a24f2ceSDong Aisheng /* DAI mode */ 3082a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3092a24f2ceSDong Aisheng case SND_SOC_DAIFMT_I2S: 3102a24f2ceSDong Aisheng /* data frame low 1clk before data */ 3112a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_DELAY; 3122a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3132a24f2ceSDong Aisheng break; 3142a24f2ceSDong Aisheng case SND_SOC_DAIFMT_LEFT_J: 3152a24f2ceSDong Aisheng /* data frame high with data */ 3162a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_DELAY; 3172a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3182a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_JUSTIFY; 3192a24f2ceSDong Aisheng break; 3202a24f2ceSDong Aisheng default: 3212a24f2ceSDong Aisheng return -EINVAL; 3222a24f2ceSDong Aisheng } 3232a24f2ceSDong Aisheng 3242a24f2ceSDong Aisheng /* DAI clock inversion */ 3252a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3262a24f2ceSDong Aisheng case SND_SOC_DAIFMT_IB_IF: 3272a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_EDGE; 3282a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 3292a24f2ceSDong Aisheng break; 3302a24f2ceSDong Aisheng case SND_SOC_DAIFMT_IB_NF: 3312a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_EDGE; 3322a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3332a24f2ceSDong Aisheng break; 3342a24f2ceSDong Aisheng case SND_SOC_DAIFMT_NB_IF: 3352a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 3362a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 3372a24f2ceSDong Aisheng break; 3382a24f2ceSDong Aisheng case SND_SOC_DAIFMT_NB_NF: 3392a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 3402a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3412a24f2ceSDong Aisheng break; 3422a24f2ceSDong Aisheng } 3432a24f2ceSDong Aisheng 3442a24f2ceSDong Aisheng /* 3452a24f2ceSDong Aisheng * Note: We simply just support master mode since SAIF TX can only 3462a24f2ceSDong Aisheng * work as master. 34776067540SDong Aisheng * Here the master is relative to codec side. 34876067540SDong Aisheng * Saif internally could be slave when working on EXTMASTER mode. 34976067540SDong Aisheng * We just hide this to machine driver. 3502a24f2ceSDong Aisheng */ 3512a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3522a24f2ceSDong Aisheng case SND_SOC_DAIFMT_CBS_CFS: 35376067540SDong Aisheng if (saif->id == saif->master_id) 3542a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 35576067540SDong Aisheng else 35676067540SDong Aisheng scr |= BM_SAIF_CTRL_SLAVE_MODE; 35776067540SDong Aisheng 3582a24f2ceSDong Aisheng __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 3592a24f2ceSDong Aisheng break; 3602a24f2ceSDong Aisheng default: 3612a24f2ceSDong Aisheng return -EINVAL; 3622a24f2ceSDong Aisheng } 3632a24f2ceSDong Aisheng 3642a24f2ceSDong Aisheng return 0; 3652a24f2ceSDong Aisheng } 3662a24f2ceSDong Aisheng 3672a24f2ceSDong Aisheng static int mxs_saif_startup(struct snd_pcm_substream *substream, 3682a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 3692a24f2ceSDong Aisheng { 3702a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 3712a24f2ceSDong Aisheng snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param); 3722a24f2ceSDong Aisheng 3732a24f2ceSDong Aisheng /* clear error status to 0 for each re-open */ 3742a24f2ceSDong Aisheng saif->fifo_underrun = 0; 3752a24f2ceSDong Aisheng saif->fifo_overrun = 0; 3762a24f2ceSDong Aisheng 3772a24f2ceSDong Aisheng /* Clear Reset for normal operations */ 3782a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_SFTRST, 3792a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 3802a24f2ceSDong Aisheng 381bbe8ff5eSDong Aisheng /* clear clock gate */ 382bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 383bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 384bbe8ff5eSDong Aisheng 3852a24f2ceSDong Aisheng return 0; 3862a24f2ceSDong Aisheng } 3872a24f2ceSDong Aisheng 3882a24f2ceSDong Aisheng /* 3892a24f2ceSDong Aisheng * Should only be called when port is inactive. 3902a24f2ceSDong Aisheng * although can be called multiple times by upper layers. 3912a24f2ceSDong Aisheng */ 3922a24f2ceSDong Aisheng static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 3932a24f2ceSDong Aisheng struct snd_pcm_hw_params *params, 3942a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 3952a24f2ceSDong Aisheng { 3962a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 397c2e1d907SDong Aisheng struct mxs_saif *master_saif; 3982a24f2ceSDong Aisheng u32 scr, stat; 3992a24f2ceSDong Aisheng int ret; 4002a24f2ceSDong Aisheng 401c2e1d907SDong Aisheng master_saif = mxs_saif_get_master(saif); 402c2e1d907SDong Aisheng if (!master_saif) 403c2e1d907SDong Aisheng return -EINVAL; 404c2e1d907SDong Aisheng 4052a24f2ceSDong Aisheng /* mclk should already be set */ 4062a24f2ceSDong Aisheng if (!saif->mclk && saif->mclk_in_use) { 4072a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "set mclk first\n"); 4082a24f2ceSDong Aisheng return -EINVAL; 4092a24f2ceSDong Aisheng } 4102a24f2ceSDong Aisheng 4112a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 4122a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 4132a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "error: busy\n"); 4142a24f2ceSDong Aisheng return -EBUSY; 4152a24f2ceSDong Aisheng } 4162a24f2ceSDong Aisheng 4172a24f2ceSDong Aisheng /* 4182a24f2ceSDong Aisheng * Set saif clk based on sample rate. 4192a24f2ceSDong Aisheng * If mclk is used, we also set mclk, if not, saif->mclk is 4202a24f2ceSDong Aisheng * default 0, means not used. 4212a24f2ceSDong Aisheng */ 4222a24f2ceSDong Aisheng ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 4232a24f2ceSDong Aisheng if (ret) { 4242a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "unable to get proper clk\n"); 4252a24f2ceSDong Aisheng return ret; 4262a24f2ceSDong Aisheng } 4272a24f2ceSDong Aisheng 428c2e1d907SDong Aisheng /* prepare clk in hw_param, enable in trigger */ 429c2e1d907SDong Aisheng clk_prepare(saif->clk); 430c2e1d907SDong Aisheng if (saif != master_saif) 431c2e1d907SDong Aisheng clk_prepare(master_saif->clk); 432c2e1d907SDong Aisheng 4332a24f2ceSDong Aisheng scr = __raw_readl(saif->base + SAIF_CTRL); 4342a24f2ceSDong Aisheng 4352a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 4362a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4372a24f2ceSDong Aisheng switch (params_format(params)) { 4382a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S16_LE: 4392a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 4402a24f2ceSDong Aisheng break; 4412a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S20_3LE: 4422a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 4432a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4442a24f2ceSDong Aisheng break; 4452a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S24_LE: 4462a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 4472a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4482a24f2ceSDong Aisheng break; 4492a24f2ceSDong Aisheng default: 4502a24f2ceSDong Aisheng return -EINVAL; 4512a24f2ceSDong Aisheng } 4522a24f2ceSDong Aisheng 4532a24f2ceSDong Aisheng /* Tx/Rx config */ 4542a24f2ceSDong Aisheng if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 4552a24f2ceSDong Aisheng /* enable TX mode */ 4562a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_READ_MODE; 4572a24f2ceSDong Aisheng } else { 4582a24f2ceSDong Aisheng /* enable RX mode */ 4592a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_READ_MODE; 4602a24f2ceSDong Aisheng } 4612a24f2ceSDong Aisheng 4622a24f2ceSDong Aisheng __raw_writel(scr, saif->base + SAIF_CTRL); 4632a24f2ceSDong Aisheng return 0; 4642a24f2ceSDong Aisheng } 4652a24f2ceSDong Aisheng 4662a24f2ceSDong Aisheng static int mxs_saif_prepare(struct snd_pcm_substream *substream, 4672a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 4682a24f2ceSDong Aisheng { 4692a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 4702a24f2ceSDong Aisheng 4712a24f2ceSDong Aisheng /* enable FIFO error irqs */ 4722a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 4732a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 4742a24f2ceSDong Aisheng 4752a24f2ceSDong Aisheng return 0; 4762a24f2ceSDong Aisheng } 4772a24f2ceSDong Aisheng 4782a24f2ceSDong Aisheng static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 4792a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 4802a24f2ceSDong Aisheng { 4812a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 48276067540SDong Aisheng struct mxs_saif *master_saif; 48376067540SDong Aisheng u32 delay; 48476067540SDong Aisheng 48576067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 48676067540SDong Aisheng if (!master_saif) 48776067540SDong Aisheng return -EINVAL; 4882a24f2ceSDong Aisheng 4892a24f2ceSDong Aisheng switch (cmd) { 4902a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_START: 4912a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_RESUME: 4922a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 4932a24f2ceSDong Aisheng dev_dbg(cpu_dai->dev, "start\n"); 4942a24f2ceSDong Aisheng 49576067540SDong Aisheng clk_enable(master_saif->clk); 49676067540SDong Aisheng if (!master_saif->mclk_in_use) 49776067540SDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 49876067540SDong Aisheng master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 49976067540SDong Aisheng 50076067540SDong Aisheng /* 50176067540SDong Aisheng * If the saif's master is not himself, we also need to enable 50276067540SDong Aisheng * itself clk for its internal basic logic to work. 50376067540SDong Aisheng */ 50476067540SDong Aisheng if (saif != master_saif) { 5052a24f2ceSDong Aisheng clk_enable(saif->clk); 5062a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 5072a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 50876067540SDong Aisheng } 5092a24f2ceSDong Aisheng 5102a24f2ceSDong Aisheng if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5112a24f2ceSDong Aisheng /* 5122a24f2ceSDong Aisheng * write a data to saif data register to trigger 5132a24f2ceSDong Aisheng * the transfer 5142a24f2ceSDong Aisheng */ 5152a24f2ceSDong Aisheng __raw_writel(0, saif->base + SAIF_DATA); 5162a24f2ceSDong Aisheng } else { 5172a24f2ceSDong Aisheng /* 5182a24f2ceSDong Aisheng * read a data from saif data register to trigger 5192a24f2ceSDong Aisheng * the receive 5202a24f2ceSDong Aisheng */ 5212a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_DATA); 5222a24f2ceSDong Aisheng } 5232a24f2ceSDong Aisheng 52476067540SDong Aisheng master_saif->ongoing = 1; 52576067540SDong Aisheng 52676067540SDong Aisheng dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 5272a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_CTRL), 5282a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_STAT)); 5292a24f2ceSDong Aisheng 53076067540SDong Aisheng dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 53176067540SDong Aisheng __raw_readl(master_saif->base + SAIF_CTRL), 53276067540SDong Aisheng __raw_readl(master_saif->base + SAIF_STAT)); 5332a24f2ceSDong Aisheng break; 5342a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_SUSPEND: 5352a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_STOP: 5362a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 5372a24f2ceSDong Aisheng dev_dbg(cpu_dai->dev, "stop\n"); 5382a24f2ceSDong Aisheng 53976067540SDong Aisheng /* wait a while for the current sample to complete */ 54076067540SDong Aisheng delay = USEC_PER_SEC / master_saif->cur_rate; 54176067540SDong Aisheng 54276067540SDong Aisheng if (!master_saif->mclk_in_use) { 54376067540SDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 54476067540SDong Aisheng master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 54576067540SDong Aisheng udelay(delay); 54676067540SDong Aisheng } 54776067540SDong Aisheng clk_disable(master_saif->clk); 54876067540SDong Aisheng 54976067540SDong Aisheng if (saif != master_saif) { 5502a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 5512a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 55276067540SDong Aisheng udelay(delay); 55376067540SDong Aisheng clk_disable(saif->clk); 55476067540SDong Aisheng } 55576067540SDong Aisheng 55676067540SDong Aisheng master_saif->ongoing = 0; 5572a24f2ceSDong Aisheng 5582a24f2ceSDong Aisheng break; 5592a24f2ceSDong Aisheng default: 5602a24f2ceSDong Aisheng return -EINVAL; 5612a24f2ceSDong Aisheng } 5622a24f2ceSDong Aisheng 5632a24f2ceSDong Aisheng return 0; 5642a24f2ceSDong Aisheng } 5652a24f2ceSDong Aisheng 5662a24f2ceSDong Aisheng #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 5672a24f2ceSDong Aisheng #define MXS_SAIF_FORMATS \ 5682a24f2ceSDong Aisheng (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 5692a24f2ceSDong Aisheng SNDRV_PCM_FMTBIT_S24_LE) 5702a24f2ceSDong Aisheng 57185e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 5722a24f2ceSDong Aisheng .startup = mxs_saif_startup, 5732a24f2ceSDong Aisheng .trigger = mxs_saif_trigger, 5742a24f2ceSDong Aisheng .prepare = mxs_saif_prepare, 5752a24f2ceSDong Aisheng .hw_params = mxs_saif_hw_params, 5762a24f2ceSDong Aisheng .set_sysclk = mxs_saif_set_dai_sysclk, 5772a24f2ceSDong Aisheng .set_fmt = mxs_saif_set_dai_fmt, 5782a24f2ceSDong Aisheng }; 5792a24f2ceSDong Aisheng 5802a24f2ceSDong Aisheng static int mxs_saif_dai_probe(struct snd_soc_dai *dai) 5812a24f2ceSDong Aisheng { 5822a24f2ceSDong Aisheng struct mxs_saif *saif = dev_get_drvdata(dai->dev); 5832a24f2ceSDong Aisheng 5842a24f2ceSDong Aisheng snd_soc_dai_set_drvdata(dai, saif); 5852a24f2ceSDong Aisheng 5862a24f2ceSDong Aisheng return 0; 5872a24f2ceSDong Aisheng } 5882a24f2ceSDong Aisheng 5892a24f2ceSDong Aisheng static struct snd_soc_dai_driver mxs_saif_dai = { 5902a24f2ceSDong Aisheng .name = "mxs-saif", 5912a24f2ceSDong Aisheng .probe = mxs_saif_dai_probe, 5922a24f2ceSDong Aisheng .playback = { 5932a24f2ceSDong Aisheng .channels_min = 2, 5942a24f2ceSDong Aisheng .channels_max = 2, 5952a24f2ceSDong Aisheng .rates = MXS_SAIF_RATES, 5962a24f2ceSDong Aisheng .formats = MXS_SAIF_FORMATS, 5972a24f2ceSDong Aisheng }, 5982a24f2ceSDong Aisheng .capture = { 5992a24f2ceSDong Aisheng .channels_min = 2, 6002a24f2ceSDong Aisheng .channels_max = 2, 6012a24f2ceSDong Aisheng .rates = MXS_SAIF_RATES, 6022a24f2ceSDong Aisheng .formats = MXS_SAIF_FORMATS, 6032a24f2ceSDong Aisheng }, 6042a24f2ceSDong Aisheng .ops = &mxs_saif_dai_ops, 6052a24f2ceSDong Aisheng }; 6062a24f2ceSDong Aisheng 6072a24f2ceSDong Aisheng static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 6082a24f2ceSDong Aisheng { 6092a24f2ceSDong Aisheng struct mxs_saif *saif = dev_id; 6102a24f2ceSDong Aisheng unsigned int stat; 6112a24f2ceSDong Aisheng 6122a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 6132a24f2ceSDong Aisheng if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 6142a24f2ceSDong Aisheng BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 6152a24f2ceSDong Aisheng return IRQ_NONE; 6162a24f2ceSDong Aisheng 6172a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 6182a24f2ceSDong Aisheng dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 6192a24f2ceSDong Aisheng __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 6202a24f2ceSDong Aisheng saif->base + SAIF_STAT + MXS_CLR_ADDR); 6212a24f2ceSDong Aisheng } 6222a24f2ceSDong Aisheng 6232a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 6242a24f2ceSDong Aisheng dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 6252a24f2ceSDong Aisheng __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 6262a24f2ceSDong Aisheng saif->base + SAIF_STAT + MXS_CLR_ADDR); 6272a24f2ceSDong Aisheng } 6282a24f2ceSDong Aisheng 6292a24f2ceSDong Aisheng dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 6302a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_CTRL), 6312a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_STAT)); 6322a24f2ceSDong Aisheng 6332a24f2ceSDong Aisheng return IRQ_HANDLED; 6342a24f2ceSDong Aisheng } 6352a24f2ceSDong Aisheng 6369d0403e8SShawn Guo static int __devinit mxs_saif_probe(struct platform_device *pdev) 6372a24f2ceSDong Aisheng { 63808641c7cSShawn Guo struct device_node *np = pdev->dev.of_node; 639226d0f22SJulia Lawall struct resource *iores, *dmares; 6402a24f2ceSDong Aisheng struct mxs_saif *saif; 64176067540SDong Aisheng struct mxs_saif_platform_data *pdata; 642f755865fSShawn Guo struct pinctrl *pinctrl; 6432a24f2ceSDong Aisheng int ret = 0; 6442a24f2ceSDong Aisheng 64508641c7cSShawn Guo 64608641c7cSShawn Guo if (!np && pdev->id >= ARRAY_SIZE(mxs_saif)) 6470bb98ba2SJulia Lawall return -EINVAL; 6480bb98ba2SJulia Lawall 649830eb876SJulia Lawall saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 6502a24f2ceSDong Aisheng if (!saif) 6512a24f2ceSDong Aisheng return -ENOMEM; 6522a24f2ceSDong Aisheng 65308641c7cSShawn Guo if (np) { 65408641c7cSShawn Guo struct device_node *master; 65508641c7cSShawn Guo saif->id = of_alias_get_id(np, "saif"); 65608641c7cSShawn Guo if (saif->id < 0) 65708641c7cSShawn Guo return saif->id; 65808641c7cSShawn Guo /* 65908641c7cSShawn Guo * If there is no "fsl,saif-master" phandle, it's a saif 66008641c7cSShawn Guo * master. Otherwise, it's a slave and its phandle points 66108641c7cSShawn Guo * to the master. 66208641c7cSShawn Guo */ 66308641c7cSShawn Guo master = of_parse_phandle(np, "fsl,saif-master", 0); 66408641c7cSShawn Guo if (!master) { 66508641c7cSShawn Guo saif->master_id = saif->id; 66608641c7cSShawn Guo } else { 66708641c7cSShawn Guo saif->master_id = of_alias_get_id(master, "saif"); 66808641c7cSShawn Guo if (saif->master_id < 0) 66908641c7cSShawn Guo return saif->master_id; 67008641c7cSShawn Guo } 67108641c7cSShawn Guo } else { 67276067540SDong Aisheng saif->id = pdev->id; 67377882580SDong Aisheng pdata = pdev->dev.platform_data; 67408641c7cSShawn Guo if (pdata && !pdata->master_mode) 67577882580SDong Aisheng saif->master_id = pdata->master_id; 67608641c7cSShawn Guo else 67708641c7cSShawn Guo saif->master_id = saif->id; 67808641c7cSShawn Guo } 67908641c7cSShawn Guo 68008641c7cSShawn Guo if (saif->master_id < 0 || saif->master_id >= ARRAY_SIZE(mxs_saif)) { 68177882580SDong Aisheng dev_err(&pdev->dev, "get wrong master id\n"); 68276067540SDong Aisheng return -EINVAL; 68376067540SDong Aisheng } 68408641c7cSShawn Guo 68508641c7cSShawn Guo mxs_saif[saif->id] = saif; 6862a24f2ceSDong Aisheng 687f755865fSShawn Guo pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 688f755865fSShawn Guo if (IS_ERR(pinctrl)) { 689f755865fSShawn Guo ret = PTR_ERR(pinctrl); 690f755865fSShawn Guo return ret; 691f755865fSShawn Guo } 692f755865fSShawn Guo 6932a24f2ceSDong Aisheng saif->clk = clk_get(&pdev->dev, NULL); 6942a24f2ceSDong Aisheng if (IS_ERR(saif->clk)) { 6952a24f2ceSDong Aisheng ret = PTR_ERR(saif->clk); 6962a24f2ceSDong Aisheng dev_err(&pdev->dev, "Cannot get the clock: %d\n", 6972a24f2ceSDong Aisheng ret); 698830eb876SJulia Lawall return ret; 6992a24f2ceSDong Aisheng } 7002a24f2ceSDong Aisheng 701226d0f22SJulia Lawall iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 7022a24f2ceSDong Aisheng 703830eb876SJulia Lawall saif->base = devm_request_and_ioremap(&pdev->dev, iores); 7042a24f2ceSDong Aisheng if (!saif->base) { 7052a24f2ceSDong Aisheng dev_err(&pdev->dev, "ioremap failed\n"); 7062a24f2ceSDong Aisheng ret = -ENODEV; 707830eb876SJulia Lawall goto failed_get_resource; 7082a24f2ceSDong Aisheng } 7092a24f2ceSDong Aisheng 710226d0f22SJulia Lawall dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 711226d0f22SJulia Lawall if (!dmares) { 71208641c7cSShawn Guo /* 71308641c7cSShawn Guo * TODO: This is a temporary solution and should be changed 71408641c7cSShawn Guo * to use generic DMA binding later when the helplers get in. 71508641c7cSShawn Guo */ 71608641c7cSShawn Guo ret = of_property_read_u32(np, "fsl,saif-dma-channel", 71708641c7cSShawn Guo &saif->dma_param.chan_num); 71808641c7cSShawn Guo if (ret) { 71908641c7cSShawn Guo dev_err(&pdev->dev, "failed to get dma channel\n"); 720830eb876SJulia Lawall goto failed_get_resource; 7212a24f2ceSDong Aisheng } 72208641c7cSShawn Guo } else { 723226d0f22SJulia Lawall saif->dma_param.chan_num = dmares->start; 72408641c7cSShawn Guo } 7252a24f2ceSDong Aisheng 7262a24f2ceSDong Aisheng saif->irq = platform_get_irq(pdev, 0); 7272a24f2ceSDong Aisheng if (saif->irq < 0) { 7282a24f2ceSDong Aisheng ret = saif->irq; 7292a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to get irq resource: %d\n", 7302a24f2ceSDong Aisheng ret); 731830eb876SJulia Lawall goto failed_get_resource; 7322a24f2ceSDong Aisheng } 7332a24f2ceSDong Aisheng 7342a24f2ceSDong Aisheng saif->dev = &pdev->dev; 735830eb876SJulia Lawall ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0, 736830eb876SJulia Lawall "mxs-saif", saif); 7372a24f2ceSDong Aisheng if (ret) { 7382a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to request irq\n"); 739830eb876SJulia Lawall goto failed_get_resource; 7402a24f2ceSDong Aisheng } 7412a24f2ceSDong Aisheng 7422a24f2ceSDong Aisheng saif->dma_param.chan_irq = platform_get_irq(pdev, 1); 7432a24f2ceSDong Aisheng if (saif->dma_param.chan_irq < 0) { 7442a24f2ceSDong Aisheng ret = saif->dma_param.chan_irq; 7452a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to get dma irq resource: %d\n", 7462a24f2ceSDong Aisheng ret); 747830eb876SJulia Lawall goto failed_get_resource; 7482a24f2ceSDong Aisheng } 7492a24f2ceSDong Aisheng 7502a24f2ceSDong Aisheng platform_set_drvdata(pdev, saif); 7512a24f2ceSDong Aisheng 7522a24f2ceSDong Aisheng ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai); 7532a24f2ceSDong Aisheng if (ret) { 7542a24f2ceSDong Aisheng dev_err(&pdev->dev, "register DAI failed\n"); 755830eb876SJulia Lawall goto failed_get_resource; 7562a24f2ceSDong Aisheng } 7572a24f2ceSDong Aisheng 7584da3fe78SShawn Guo ret = mxs_pcm_platform_register(&pdev->dev); 7592a24f2ceSDong Aisheng if (ret) { 7604da3fe78SShawn Guo dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 7614da3fe78SShawn Guo goto failed_pdev_alloc; 7622a24f2ceSDong Aisheng } 7632a24f2ceSDong Aisheng 7642a24f2ceSDong Aisheng return 0; 7652a24f2ceSDong Aisheng 7662a24f2ceSDong Aisheng failed_pdev_alloc: 7672a24f2ceSDong Aisheng snd_soc_unregister_dai(&pdev->dev); 7682a24f2ceSDong Aisheng failed_get_resource: 7692a24f2ceSDong Aisheng clk_put(saif->clk); 7702a24f2ceSDong Aisheng 7712a24f2ceSDong Aisheng return ret; 7722a24f2ceSDong Aisheng } 7732a24f2ceSDong Aisheng 7742a24f2ceSDong Aisheng static int __devexit mxs_saif_remove(struct platform_device *pdev) 7752a24f2ceSDong Aisheng { 7762a24f2ceSDong Aisheng struct mxs_saif *saif = platform_get_drvdata(pdev); 7772a24f2ceSDong Aisheng 7784da3fe78SShawn Guo mxs_pcm_platform_unregister(&pdev->dev); 7792a24f2ceSDong Aisheng snd_soc_unregister_dai(&pdev->dev); 7802a24f2ceSDong Aisheng clk_put(saif->clk); 7812a24f2ceSDong Aisheng 7822a24f2ceSDong Aisheng return 0; 7832a24f2ceSDong Aisheng } 7842a24f2ceSDong Aisheng 78508641c7cSShawn Guo static const struct of_device_id mxs_saif_dt_ids[] = { 78608641c7cSShawn Guo { .compatible = "fsl,imx28-saif", }, 78708641c7cSShawn Guo { /* sentinel */ } 78808641c7cSShawn Guo }; 78908641c7cSShawn Guo MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 79008641c7cSShawn Guo 7912a24f2ceSDong Aisheng static struct platform_driver mxs_saif_driver = { 7922a24f2ceSDong Aisheng .probe = mxs_saif_probe, 7932a24f2ceSDong Aisheng .remove = __devexit_p(mxs_saif_remove), 7942a24f2ceSDong Aisheng 7952a24f2ceSDong Aisheng .driver = { 7962a24f2ceSDong Aisheng .name = "mxs-saif", 7972a24f2ceSDong Aisheng .owner = THIS_MODULE, 79808641c7cSShawn Guo .of_match_table = mxs_saif_dt_ids, 7992a24f2ceSDong Aisheng }, 8002a24f2ceSDong Aisheng }; 8012a24f2ceSDong Aisheng 80285aa0960SAxel Lin module_platform_driver(mxs_saif_driver); 8032a24f2ceSDong Aisheng 8042a24f2ceSDong Aisheng MODULE_AUTHOR("Freescale Semiconductor, Inc."); 8052a24f2ceSDong Aisheng MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 8062a24f2ceSDong Aisheng MODULE_LICENSE("GPL"); 807