12a24f2ceSDong Aisheng /* 22a24f2ceSDong Aisheng * Copyright 2011 Freescale Semiconductor, Inc. 32a24f2ceSDong Aisheng * 42a24f2ceSDong Aisheng * This program is free software; you can redistribute it and/or modify 52a24f2ceSDong Aisheng * it under the terms of the GNU General Public License as published by 62a24f2ceSDong Aisheng * the Free Software Foundation; either version 2 of the License, or 72a24f2ceSDong Aisheng * (at your option) any later version. 82a24f2ceSDong Aisheng * 92a24f2ceSDong Aisheng * This program is distributed in the hope that it will be useful, 102a24f2ceSDong Aisheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 112a24f2ceSDong Aisheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122a24f2ceSDong Aisheng * GNU General Public License for more details. 132a24f2ceSDong Aisheng * 142a24f2ceSDong Aisheng * You should have received a copy of the GNU General Public License along 152a24f2ceSDong Aisheng * with this program; if not, write to the Free Software Foundation, Inc., 162a24f2ceSDong Aisheng * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 172a24f2ceSDong Aisheng */ 182a24f2ceSDong Aisheng 192a24f2ceSDong Aisheng #include <linux/module.h> 202a24f2ceSDong Aisheng #include <linux/init.h> 2108641c7cSShawn Guo #include <linux/of.h> 2208641c7cSShawn Guo #include <linux/of_device.h> 232a24f2ceSDong Aisheng #include <linux/platform_device.h> 242a24f2ceSDong Aisheng #include <linux/slab.h> 252a24f2ceSDong Aisheng #include <linux/dma-mapping.h> 262a24f2ceSDong Aisheng #include <linux/clk.h> 277c9e6150SShawn Guo #include <linux/clk-provider.h> 282a24f2ceSDong Aisheng #include <linux/delay.h> 2976067540SDong Aisheng #include <linux/time.h> 302a24f2ceSDong Aisheng #include <sound/core.h> 312a24f2ceSDong Aisheng #include <sound/pcm.h> 322a24f2ceSDong Aisheng #include <sound/pcm_params.h> 332a24f2ceSDong Aisheng #include <sound/soc.h> 342a24f2ceSDong Aisheng 352a24f2ceSDong Aisheng #include "mxs-saif.h" 362a24f2ceSDong Aisheng 37114fe75dSShawn Guo #define MXS_SET_ADDR 0x4 38114fe75dSShawn Guo #define MXS_CLR_ADDR 0x8 39114fe75dSShawn Guo 402a24f2ceSDong Aisheng static struct mxs_saif *mxs_saif[2]; 412a24f2ceSDong Aisheng 4276067540SDong Aisheng /* 4376067540SDong Aisheng * SAIF is a little different with other normal SOC DAIs on clock using. 4476067540SDong Aisheng * 4576067540SDong Aisheng * For MXS, two SAIF modules are instantiated on-chip. 4676067540SDong Aisheng * Each SAIF has a set of clock pins and can be operating in master 4776067540SDong Aisheng * mode simultaneously if they are connected to different off-chip codecs. 4876067540SDong Aisheng * Also, one of the two SAIFs can master or drive the clock pins while the 4976067540SDong Aisheng * other SAIF, in slave mode, receives clocking from the master SAIF. 5076067540SDong Aisheng * This also means that both SAIFs must operate at the same sample rate. 5176067540SDong Aisheng * 5276067540SDong Aisheng * We abstract this as each saif has a master, the master could be 5305004cb4SMatthew Garrett * itself or other saifs. In the generic saif driver, saif does not need 5405004cb4SMatthew Garrett * to know the different clkmux. Saif only needs to know who is its master 5505004cb4SMatthew Garrett * and operating its master to generate the proper clock rate for it. 5676067540SDong Aisheng * The master id is provided in mach-specific layer according to different 5776067540SDong Aisheng * clkmux setting. 5876067540SDong Aisheng */ 5976067540SDong Aisheng 602a24f2ceSDong Aisheng static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 612a24f2ceSDong Aisheng int clk_id, unsigned int freq, int dir) 622a24f2ceSDong Aisheng { 632a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 642a24f2ceSDong Aisheng 652a24f2ceSDong Aisheng switch (clk_id) { 662a24f2ceSDong Aisheng case MXS_SAIF_MCLK: 672a24f2ceSDong Aisheng saif->mclk = freq; 682a24f2ceSDong Aisheng break; 692a24f2ceSDong Aisheng default: 702a24f2ceSDong Aisheng return -EINVAL; 712a24f2ceSDong Aisheng } 722a24f2ceSDong Aisheng return 0; 732a24f2ceSDong Aisheng } 742a24f2ceSDong Aisheng 752a24f2ceSDong Aisheng /* 7676067540SDong Aisheng * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 7776067540SDong Aisheng * is provided by other SAIF, we provide a interface here to get its master 7876067540SDong Aisheng * from its master_id. 7905004cb4SMatthew Garrett * Note that the master could be itself. 8076067540SDong Aisheng */ 8176067540SDong Aisheng static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 8276067540SDong Aisheng { 8376067540SDong Aisheng return mxs_saif[saif->master_id]; 8476067540SDong Aisheng } 8576067540SDong Aisheng 8676067540SDong Aisheng /* 872a24f2ceSDong Aisheng * Set SAIF clock and MCLK 882a24f2ceSDong Aisheng */ 892a24f2ceSDong Aisheng static int mxs_saif_set_clk(struct mxs_saif *saif, 902a24f2ceSDong Aisheng unsigned int mclk, 912a24f2ceSDong Aisheng unsigned int rate) 922a24f2ceSDong Aisheng { 932a24f2ceSDong Aisheng u32 scr; 942a24f2ceSDong Aisheng int ret; 9576067540SDong Aisheng struct mxs_saif *master_saif; 962a24f2ceSDong Aisheng 9776067540SDong Aisheng dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 9876067540SDong Aisheng 9976067540SDong Aisheng /* Set master saif to generate proper clock */ 10076067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 10176067540SDong Aisheng if (!master_saif) 10276067540SDong Aisheng return -EINVAL; 10376067540SDong Aisheng 10476067540SDong Aisheng dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 10576067540SDong Aisheng 10676067540SDong Aisheng /* Checking if can playback and capture simutaneously */ 10776067540SDong Aisheng if (master_saif->ongoing && rate != master_saif->cur_rate) { 10876067540SDong Aisheng dev_err(saif->dev, 10976067540SDong Aisheng "can not change clock, master saif%d(rate %d) is ongoing\n", 11076067540SDong Aisheng master_saif->id, master_saif->cur_rate); 11176067540SDong Aisheng return -EINVAL; 11276067540SDong Aisheng } 11376067540SDong Aisheng 11476067540SDong Aisheng scr = __raw_readl(master_saif->base + SAIF_CTRL); 1152a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 1162a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 1172a24f2ceSDong Aisheng 1182a24f2ceSDong Aisheng /* 1192a24f2ceSDong Aisheng * Set SAIF clock 1202a24f2ceSDong Aisheng * 1212a24f2ceSDong Aisheng * The SAIF clock should be either 384*fs or 512*fs. 1222a24f2ceSDong Aisheng * If MCLK is used, the SAIF clk ratio need to match mclk ratio. 1232a24f2ceSDong Aisheng * For 32x mclk, set saif clk as 512*fs. 1242a24f2ceSDong Aisheng * For 48x mclk, set saif clk as 384*fs. 1252a24f2ceSDong Aisheng * 1262a24f2ceSDong Aisheng * If MCLK is not used, we just set saif clk to 512*fs. 1272a24f2ceSDong Aisheng */ 1286b35f924SFabio Estevam clk_prepare_enable(master_saif->clk); 1296b35f924SFabio Estevam 13076067540SDong Aisheng if (master_saif->mclk_in_use) { 1312a24f2ceSDong Aisheng if (mclk % 32 == 0) { 1322a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 13376067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 512 * rate); 1342a24f2ceSDong Aisheng } else if (mclk % 48 == 0) { 1352a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 13676067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 384 * rate); 1372a24f2ceSDong Aisheng } else { 1382a24f2ceSDong Aisheng /* SAIF MCLK should be either 32x or 48x */ 1396b35f924SFabio Estevam clk_disable_unprepare(master_saif->clk); 1402a24f2ceSDong Aisheng return -EINVAL; 1412a24f2ceSDong Aisheng } 1422a24f2ceSDong Aisheng } else { 14376067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 512 * rate); 1442a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 1452a24f2ceSDong Aisheng } 1462a24f2ceSDong Aisheng 1476b35f924SFabio Estevam clk_disable_unprepare(master_saif->clk); 1486b35f924SFabio Estevam 1492a24f2ceSDong Aisheng if (ret) 1502a24f2ceSDong Aisheng return ret; 1512a24f2ceSDong Aisheng 15276067540SDong Aisheng master_saif->cur_rate = rate; 15376067540SDong Aisheng 15476067540SDong Aisheng if (!master_saif->mclk_in_use) { 15576067540SDong Aisheng __raw_writel(scr, master_saif->base + SAIF_CTRL); 1562a24f2ceSDong Aisheng return 0; 1572a24f2ceSDong Aisheng } 1582a24f2ceSDong Aisheng 1592a24f2ceSDong Aisheng /* 1602a24f2ceSDong Aisheng * Program the over-sample rate for MCLK output 1612a24f2ceSDong Aisheng * 1622a24f2ceSDong Aisheng * The available MCLK range is 32x, 48x... 512x. The rate 1632a24f2ceSDong Aisheng * could be from 8kHz to 192kH. 1642a24f2ceSDong Aisheng */ 1652a24f2ceSDong Aisheng switch (mclk / rate) { 1662a24f2ceSDong Aisheng case 32: 1672a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 1682a24f2ceSDong Aisheng break; 1692a24f2ceSDong Aisheng case 64: 1702a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 1712a24f2ceSDong Aisheng break; 1722a24f2ceSDong Aisheng case 128: 1732a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 1742a24f2ceSDong Aisheng break; 1752a24f2ceSDong Aisheng case 256: 1762a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 1772a24f2ceSDong Aisheng break; 1782a24f2ceSDong Aisheng case 512: 1792a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 1802a24f2ceSDong Aisheng break; 1812a24f2ceSDong Aisheng case 48: 1822a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 1832a24f2ceSDong Aisheng break; 1842a24f2ceSDong Aisheng case 96: 1852a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 1862a24f2ceSDong Aisheng break; 1872a24f2ceSDong Aisheng case 192: 1882a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 1892a24f2ceSDong Aisheng break; 1902a24f2ceSDong Aisheng case 384: 1912a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 1922a24f2ceSDong Aisheng break; 1932a24f2ceSDong Aisheng default: 1942a24f2ceSDong Aisheng return -EINVAL; 1952a24f2ceSDong Aisheng } 1962a24f2ceSDong Aisheng 19776067540SDong Aisheng __raw_writel(scr, master_saif->base + SAIF_CTRL); 1982a24f2ceSDong Aisheng 1992a24f2ceSDong Aisheng return 0; 2002a24f2ceSDong Aisheng } 2012a24f2ceSDong Aisheng 2022a24f2ceSDong Aisheng /* 2032a24f2ceSDong Aisheng * Put and disable MCLK. 2042a24f2ceSDong Aisheng */ 2052a24f2ceSDong Aisheng int mxs_saif_put_mclk(unsigned int saif_id) 2062a24f2ceSDong Aisheng { 2072a24f2ceSDong Aisheng struct mxs_saif *saif = mxs_saif[saif_id]; 2082a24f2ceSDong Aisheng u32 stat; 2092a24f2ceSDong Aisheng 2102a24f2ceSDong Aisheng if (!saif) 2112a24f2ceSDong Aisheng return -EINVAL; 2122a24f2ceSDong Aisheng 2132a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2142a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2152a24f2ceSDong Aisheng dev_err(saif->dev, "error: busy\n"); 2162a24f2ceSDong Aisheng return -EBUSY; 2172a24f2ceSDong Aisheng } 2182a24f2ceSDong Aisheng 21967939b22SShawn Guo clk_disable_unprepare(saif->clk); 2202a24f2ceSDong Aisheng 2212a24f2ceSDong Aisheng /* disable MCLK output */ 2222a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 2232a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 2242a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 2252a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 2262a24f2ceSDong Aisheng 2272a24f2ceSDong Aisheng saif->mclk_in_use = 0; 2282a24f2ceSDong Aisheng return 0; 2292a24f2ceSDong Aisheng } 230cf7d0f09SLothar Waßmann EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); 2312a24f2ceSDong Aisheng 2322a24f2ceSDong Aisheng /* 2332a24f2ceSDong Aisheng * Get MCLK and set clock rate, then enable it 2342a24f2ceSDong Aisheng * 2352a24f2ceSDong Aisheng * This interface is used for codecs who are using MCLK provided 2362a24f2ceSDong Aisheng * by saif. 2372a24f2ceSDong Aisheng */ 2382a24f2ceSDong Aisheng int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 2392a24f2ceSDong Aisheng unsigned int rate) 2402a24f2ceSDong Aisheng { 2412a24f2ceSDong Aisheng struct mxs_saif *saif = mxs_saif[saif_id]; 2422a24f2ceSDong Aisheng u32 stat; 2432a24f2ceSDong Aisheng int ret; 24476067540SDong Aisheng struct mxs_saif *master_saif; 2452a24f2ceSDong Aisheng 2462a24f2ceSDong Aisheng if (!saif) 2472a24f2ceSDong Aisheng return -EINVAL; 2482a24f2ceSDong Aisheng 249bbe8ff5eSDong Aisheng /* Clear Reset */ 250bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_SFTRST, 251bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 252bbe8ff5eSDong Aisheng 253bbe8ff5eSDong Aisheng /* FIXME: need clear clk gate for register r/w */ 254bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 255bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 256bbe8ff5eSDong Aisheng 25776067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 25876067540SDong Aisheng if (saif != master_saif) { 25976067540SDong Aisheng dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 26076067540SDong Aisheng return -EINVAL; 26176067540SDong Aisheng } 26276067540SDong Aisheng 2632a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2642a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2652a24f2ceSDong Aisheng dev_err(saif->dev, "error: busy\n"); 2662a24f2ceSDong Aisheng return -EBUSY; 2672a24f2ceSDong Aisheng } 2682a24f2ceSDong Aisheng 2692a24f2ceSDong Aisheng saif->mclk_in_use = 1; 2702a24f2ceSDong Aisheng ret = mxs_saif_set_clk(saif, mclk, rate); 2712a24f2ceSDong Aisheng if (ret) 2722a24f2ceSDong Aisheng return ret; 2732a24f2ceSDong Aisheng 27467939b22SShawn Guo ret = clk_prepare_enable(saif->clk); 2752a24f2ceSDong Aisheng if (ret) 2762a24f2ceSDong Aisheng return ret; 2772a24f2ceSDong Aisheng 2782a24f2ceSDong Aisheng /* enable MCLK output */ 2792a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 2802a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 2812a24f2ceSDong Aisheng 2822a24f2ceSDong Aisheng return 0; 2832a24f2ceSDong Aisheng } 284cf7d0f09SLothar Waßmann EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); 2852a24f2ceSDong Aisheng 2862a24f2ceSDong Aisheng /* 2872a24f2ceSDong Aisheng * SAIF DAI format configuration. 2882a24f2ceSDong Aisheng * Should only be called when port is inactive. 2892a24f2ceSDong Aisheng */ 2902a24f2ceSDong Aisheng static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 2912a24f2ceSDong Aisheng { 2922a24f2ceSDong Aisheng u32 scr, stat; 2932a24f2ceSDong Aisheng u32 scr0; 2942a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 2952a24f2ceSDong Aisheng 2962a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2972a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2982a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "error: busy\n"); 2992a24f2ceSDong Aisheng return -EBUSY; 3002a24f2ceSDong Aisheng } 3012a24f2ceSDong Aisheng 302b25658edSJörg Krause /* If SAIF1 is configured as slave, the clk gate needs to be cleared 303b25658edSJörg Krause * before the register can be written. 304b25658edSJörg Krause */ 305b25658edSJörg Krause if (saif->id != saif->master_id) { 306b25658edSJörg Krause __raw_writel(BM_SAIF_CTRL_SFTRST, 307b25658edSJörg Krause saif->base + SAIF_CTRL + MXS_CLR_ADDR); 308b25658edSJörg Krause __raw_writel(BM_SAIF_CTRL_CLKGATE, 309b25658edSJörg Krause saif->base + SAIF_CTRL + MXS_CLR_ADDR); 310b25658edSJörg Krause } 311b25658edSJörg Krause 3122a24f2ceSDong Aisheng scr0 = __raw_readl(saif->base + SAIF_CTRL); 3132a24f2ceSDong Aisheng scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 3142a24f2ceSDong Aisheng & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 3152a24f2ceSDong Aisheng scr = 0; 3162a24f2ceSDong Aisheng 3172a24f2ceSDong Aisheng /* DAI mode */ 3182a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3192a24f2ceSDong Aisheng case SND_SOC_DAIFMT_I2S: 3202a24f2ceSDong Aisheng /* data frame low 1clk before data */ 3212a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_DELAY; 3222a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3232a24f2ceSDong Aisheng break; 3242a24f2ceSDong Aisheng case SND_SOC_DAIFMT_LEFT_J: 3252a24f2ceSDong Aisheng /* data frame high with data */ 3262a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_DELAY; 3272a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3282a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_JUSTIFY; 3292a24f2ceSDong Aisheng break; 3302a24f2ceSDong Aisheng default: 3312a24f2ceSDong Aisheng return -EINVAL; 3322a24f2ceSDong Aisheng } 3332a24f2ceSDong Aisheng 3342a24f2ceSDong Aisheng /* DAI clock inversion */ 3352a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3362a24f2ceSDong Aisheng case SND_SOC_DAIFMT_IB_IF: 3372a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_EDGE; 3382a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 3392a24f2ceSDong Aisheng break; 3402a24f2ceSDong Aisheng case SND_SOC_DAIFMT_IB_NF: 3412a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_EDGE; 3422a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3432a24f2ceSDong Aisheng break; 3442a24f2ceSDong Aisheng case SND_SOC_DAIFMT_NB_IF: 3452a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 3462a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 3472a24f2ceSDong Aisheng break; 3482a24f2ceSDong Aisheng case SND_SOC_DAIFMT_NB_NF: 3492a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 3502a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3512a24f2ceSDong Aisheng break; 3522a24f2ceSDong Aisheng } 3532a24f2ceSDong Aisheng 3542a24f2ceSDong Aisheng /* 3552a24f2ceSDong Aisheng * Note: We simply just support master mode since SAIF TX can only 3562a24f2ceSDong Aisheng * work as master. 35776067540SDong Aisheng * Here the master is relative to codec side. 35876067540SDong Aisheng * Saif internally could be slave when working on EXTMASTER mode. 35976067540SDong Aisheng * We just hide this to machine driver. 3602a24f2ceSDong Aisheng */ 3612a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3622a24f2ceSDong Aisheng case SND_SOC_DAIFMT_CBS_CFS: 36376067540SDong Aisheng if (saif->id == saif->master_id) 3642a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 36576067540SDong Aisheng else 36676067540SDong Aisheng scr |= BM_SAIF_CTRL_SLAVE_MODE; 36776067540SDong Aisheng 3682a24f2ceSDong Aisheng __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 3692a24f2ceSDong Aisheng break; 3702a24f2ceSDong Aisheng default: 3712a24f2ceSDong Aisheng return -EINVAL; 3722a24f2ceSDong Aisheng } 3732a24f2ceSDong Aisheng 3742a24f2ceSDong Aisheng return 0; 3752a24f2ceSDong Aisheng } 3762a24f2ceSDong Aisheng 3772a24f2ceSDong Aisheng static int mxs_saif_startup(struct snd_pcm_substream *substream, 3782a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 3792a24f2ceSDong Aisheng { 3802a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 3812a24f2ceSDong Aisheng 3822a24f2ceSDong Aisheng /* clear error status to 0 for each re-open */ 3832a24f2ceSDong Aisheng saif->fifo_underrun = 0; 3842a24f2ceSDong Aisheng saif->fifo_overrun = 0; 3852a24f2ceSDong Aisheng 3862a24f2ceSDong Aisheng /* Clear Reset for normal operations */ 3872a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_SFTRST, 3882a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 3892a24f2ceSDong Aisheng 390bbe8ff5eSDong Aisheng /* clear clock gate */ 391bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 392bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 393bbe8ff5eSDong Aisheng 394f212c6d8SMans Rullgard clk_prepare(saif->clk); 395f212c6d8SMans Rullgard 3962a24f2ceSDong Aisheng return 0; 3972a24f2ceSDong Aisheng } 3982a24f2ceSDong Aisheng 399f212c6d8SMans Rullgard static void mxs_saif_shutdown(struct snd_pcm_substream *substream, 400f212c6d8SMans Rullgard struct snd_soc_dai *cpu_dai) 401f212c6d8SMans Rullgard { 402f212c6d8SMans Rullgard struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 403f212c6d8SMans Rullgard 404f212c6d8SMans Rullgard clk_unprepare(saif->clk); 405f212c6d8SMans Rullgard } 406f212c6d8SMans Rullgard 4072a24f2ceSDong Aisheng /* 4082a24f2ceSDong Aisheng * Should only be called when port is inactive. 4092a24f2ceSDong Aisheng * although can be called multiple times by upper layers. 4102a24f2ceSDong Aisheng */ 4112a24f2ceSDong Aisheng static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 4122a24f2ceSDong Aisheng struct snd_pcm_hw_params *params, 4132a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 4142a24f2ceSDong Aisheng { 4152a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 416c2e1d907SDong Aisheng struct mxs_saif *master_saif; 4172a24f2ceSDong Aisheng u32 scr, stat; 4182a24f2ceSDong Aisheng int ret; 4192a24f2ceSDong Aisheng 420c2e1d907SDong Aisheng master_saif = mxs_saif_get_master(saif); 421c2e1d907SDong Aisheng if (!master_saif) 422c2e1d907SDong Aisheng return -EINVAL; 423c2e1d907SDong Aisheng 4242a24f2ceSDong Aisheng /* mclk should already be set */ 4252a24f2ceSDong Aisheng if (!saif->mclk && saif->mclk_in_use) { 4262a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "set mclk first\n"); 4272a24f2ceSDong Aisheng return -EINVAL; 4282a24f2ceSDong Aisheng } 4292a24f2ceSDong Aisheng 4302a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 431436e056cSMans Rullgard if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) { 4322a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "error: busy\n"); 4332a24f2ceSDong Aisheng return -EBUSY; 4342a24f2ceSDong Aisheng } 4352a24f2ceSDong Aisheng 4362a24f2ceSDong Aisheng /* 4372a24f2ceSDong Aisheng * Set saif clk based on sample rate. 4382a24f2ceSDong Aisheng * If mclk is used, we also set mclk, if not, saif->mclk is 4392a24f2ceSDong Aisheng * default 0, means not used. 4402a24f2ceSDong Aisheng */ 4412a24f2ceSDong Aisheng ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 4422a24f2ceSDong Aisheng if (ret) { 4432a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "unable to get proper clk\n"); 4442a24f2ceSDong Aisheng return ret; 4452a24f2ceSDong Aisheng } 4462a24f2ceSDong Aisheng 447d0ba4c01SDong Aisheng if (saif != master_saif) { 448d0ba4c01SDong Aisheng /* 449d0ba4c01SDong Aisheng * Set an initial clock rate for the saif internal logic to work 450d0ba4c01SDong Aisheng * properly. This is important when working in EXTMASTER mode 451d0ba4c01SDong Aisheng * that uses the other saif's BITCLK&LRCLK but it still needs a 452d0ba4c01SDong Aisheng * basic clock which should be fast enough for the internal 453d0ba4c01SDong Aisheng * logic. 454d0ba4c01SDong Aisheng */ 455d0ba4c01SDong Aisheng clk_enable(saif->clk); 456d0ba4c01SDong Aisheng ret = clk_set_rate(saif->clk, 24000000); 457d0ba4c01SDong Aisheng clk_disable(saif->clk); 458d0ba4c01SDong Aisheng if (ret) 459d0ba4c01SDong Aisheng return ret; 460d0ba4c01SDong Aisheng 461c2e1d907SDong Aisheng clk_prepare(master_saif->clk); 462d0ba4c01SDong Aisheng } 463c2e1d907SDong Aisheng 4642a24f2ceSDong Aisheng scr = __raw_readl(saif->base + SAIF_CTRL); 4652a24f2ceSDong Aisheng 4662a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 4672a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4682a24f2ceSDong Aisheng switch (params_format(params)) { 4692a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S16_LE: 4702a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 4712a24f2ceSDong Aisheng break; 4722a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S20_3LE: 4732a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 4742a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4752a24f2ceSDong Aisheng break; 4762a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S24_LE: 4772a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 4782a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4792a24f2ceSDong Aisheng break; 4802a24f2ceSDong Aisheng default: 4812a24f2ceSDong Aisheng return -EINVAL; 4822a24f2ceSDong Aisheng } 4832a24f2ceSDong Aisheng 4842a24f2ceSDong Aisheng /* Tx/Rx config */ 4852a24f2ceSDong Aisheng if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 4862a24f2ceSDong Aisheng /* enable TX mode */ 4872a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_READ_MODE; 4882a24f2ceSDong Aisheng } else { 4892a24f2ceSDong Aisheng /* enable RX mode */ 4902a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_READ_MODE; 4912a24f2ceSDong Aisheng } 4922a24f2ceSDong Aisheng 4932a24f2ceSDong Aisheng __raw_writel(scr, saif->base + SAIF_CTRL); 4942a24f2ceSDong Aisheng return 0; 4952a24f2ceSDong Aisheng } 4962a24f2ceSDong Aisheng 4972a24f2ceSDong Aisheng static int mxs_saif_prepare(struct snd_pcm_substream *substream, 4982a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 4992a24f2ceSDong Aisheng { 5002a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 5012a24f2ceSDong Aisheng 5022a24f2ceSDong Aisheng /* enable FIFO error irqs */ 5032a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 5042a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 5052a24f2ceSDong Aisheng 5062a24f2ceSDong Aisheng return 0; 5072a24f2ceSDong Aisheng } 5082a24f2ceSDong Aisheng 5092a24f2ceSDong Aisheng static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 5102a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 5112a24f2ceSDong Aisheng { 5122a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 51376067540SDong Aisheng struct mxs_saif *master_saif; 51476067540SDong Aisheng u32 delay; 515863ebddeSMarkus Pargmann int ret; 51676067540SDong Aisheng 51776067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 51876067540SDong Aisheng if (!master_saif) 51976067540SDong Aisheng return -EINVAL; 5202a24f2ceSDong Aisheng 5212a24f2ceSDong Aisheng switch (cmd) { 5222a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_START: 5232a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_RESUME: 5242a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 52588cf632aSMarkus Pargmann if (saif->state == MXS_SAIF_STATE_RUNNING) 52688cf632aSMarkus Pargmann return 0; 52788cf632aSMarkus Pargmann 5282a24f2ceSDong Aisheng dev_dbg(cpu_dai->dev, "start\n"); 5292a24f2ceSDong Aisheng 530863ebddeSMarkus Pargmann ret = clk_enable(master_saif->clk); 531863ebddeSMarkus Pargmann if (ret) { 532863ebddeSMarkus Pargmann dev_err(saif->dev, "Failed to enable master clock\n"); 533863ebddeSMarkus Pargmann return ret; 534863ebddeSMarkus Pargmann } 53576067540SDong Aisheng 53676067540SDong Aisheng /* 53705004cb4SMatthew Garrett * If the saif's master is not itself, we also need to enable 53876067540SDong Aisheng * itself clk for its internal basic logic to work. 53976067540SDong Aisheng */ 54076067540SDong Aisheng if (saif != master_saif) { 541863ebddeSMarkus Pargmann ret = clk_enable(saif->clk); 542863ebddeSMarkus Pargmann if (ret) { 543863ebddeSMarkus Pargmann dev_err(saif->dev, "Failed to enable master clock\n"); 544863ebddeSMarkus Pargmann clk_disable(master_saif->clk); 545863ebddeSMarkus Pargmann return ret; 546863ebddeSMarkus Pargmann } 547863ebddeSMarkus Pargmann 5482a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 5492a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 55076067540SDong Aisheng } 5512a24f2ceSDong Aisheng 552863ebddeSMarkus Pargmann if (!master_saif->mclk_in_use) 553863ebddeSMarkus Pargmann __raw_writel(BM_SAIF_CTRL_RUN, 554863ebddeSMarkus Pargmann master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 555863ebddeSMarkus Pargmann 5562a24f2ceSDong Aisheng if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5572a24f2ceSDong Aisheng /* 558f55f1475SFabio Estevam * write data to saif data register to trigger 559f55f1475SFabio Estevam * the transfer. 560f55f1475SFabio Estevam * For 24-bit format the 32-bit FIFO register stores 561f55f1475SFabio Estevam * only one channel, so we need to write twice. 562f55f1475SFabio Estevam * This is also safe for the other non 24-bit formats. 5632a24f2ceSDong Aisheng */ 5642a24f2ceSDong Aisheng __raw_writel(0, saif->base + SAIF_DATA); 565f55f1475SFabio Estevam __raw_writel(0, saif->base + SAIF_DATA); 5662a24f2ceSDong Aisheng } else { 5672a24f2ceSDong Aisheng /* 568f55f1475SFabio Estevam * read data from saif data register to trigger 569f55f1475SFabio Estevam * the receive. 570f55f1475SFabio Estevam * For 24-bit format the 32-bit FIFO register stores 571f55f1475SFabio Estevam * only one channel, so we need to read twice. 572f55f1475SFabio Estevam * This is also safe for the other non 24-bit formats. 5732a24f2ceSDong Aisheng */ 5742a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_DATA); 575f55f1475SFabio Estevam __raw_readl(saif->base + SAIF_DATA); 5762a24f2ceSDong Aisheng } 5772a24f2ceSDong Aisheng 57876067540SDong Aisheng master_saif->ongoing = 1; 57988cf632aSMarkus Pargmann saif->state = MXS_SAIF_STATE_RUNNING; 58076067540SDong Aisheng 58176067540SDong Aisheng dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 5822a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_CTRL), 5832a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_STAT)); 5842a24f2ceSDong Aisheng 58576067540SDong Aisheng dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 58676067540SDong Aisheng __raw_readl(master_saif->base + SAIF_CTRL), 58776067540SDong Aisheng __raw_readl(master_saif->base + SAIF_STAT)); 5882a24f2ceSDong Aisheng break; 5892a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_SUSPEND: 5902a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_STOP: 5912a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 59288cf632aSMarkus Pargmann if (saif->state == MXS_SAIF_STATE_STOPPED) 59388cf632aSMarkus Pargmann return 0; 59488cf632aSMarkus Pargmann 5952a24f2ceSDong Aisheng dev_dbg(cpu_dai->dev, "stop\n"); 5962a24f2ceSDong Aisheng 59776067540SDong Aisheng /* wait a while for the current sample to complete */ 59876067540SDong Aisheng delay = USEC_PER_SEC / master_saif->cur_rate; 59976067540SDong Aisheng 60076067540SDong Aisheng if (!master_saif->mclk_in_use) { 60176067540SDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 60276067540SDong Aisheng master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 60376067540SDong Aisheng udelay(delay); 60476067540SDong Aisheng } 60576067540SDong Aisheng clk_disable(master_saif->clk); 60676067540SDong Aisheng 60776067540SDong Aisheng if (saif != master_saif) { 6082a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 6092a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 61076067540SDong Aisheng udelay(delay); 61176067540SDong Aisheng clk_disable(saif->clk); 61276067540SDong Aisheng } 61376067540SDong Aisheng 61476067540SDong Aisheng master_saif->ongoing = 0; 61588cf632aSMarkus Pargmann saif->state = MXS_SAIF_STATE_STOPPED; 6162a24f2ceSDong Aisheng 6172a24f2ceSDong Aisheng break; 6182a24f2ceSDong Aisheng default: 6192a24f2ceSDong Aisheng return -EINVAL; 6202a24f2ceSDong Aisheng } 6212a24f2ceSDong Aisheng 6222a24f2ceSDong Aisheng return 0; 6232a24f2ceSDong Aisheng } 6242a24f2ceSDong Aisheng 6252a24f2ceSDong Aisheng #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 6262a24f2ceSDong Aisheng #define MXS_SAIF_FORMATS \ 6272a24f2ceSDong Aisheng (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 6282a24f2ceSDong Aisheng SNDRV_PCM_FMTBIT_S24_LE) 6292a24f2ceSDong Aisheng 63085e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 6312a24f2ceSDong Aisheng .startup = mxs_saif_startup, 632f212c6d8SMans Rullgard .shutdown = mxs_saif_shutdown, 6332a24f2ceSDong Aisheng .trigger = mxs_saif_trigger, 6342a24f2ceSDong Aisheng .prepare = mxs_saif_prepare, 6352a24f2ceSDong Aisheng .hw_params = mxs_saif_hw_params, 6362a24f2ceSDong Aisheng .set_sysclk = mxs_saif_set_dai_sysclk, 6372a24f2ceSDong Aisheng .set_fmt = mxs_saif_set_dai_fmt, 6382a24f2ceSDong Aisheng }; 6392a24f2ceSDong Aisheng 6402a24f2ceSDong Aisheng static int mxs_saif_dai_probe(struct snd_soc_dai *dai) 6412a24f2ceSDong Aisheng { 6422a24f2ceSDong Aisheng struct mxs_saif *saif = dev_get_drvdata(dai->dev); 6432a24f2ceSDong Aisheng 6442a24f2ceSDong Aisheng snd_soc_dai_set_drvdata(dai, saif); 6452a24f2ceSDong Aisheng 6462a24f2ceSDong Aisheng return 0; 6472a24f2ceSDong Aisheng } 6482a24f2ceSDong Aisheng 6492a24f2ceSDong Aisheng static struct snd_soc_dai_driver mxs_saif_dai = { 6502a24f2ceSDong Aisheng .name = "mxs-saif", 6512a24f2ceSDong Aisheng .probe = mxs_saif_dai_probe, 6522a24f2ceSDong Aisheng .playback = { 6532a24f2ceSDong Aisheng .channels_min = 2, 6542a24f2ceSDong Aisheng .channels_max = 2, 6552a24f2ceSDong Aisheng .rates = MXS_SAIF_RATES, 6562a24f2ceSDong Aisheng .formats = MXS_SAIF_FORMATS, 6572a24f2ceSDong Aisheng }, 6582a24f2ceSDong Aisheng .capture = { 6592a24f2ceSDong Aisheng .channels_min = 2, 6602a24f2ceSDong Aisheng .channels_max = 2, 6612a24f2ceSDong Aisheng .rates = MXS_SAIF_RATES, 6622a24f2ceSDong Aisheng .formats = MXS_SAIF_FORMATS, 6632a24f2ceSDong Aisheng }, 6642a24f2ceSDong Aisheng .ops = &mxs_saif_dai_ops, 6652a24f2ceSDong Aisheng }; 6662a24f2ceSDong Aisheng 667026240bbSKuninori Morimoto static const struct snd_soc_component_driver mxs_saif_component = { 668026240bbSKuninori Morimoto .name = "mxs-saif", 669026240bbSKuninori Morimoto }; 670026240bbSKuninori Morimoto 6712a24f2ceSDong Aisheng static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 6722a24f2ceSDong Aisheng { 6732a24f2ceSDong Aisheng struct mxs_saif *saif = dev_id; 6742a24f2ceSDong Aisheng unsigned int stat; 6752a24f2ceSDong Aisheng 6762a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 6772a24f2ceSDong Aisheng if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 6782a24f2ceSDong Aisheng BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 6792a24f2ceSDong Aisheng return IRQ_NONE; 6802a24f2ceSDong Aisheng 6812a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 6822a24f2ceSDong Aisheng dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 6832a24f2ceSDong Aisheng __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 6842a24f2ceSDong Aisheng saif->base + SAIF_STAT + MXS_CLR_ADDR); 6852a24f2ceSDong Aisheng } 6862a24f2ceSDong Aisheng 6872a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 6882a24f2ceSDong Aisheng dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 6892a24f2ceSDong Aisheng __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 6902a24f2ceSDong Aisheng saif->base + SAIF_STAT + MXS_CLR_ADDR); 6912a24f2ceSDong Aisheng } 6922a24f2ceSDong Aisheng 6932a24f2ceSDong Aisheng dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 6942a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_CTRL), 6952a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_STAT)); 6962a24f2ceSDong Aisheng 6972a24f2ceSDong Aisheng return IRQ_HANDLED; 6982a24f2ceSDong Aisheng } 6992a24f2ceSDong Aisheng 7007c9e6150SShawn Guo static int mxs_saif_mclk_init(struct platform_device *pdev) 7017c9e6150SShawn Guo { 7027c9e6150SShawn Guo struct mxs_saif *saif = platform_get_drvdata(pdev); 7037c9e6150SShawn Guo struct device_node *np = pdev->dev.of_node; 7047c9e6150SShawn Guo struct clk *clk; 7057c9e6150SShawn Guo int ret; 7067c9e6150SShawn Guo 7077c9e6150SShawn Guo clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk", 7087c9e6150SShawn Guo __clk_get_name(saif->clk), 0, 7097c9e6150SShawn Guo saif->base + SAIF_CTRL, 7107c9e6150SShawn Guo BP_SAIF_CTRL_BITCLK_MULT_RATE, 3, 7117c9e6150SShawn Guo 0, NULL); 7127c9e6150SShawn Guo if (IS_ERR(clk)) { 7137c9e6150SShawn Guo ret = PTR_ERR(clk); 7147c9e6150SShawn Guo if (ret == -EEXIST) 7157c9e6150SShawn Guo return 0; 7167c9e6150SShawn Guo dev_err(&pdev->dev, "failed to register mclk: %d\n", ret); 7177c9e6150SShawn Guo return PTR_ERR(clk); 7187c9e6150SShawn Guo } 7197c9e6150SShawn Guo 7207c9e6150SShawn Guo ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); 7217c9e6150SShawn Guo if (ret) 7227c9e6150SShawn Guo return ret; 7237c9e6150SShawn Guo 7247c9e6150SShawn Guo return 0; 7257c9e6150SShawn Guo } 7267c9e6150SShawn Guo 727fd582736SBill Pemberton static int mxs_saif_probe(struct platform_device *pdev) 7282a24f2ceSDong Aisheng { 72908641c7cSShawn Guo struct device_node *np = pdev->dev.of_node; 73062477adfSShawn Guo struct resource *iores; 7312a24f2ceSDong Aisheng struct mxs_saif *saif; 7325396ecf7SFabio Estevam int irq, ret = 0; 7334498a3caSFabio Estevam struct device_node *master; 7342a24f2ceSDong Aisheng 7354498a3caSFabio Estevam if (!np) 7360bb98ba2SJulia Lawall return -EINVAL; 7370bb98ba2SJulia Lawall 738830eb876SJulia Lawall saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 7392a24f2ceSDong Aisheng if (!saif) 7402a24f2ceSDong Aisheng return -ENOMEM; 7412a24f2ceSDong Aisheng 742324a7fb0SFabio Estevam ret = of_alias_get_id(np, "saif"); 743324a7fb0SFabio Estevam if (ret < 0) 744324a7fb0SFabio Estevam return ret; 745324a7fb0SFabio Estevam else 746324a7fb0SFabio Estevam saif->id = ret; 747324a7fb0SFabio Estevam 748e1b790a8SAlexey Khoroshilov if (saif->id >= ARRAY_SIZE(mxs_saif)) { 749e1b790a8SAlexey Khoroshilov dev_err(&pdev->dev, "get wrong saif id\n"); 750e1b790a8SAlexey Khoroshilov return -EINVAL; 751e1b790a8SAlexey Khoroshilov } 752e1b790a8SAlexey Khoroshilov 75308641c7cSShawn Guo /* 75408641c7cSShawn Guo * If there is no "fsl,saif-master" phandle, it's a saif 75508641c7cSShawn Guo * master. Otherwise, it's a slave and its phandle points 75608641c7cSShawn Guo * to the master. 75708641c7cSShawn Guo */ 75808641c7cSShawn Guo master = of_parse_phandle(np, "fsl,saif-master", 0); 75908641c7cSShawn Guo if (!master) { 76008641c7cSShawn Guo saif->master_id = saif->id; 76108641c7cSShawn Guo } else { 762324a7fb0SFabio Estevam ret = of_alias_get_id(master, "saif"); 763324a7fb0SFabio Estevam if (ret < 0) 764324a7fb0SFabio Estevam return ret; 765324a7fb0SFabio Estevam else 766324a7fb0SFabio Estevam saif->master_id = ret; 76708641c7cSShawn Guo 768324a7fb0SFabio Estevam if (saif->master_id >= ARRAY_SIZE(mxs_saif)) { 76977882580SDong Aisheng dev_err(&pdev->dev, "get wrong master id\n"); 77076067540SDong Aisheng return -EINVAL; 77176067540SDong Aisheng } 772e1b790a8SAlexey Khoroshilov } 77308641c7cSShawn Guo 77408641c7cSShawn Guo mxs_saif[saif->id] = saif; 7752a24f2ceSDong Aisheng 776730963f8SFabio Estevam saif->clk = devm_clk_get(&pdev->dev, NULL); 7772a24f2ceSDong Aisheng if (IS_ERR(saif->clk)) { 7782a24f2ceSDong Aisheng ret = PTR_ERR(saif->clk); 7792a24f2ceSDong Aisheng dev_err(&pdev->dev, "Cannot get the clock: %d\n", 7802a24f2ceSDong Aisheng ret); 781830eb876SJulia Lawall return ret; 7822a24f2ceSDong Aisheng } 7832a24f2ceSDong Aisheng 784226d0f22SJulia Lawall iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 7852a24f2ceSDong Aisheng 786b25b5aa0SThierry Reding saif->base = devm_ioremap_resource(&pdev->dev, iores); 787b25b5aa0SThierry Reding if (IS_ERR(saif->base)) 788b25b5aa0SThierry Reding return PTR_ERR(saif->base); 7892a24f2ceSDong Aisheng 7905396ecf7SFabio Estevam irq = platform_get_irq(pdev, 0); 7915396ecf7SFabio Estevam if (irq < 0) { 7925396ecf7SFabio Estevam ret = irq; 7932a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to get irq resource: %d\n", 7942a24f2ceSDong Aisheng ret); 795730963f8SFabio Estevam return ret; 7962a24f2ceSDong Aisheng } 7972a24f2ceSDong Aisheng 7982a24f2ceSDong Aisheng saif->dev = &pdev->dev; 7995396ecf7SFabio Estevam ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0, 8008c2727f9SFabio Estevam dev_name(&pdev->dev), saif); 8012a24f2ceSDong Aisheng if (ret) { 8022a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to request irq\n"); 803730963f8SFabio Estevam return ret; 8042a24f2ceSDong Aisheng } 8052a24f2ceSDong Aisheng 8062a24f2ceSDong Aisheng platform_set_drvdata(pdev, saif); 8072a24f2ceSDong Aisheng 8087c9e6150SShawn Guo /* We only support saif0 being tx and clock master */ 8097c9e6150SShawn Guo if (saif->id == 0) { 8107c9e6150SShawn Guo ret = mxs_saif_mclk_init(pdev); 8117c9e6150SShawn Guo if (ret) 8127c9e6150SShawn Guo dev_warn(&pdev->dev, "failed to init clocks\n"); 8137c9e6150SShawn Guo } 8147c9e6150SShawn Guo 815fcd70eb5SSachin Kamat ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component, 816026240bbSKuninori Morimoto &mxs_saif_dai, 1); 8172a24f2ceSDong Aisheng if (ret) { 8182a24f2ceSDong Aisheng dev_err(&pdev->dev, "register DAI failed\n"); 819730963f8SFabio Estevam return ret; 8202a24f2ceSDong Aisheng } 8212a24f2ceSDong Aisheng 8224da3fe78SShawn Guo ret = mxs_pcm_platform_register(&pdev->dev); 8232a24f2ceSDong Aisheng if (ret) { 8244da3fe78SShawn Guo dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 825fcd70eb5SSachin Kamat return ret; 8262a24f2ceSDong Aisheng } 8272a24f2ceSDong Aisheng 8282a24f2ceSDong Aisheng return 0; 8292a24f2ceSDong Aisheng } 8302a24f2ceSDong Aisheng 83108641c7cSShawn Guo static const struct of_device_id mxs_saif_dt_ids[] = { 83208641c7cSShawn Guo { .compatible = "fsl,imx28-saif", }, 83308641c7cSShawn Guo { /* sentinel */ } 83408641c7cSShawn Guo }; 83508641c7cSShawn Guo MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 83608641c7cSShawn Guo 8372a24f2ceSDong Aisheng static struct platform_driver mxs_saif_driver = { 8382a24f2ceSDong Aisheng .probe = mxs_saif_probe, 8392a24f2ceSDong Aisheng 8402a24f2ceSDong Aisheng .driver = { 8412a24f2ceSDong Aisheng .name = "mxs-saif", 84208641c7cSShawn Guo .of_match_table = mxs_saif_dt_ids, 8432a24f2ceSDong Aisheng }, 8442a24f2ceSDong Aisheng }; 8452a24f2ceSDong Aisheng 84685aa0960SAxel Lin module_platform_driver(mxs_saif_driver); 8472a24f2ceSDong Aisheng 8482a24f2ceSDong Aisheng MODULE_AUTHOR("Freescale Semiconductor, Inc."); 8492a24f2ceSDong Aisheng MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 8502a24f2ceSDong Aisheng MODULE_LICENSE("GPL"); 8519f4c3f1cSFabio Estevam MODULE_ALIAS("platform:mxs-saif"); 852