12a24f2ceSDong Aisheng /* 22a24f2ceSDong Aisheng * Copyright 2011 Freescale Semiconductor, Inc. 32a24f2ceSDong Aisheng * 42a24f2ceSDong Aisheng * This program is free software; you can redistribute it and/or modify 52a24f2ceSDong Aisheng * it under the terms of the GNU General Public License as published by 62a24f2ceSDong Aisheng * the Free Software Foundation; either version 2 of the License, or 72a24f2ceSDong Aisheng * (at your option) any later version. 82a24f2ceSDong Aisheng * 92a24f2ceSDong Aisheng * This program is distributed in the hope that it will be useful, 102a24f2ceSDong Aisheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 112a24f2ceSDong Aisheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 122a24f2ceSDong Aisheng * GNU General Public License for more details. 132a24f2ceSDong Aisheng * 142a24f2ceSDong Aisheng * You should have received a copy of the GNU General Public License along 152a24f2ceSDong Aisheng * with this program; if not, write to the Free Software Foundation, Inc., 162a24f2ceSDong Aisheng * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 172a24f2ceSDong Aisheng */ 182a24f2ceSDong Aisheng 192a24f2ceSDong Aisheng #include <linux/module.h> 202a24f2ceSDong Aisheng #include <linux/init.h> 212a24f2ceSDong Aisheng #include <linux/platform_device.h> 222a24f2ceSDong Aisheng #include <linux/slab.h> 232a24f2ceSDong Aisheng #include <linux/dma-mapping.h> 242a24f2ceSDong Aisheng #include <linux/clk.h> 252a24f2ceSDong Aisheng #include <linux/delay.h> 2676067540SDong Aisheng #include <linux/time.h> 272a24f2ceSDong Aisheng #include <sound/core.h> 282a24f2ceSDong Aisheng #include <sound/pcm.h> 292a24f2ceSDong Aisheng #include <sound/pcm_params.h> 302a24f2ceSDong Aisheng #include <sound/soc.h> 3176067540SDong Aisheng #include <sound/saif.h> 322a24f2ceSDong Aisheng #include <mach/dma.h> 332a24f2ceSDong Aisheng #include <asm/mach-types.h> 342a24f2ceSDong Aisheng #include <mach/hardware.h> 352a24f2ceSDong Aisheng #include <mach/mxs.h> 362a24f2ceSDong Aisheng 372a24f2ceSDong Aisheng #include "mxs-saif.h" 382a24f2ceSDong Aisheng 392a24f2ceSDong Aisheng static struct mxs_saif *mxs_saif[2]; 402a24f2ceSDong Aisheng 4176067540SDong Aisheng /* 4276067540SDong Aisheng * SAIF is a little different with other normal SOC DAIs on clock using. 4376067540SDong Aisheng * 4476067540SDong Aisheng * For MXS, two SAIF modules are instantiated on-chip. 4576067540SDong Aisheng * Each SAIF has a set of clock pins and can be operating in master 4676067540SDong Aisheng * mode simultaneously if they are connected to different off-chip codecs. 4776067540SDong Aisheng * Also, one of the two SAIFs can master or drive the clock pins while the 4876067540SDong Aisheng * other SAIF, in slave mode, receives clocking from the master SAIF. 4976067540SDong Aisheng * This also means that both SAIFs must operate at the same sample rate. 5076067540SDong Aisheng * 5176067540SDong Aisheng * We abstract this as each saif has a master, the master could be 5276067540SDong Aisheng * himself or other saifs. In the generic saif driver, saif does not need 5376067540SDong Aisheng * to know the different clkmux. Saif only needs to know who is his master 5476067540SDong Aisheng * and operating his master to generate the proper clock rate for him. 5576067540SDong Aisheng * The master id is provided in mach-specific layer according to different 5676067540SDong Aisheng * clkmux setting. 5776067540SDong Aisheng */ 5876067540SDong Aisheng 592a24f2ceSDong Aisheng static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 602a24f2ceSDong Aisheng int clk_id, unsigned int freq, int dir) 612a24f2ceSDong Aisheng { 622a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 632a24f2ceSDong Aisheng 642a24f2ceSDong Aisheng switch (clk_id) { 652a24f2ceSDong Aisheng case MXS_SAIF_MCLK: 662a24f2ceSDong Aisheng saif->mclk = freq; 672a24f2ceSDong Aisheng break; 682a24f2ceSDong Aisheng default: 692a24f2ceSDong Aisheng return -EINVAL; 702a24f2ceSDong Aisheng } 712a24f2ceSDong Aisheng return 0; 722a24f2ceSDong Aisheng } 732a24f2ceSDong Aisheng 742a24f2ceSDong Aisheng /* 7576067540SDong Aisheng * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 7676067540SDong Aisheng * is provided by other SAIF, we provide a interface here to get its master 7776067540SDong Aisheng * from its master_id. 7876067540SDong Aisheng * Note that the master could be himself. 7976067540SDong Aisheng */ 8076067540SDong Aisheng static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 8176067540SDong Aisheng { 8276067540SDong Aisheng return mxs_saif[saif->master_id]; 8376067540SDong Aisheng } 8476067540SDong Aisheng 8576067540SDong Aisheng /* 862a24f2ceSDong Aisheng * Set SAIF clock and MCLK 872a24f2ceSDong Aisheng */ 882a24f2ceSDong Aisheng static int mxs_saif_set_clk(struct mxs_saif *saif, 892a24f2ceSDong Aisheng unsigned int mclk, 902a24f2ceSDong Aisheng unsigned int rate) 912a24f2ceSDong Aisheng { 922a24f2ceSDong Aisheng u32 scr; 932a24f2ceSDong Aisheng int ret; 9476067540SDong Aisheng struct mxs_saif *master_saif; 952a24f2ceSDong Aisheng 9676067540SDong Aisheng dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 9776067540SDong Aisheng 9876067540SDong Aisheng /* Set master saif to generate proper clock */ 9976067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 10076067540SDong Aisheng if (!master_saif) 10176067540SDong Aisheng return -EINVAL; 10276067540SDong Aisheng 10376067540SDong Aisheng dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 10476067540SDong Aisheng 10576067540SDong Aisheng /* Checking if can playback and capture simutaneously */ 10676067540SDong Aisheng if (master_saif->ongoing && rate != master_saif->cur_rate) { 10776067540SDong Aisheng dev_err(saif->dev, 10876067540SDong Aisheng "can not change clock, master saif%d(rate %d) is ongoing\n", 10976067540SDong Aisheng master_saif->id, master_saif->cur_rate); 11076067540SDong Aisheng return -EINVAL; 11176067540SDong Aisheng } 11276067540SDong Aisheng 11376067540SDong Aisheng scr = __raw_readl(master_saif->base + SAIF_CTRL); 1142a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 1152a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 1162a24f2ceSDong Aisheng 1172a24f2ceSDong Aisheng /* 1182a24f2ceSDong Aisheng * Set SAIF clock 1192a24f2ceSDong Aisheng * 1202a24f2ceSDong Aisheng * The SAIF clock should be either 384*fs or 512*fs. 1212a24f2ceSDong Aisheng * If MCLK is used, the SAIF clk ratio need to match mclk ratio. 1222a24f2ceSDong Aisheng * For 32x mclk, set saif clk as 512*fs. 1232a24f2ceSDong Aisheng * For 48x mclk, set saif clk as 384*fs. 1242a24f2ceSDong Aisheng * 1252a24f2ceSDong Aisheng * If MCLK is not used, we just set saif clk to 512*fs. 1262a24f2ceSDong Aisheng */ 1276b35f924SFabio Estevam clk_prepare_enable(master_saif->clk); 1286b35f924SFabio Estevam 12976067540SDong Aisheng if (master_saif->mclk_in_use) { 1302a24f2ceSDong Aisheng if (mclk % 32 == 0) { 1312a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 13276067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 512 * rate); 1332a24f2ceSDong Aisheng } else if (mclk % 48 == 0) { 1342a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 13576067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 384 * rate); 1362a24f2ceSDong Aisheng } else { 1372a24f2ceSDong Aisheng /* SAIF MCLK should be either 32x or 48x */ 1386b35f924SFabio Estevam clk_disable_unprepare(master_saif->clk); 1392a24f2ceSDong Aisheng return -EINVAL; 1402a24f2ceSDong Aisheng } 1412a24f2ceSDong Aisheng } else { 14276067540SDong Aisheng ret = clk_set_rate(master_saif->clk, 512 * rate); 1432a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 1442a24f2ceSDong Aisheng } 1452a24f2ceSDong Aisheng 1466b35f924SFabio Estevam clk_disable_unprepare(master_saif->clk); 1476b35f924SFabio Estevam 1482a24f2ceSDong Aisheng if (ret) 1492a24f2ceSDong Aisheng return ret; 1502a24f2ceSDong Aisheng 15176067540SDong Aisheng master_saif->cur_rate = rate; 15276067540SDong Aisheng 15376067540SDong Aisheng if (!master_saif->mclk_in_use) { 15476067540SDong Aisheng __raw_writel(scr, master_saif->base + SAIF_CTRL); 1552a24f2ceSDong Aisheng return 0; 1562a24f2ceSDong Aisheng } 1572a24f2ceSDong Aisheng 1582a24f2ceSDong Aisheng /* 1592a24f2ceSDong Aisheng * Program the over-sample rate for MCLK output 1602a24f2ceSDong Aisheng * 1612a24f2ceSDong Aisheng * The available MCLK range is 32x, 48x... 512x. The rate 1622a24f2ceSDong Aisheng * could be from 8kHz to 192kH. 1632a24f2ceSDong Aisheng */ 1642a24f2ceSDong Aisheng switch (mclk / rate) { 1652a24f2ceSDong Aisheng case 32: 1662a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 1672a24f2ceSDong Aisheng break; 1682a24f2ceSDong Aisheng case 64: 1692a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 1702a24f2ceSDong Aisheng break; 1712a24f2ceSDong Aisheng case 128: 1722a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 1732a24f2ceSDong Aisheng break; 1742a24f2ceSDong Aisheng case 256: 1752a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 1762a24f2ceSDong Aisheng break; 1772a24f2ceSDong Aisheng case 512: 1782a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 1792a24f2ceSDong Aisheng break; 1802a24f2ceSDong Aisheng case 48: 1812a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 1822a24f2ceSDong Aisheng break; 1832a24f2ceSDong Aisheng case 96: 1842a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 1852a24f2ceSDong Aisheng break; 1862a24f2ceSDong Aisheng case 192: 1872a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 1882a24f2ceSDong Aisheng break; 1892a24f2ceSDong Aisheng case 384: 1902a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 1912a24f2ceSDong Aisheng break; 1922a24f2ceSDong Aisheng default: 1932a24f2ceSDong Aisheng return -EINVAL; 1942a24f2ceSDong Aisheng } 1952a24f2ceSDong Aisheng 19676067540SDong Aisheng __raw_writel(scr, master_saif->base + SAIF_CTRL); 1972a24f2ceSDong Aisheng 1982a24f2ceSDong Aisheng return 0; 1992a24f2ceSDong Aisheng } 2002a24f2ceSDong Aisheng 2012a24f2ceSDong Aisheng /* 2022a24f2ceSDong Aisheng * Put and disable MCLK. 2032a24f2ceSDong Aisheng */ 2042a24f2ceSDong Aisheng int mxs_saif_put_mclk(unsigned int saif_id) 2052a24f2ceSDong Aisheng { 2062a24f2ceSDong Aisheng struct mxs_saif *saif = mxs_saif[saif_id]; 2072a24f2ceSDong Aisheng u32 stat; 2082a24f2ceSDong Aisheng 2092a24f2ceSDong Aisheng if (!saif) 2102a24f2ceSDong Aisheng return -EINVAL; 2112a24f2ceSDong Aisheng 2122a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2132a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2142a24f2ceSDong Aisheng dev_err(saif->dev, "error: busy\n"); 2152a24f2ceSDong Aisheng return -EBUSY; 2162a24f2ceSDong Aisheng } 2172a24f2ceSDong Aisheng 21867939b22SShawn Guo clk_disable_unprepare(saif->clk); 2192a24f2ceSDong Aisheng 2202a24f2ceSDong Aisheng /* disable MCLK output */ 2212a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 2222a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 2232a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 2242a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 2252a24f2ceSDong Aisheng 2262a24f2ceSDong Aisheng saif->mclk_in_use = 0; 2272a24f2ceSDong Aisheng return 0; 2282a24f2ceSDong Aisheng } 2292a24f2ceSDong Aisheng 2302a24f2ceSDong Aisheng /* 2312a24f2ceSDong Aisheng * Get MCLK and set clock rate, then enable it 2322a24f2ceSDong Aisheng * 2332a24f2ceSDong Aisheng * This interface is used for codecs who are using MCLK provided 2342a24f2ceSDong Aisheng * by saif. 2352a24f2ceSDong Aisheng */ 2362a24f2ceSDong Aisheng int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 2372a24f2ceSDong Aisheng unsigned int rate) 2382a24f2ceSDong Aisheng { 2392a24f2ceSDong Aisheng struct mxs_saif *saif = mxs_saif[saif_id]; 2402a24f2ceSDong Aisheng u32 stat; 2412a24f2ceSDong Aisheng int ret; 24276067540SDong Aisheng struct mxs_saif *master_saif; 2432a24f2ceSDong Aisheng 2442a24f2ceSDong Aisheng if (!saif) 2452a24f2ceSDong Aisheng return -EINVAL; 2462a24f2ceSDong Aisheng 247bbe8ff5eSDong Aisheng /* Clear Reset */ 248bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_SFTRST, 249bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 250bbe8ff5eSDong Aisheng 251bbe8ff5eSDong Aisheng /* FIXME: need clear clk gate for register r/w */ 252bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 253bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 254bbe8ff5eSDong Aisheng 25576067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 25676067540SDong Aisheng if (saif != master_saif) { 25776067540SDong Aisheng dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 25876067540SDong Aisheng return -EINVAL; 25976067540SDong Aisheng } 26076067540SDong Aisheng 2612a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2622a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2632a24f2ceSDong Aisheng dev_err(saif->dev, "error: busy\n"); 2642a24f2ceSDong Aisheng return -EBUSY; 2652a24f2ceSDong Aisheng } 2662a24f2ceSDong Aisheng 2672a24f2ceSDong Aisheng saif->mclk_in_use = 1; 2682a24f2ceSDong Aisheng ret = mxs_saif_set_clk(saif, mclk, rate); 2692a24f2ceSDong Aisheng if (ret) 2702a24f2ceSDong Aisheng return ret; 2712a24f2ceSDong Aisheng 27267939b22SShawn Guo ret = clk_prepare_enable(saif->clk); 2732a24f2ceSDong Aisheng if (ret) 2742a24f2ceSDong Aisheng return ret; 2752a24f2ceSDong Aisheng 2762a24f2ceSDong Aisheng /* enable MCLK output */ 2772a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 2782a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 2792a24f2ceSDong Aisheng 2802a24f2ceSDong Aisheng return 0; 2812a24f2ceSDong Aisheng } 2822a24f2ceSDong Aisheng 2832a24f2ceSDong Aisheng /* 2842a24f2ceSDong Aisheng * SAIF DAI format configuration. 2852a24f2ceSDong Aisheng * Should only be called when port is inactive. 2862a24f2ceSDong Aisheng */ 2872a24f2ceSDong Aisheng static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 2882a24f2ceSDong Aisheng { 2892a24f2ceSDong Aisheng u32 scr, stat; 2902a24f2ceSDong Aisheng u32 scr0; 2912a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 2922a24f2ceSDong Aisheng 2932a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 2942a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 2952a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "error: busy\n"); 2962a24f2ceSDong Aisheng return -EBUSY; 2972a24f2ceSDong Aisheng } 2982a24f2ceSDong Aisheng 2992a24f2ceSDong Aisheng scr0 = __raw_readl(saif->base + SAIF_CTRL); 3002a24f2ceSDong Aisheng scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 3012a24f2ceSDong Aisheng & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 3022a24f2ceSDong Aisheng scr = 0; 3032a24f2ceSDong Aisheng 3042a24f2ceSDong Aisheng /* DAI mode */ 3052a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3062a24f2ceSDong Aisheng case SND_SOC_DAIFMT_I2S: 3072a24f2ceSDong Aisheng /* data frame low 1clk before data */ 3082a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_DELAY; 3092a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3102a24f2ceSDong Aisheng break; 3112a24f2ceSDong Aisheng case SND_SOC_DAIFMT_LEFT_J: 3122a24f2ceSDong Aisheng /* data frame high with data */ 3132a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_DELAY; 3142a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3152a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_JUSTIFY; 3162a24f2ceSDong Aisheng break; 3172a24f2ceSDong Aisheng default: 3182a24f2ceSDong Aisheng return -EINVAL; 3192a24f2ceSDong Aisheng } 3202a24f2ceSDong Aisheng 3212a24f2ceSDong Aisheng /* DAI clock inversion */ 3222a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3232a24f2ceSDong Aisheng case SND_SOC_DAIFMT_IB_IF: 3242a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_EDGE; 3252a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 3262a24f2ceSDong Aisheng break; 3272a24f2ceSDong Aisheng case SND_SOC_DAIFMT_IB_NF: 3282a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_EDGE; 3292a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3302a24f2ceSDong Aisheng break; 3312a24f2ceSDong Aisheng case SND_SOC_DAIFMT_NB_IF: 3322a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 3332a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 3342a24f2ceSDong Aisheng break; 3352a24f2ceSDong Aisheng case SND_SOC_DAIFMT_NB_NF: 3362a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 3372a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 3382a24f2ceSDong Aisheng break; 3392a24f2ceSDong Aisheng } 3402a24f2ceSDong Aisheng 3412a24f2ceSDong Aisheng /* 3422a24f2ceSDong Aisheng * Note: We simply just support master mode since SAIF TX can only 3432a24f2ceSDong Aisheng * work as master. 34476067540SDong Aisheng * Here the master is relative to codec side. 34576067540SDong Aisheng * Saif internally could be slave when working on EXTMASTER mode. 34676067540SDong Aisheng * We just hide this to machine driver. 3472a24f2ceSDong Aisheng */ 3482a24f2ceSDong Aisheng switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3492a24f2ceSDong Aisheng case SND_SOC_DAIFMT_CBS_CFS: 35076067540SDong Aisheng if (saif->id == saif->master_id) 3512a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 35276067540SDong Aisheng else 35376067540SDong Aisheng scr |= BM_SAIF_CTRL_SLAVE_MODE; 35476067540SDong Aisheng 3552a24f2ceSDong Aisheng __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 3562a24f2ceSDong Aisheng break; 3572a24f2ceSDong Aisheng default: 3582a24f2ceSDong Aisheng return -EINVAL; 3592a24f2ceSDong Aisheng } 3602a24f2ceSDong Aisheng 3612a24f2ceSDong Aisheng return 0; 3622a24f2ceSDong Aisheng } 3632a24f2ceSDong Aisheng 3642a24f2ceSDong Aisheng static int mxs_saif_startup(struct snd_pcm_substream *substream, 3652a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 3662a24f2ceSDong Aisheng { 3672a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 3682a24f2ceSDong Aisheng snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param); 3692a24f2ceSDong Aisheng 3702a24f2ceSDong Aisheng /* clear error status to 0 for each re-open */ 3712a24f2ceSDong Aisheng saif->fifo_underrun = 0; 3722a24f2ceSDong Aisheng saif->fifo_overrun = 0; 3732a24f2ceSDong Aisheng 3742a24f2ceSDong Aisheng /* Clear Reset for normal operations */ 3752a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_SFTRST, 3762a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 3772a24f2ceSDong Aisheng 378bbe8ff5eSDong Aisheng /* clear clock gate */ 379bbe8ff5eSDong Aisheng __raw_writel(BM_SAIF_CTRL_CLKGATE, 380bbe8ff5eSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 381bbe8ff5eSDong Aisheng 3822a24f2ceSDong Aisheng return 0; 3832a24f2ceSDong Aisheng } 3842a24f2ceSDong Aisheng 3852a24f2ceSDong Aisheng /* 3862a24f2ceSDong Aisheng * Should only be called when port is inactive. 3872a24f2ceSDong Aisheng * although can be called multiple times by upper layers. 3882a24f2ceSDong Aisheng */ 3892a24f2ceSDong Aisheng static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 3902a24f2ceSDong Aisheng struct snd_pcm_hw_params *params, 3912a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 3922a24f2ceSDong Aisheng { 3932a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 3942a24f2ceSDong Aisheng u32 scr, stat; 3952a24f2ceSDong Aisheng int ret; 3962a24f2ceSDong Aisheng 3972a24f2ceSDong Aisheng /* mclk should already be set */ 3982a24f2ceSDong Aisheng if (!saif->mclk && saif->mclk_in_use) { 3992a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "set mclk first\n"); 4002a24f2ceSDong Aisheng return -EINVAL; 4012a24f2ceSDong Aisheng } 4022a24f2ceSDong Aisheng 4032a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 4042a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_BUSY) { 4052a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "error: busy\n"); 4062a24f2ceSDong Aisheng return -EBUSY; 4072a24f2ceSDong Aisheng } 4082a24f2ceSDong Aisheng 4092a24f2ceSDong Aisheng /* 4102a24f2ceSDong Aisheng * Set saif clk based on sample rate. 4112a24f2ceSDong Aisheng * If mclk is used, we also set mclk, if not, saif->mclk is 4122a24f2ceSDong Aisheng * default 0, means not used. 4132a24f2ceSDong Aisheng */ 4142a24f2ceSDong Aisheng ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 4152a24f2ceSDong Aisheng if (ret) { 4162a24f2ceSDong Aisheng dev_err(cpu_dai->dev, "unable to get proper clk\n"); 4172a24f2ceSDong Aisheng return ret; 4182a24f2ceSDong Aisheng } 4192a24f2ceSDong Aisheng 4202a24f2ceSDong Aisheng scr = __raw_readl(saif->base + SAIF_CTRL); 4212a24f2ceSDong Aisheng 4222a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 4232a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4242a24f2ceSDong Aisheng switch (params_format(params)) { 4252a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S16_LE: 4262a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 4272a24f2ceSDong Aisheng break; 4282a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S20_3LE: 4292a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 4302a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4312a24f2ceSDong Aisheng break; 4322a24f2ceSDong Aisheng case SNDRV_PCM_FORMAT_S24_LE: 4332a24f2ceSDong Aisheng scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 4342a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 4352a24f2ceSDong Aisheng break; 4362a24f2ceSDong Aisheng default: 4372a24f2ceSDong Aisheng return -EINVAL; 4382a24f2ceSDong Aisheng } 4392a24f2ceSDong Aisheng 4402a24f2ceSDong Aisheng /* Tx/Rx config */ 4412a24f2ceSDong Aisheng if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 4422a24f2ceSDong Aisheng /* enable TX mode */ 4432a24f2ceSDong Aisheng scr &= ~BM_SAIF_CTRL_READ_MODE; 4442a24f2ceSDong Aisheng } else { 4452a24f2ceSDong Aisheng /* enable RX mode */ 4462a24f2ceSDong Aisheng scr |= BM_SAIF_CTRL_READ_MODE; 4472a24f2ceSDong Aisheng } 4482a24f2ceSDong Aisheng 4492a24f2ceSDong Aisheng __raw_writel(scr, saif->base + SAIF_CTRL); 4502a24f2ceSDong Aisheng return 0; 4512a24f2ceSDong Aisheng } 4522a24f2ceSDong Aisheng 4532a24f2ceSDong Aisheng static int mxs_saif_prepare(struct snd_pcm_substream *substream, 4542a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 4552a24f2ceSDong Aisheng { 4562a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 4572a24f2ceSDong Aisheng 4582a24f2ceSDong Aisheng /* enable FIFO error irqs */ 4592a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 4602a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 4612a24f2ceSDong Aisheng 4622a24f2ceSDong Aisheng return 0; 4632a24f2ceSDong Aisheng } 4642a24f2ceSDong Aisheng 4652a24f2ceSDong Aisheng static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 4662a24f2ceSDong Aisheng struct snd_soc_dai *cpu_dai) 4672a24f2ceSDong Aisheng { 4682a24f2ceSDong Aisheng struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 46976067540SDong Aisheng struct mxs_saif *master_saif; 47076067540SDong Aisheng u32 delay; 47176067540SDong Aisheng 47276067540SDong Aisheng master_saif = mxs_saif_get_master(saif); 47376067540SDong Aisheng if (!master_saif) 47476067540SDong Aisheng return -EINVAL; 4752a24f2ceSDong Aisheng 4762a24f2ceSDong Aisheng switch (cmd) { 4772a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_START: 4782a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_RESUME: 4792a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 4802a24f2ceSDong Aisheng dev_dbg(cpu_dai->dev, "start\n"); 4812a24f2ceSDong Aisheng 48276067540SDong Aisheng clk_enable(master_saif->clk); 48376067540SDong Aisheng if (!master_saif->mclk_in_use) 48476067540SDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 48576067540SDong Aisheng master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 48676067540SDong Aisheng 48776067540SDong Aisheng /* 48876067540SDong Aisheng * If the saif's master is not himself, we also need to enable 48976067540SDong Aisheng * itself clk for its internal basic logic to work. 49076067540SDong Aisheng */ 49176067540SDong Aisheng if (saif != master_saif) { 4922a24f2ceSDong Aisheng clk_enable(saif->clk); 4932a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 4942a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_SET_ADDR); 49576067540SDong Aisheng } 4962a24f2ceSDong Aisheng 4972a24f2ceSDong Aisheng if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 4982a24f2ceSDong Aisheng /* 4992a24f2ceSDong Aisheng * write a data to saif data register to trigger 5002a24f2ceSDong Aisheng * the transfer 5012a24f2ceSDong Aisheng */ 5022a24f2ceSDong Aisheng __raw_writel(0, saif->base + SAIF_DATA); 5032a24f2ceSDong Aisheng } else { 5042a24f2ceSDong Aisheng /* 5052a24f2ceSDong Aisheng * read a data from saif data register to trigger 5062a24f2ceSDong Aisheng * the receive 5072a24f2ceSDong Aisheng */ 5082a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_DATA); 5092a24f2ceSDong Aisheng } 5102a24f2ceSDong Aisheng 51176067540SDong Aisheng master_saif->ongoing = 1; 51276067540SDong Aisheng 51376067540SDong Aisheng dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 5142a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_CTRL), 5152a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_STAT)); 5162a24f2ceSDong Aisheng 51776067540SDong Aisheng dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 51876067540SDong Aisheng __raw_readl(master_saif->base + SAIF_CTRL), 51976067540SDong Aisheng __raw_readl(master_saif->base + SAIF_STAT)); 5202a24f2ceSDong Aisheng break; 5212a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_SUSPEND: 5222a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_STOP: 5232a24f2ceSDong Aisheng case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 5242a24f2ceSDong Aisheng dev_dbg(cpu_dai->dev, "stop\n"); 5252a24f2ceSDong Aisheng 52676067540SDong Aisheng /* wait a while for the current sample to complete */ 52776067540SDong Aisheng delay = USEC_PER_SEC / master_saif->cur_rate; 52876067540SDong Aisheng 52976067540SDong Aisheng if (!master_saif->mclk_in_use) { 53076067540SDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 53176067540SDong Aisheng master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 53276067540SDong Aisheng udelay(delay); 53376067540SDong Aisheng } 53476067540SDong Aisheng clk_disable(master_saif->clk); 53576067540SDong Aisheng 53676067540SDong Aisheng if (saif != master_saif) { 5372a24f2ceSDong Aisheng __raw_writel(BM_SAIF_CTRL_RUN, 5382a24f2ceSDong Aisheng saif->base + SAIF_CTRL + MXS_CLR_ADDR); 53976067540SDong Aisheng udelay(delay); 54076067540SDong Aisheng clk_disable(saif->clk); 54176067540SDong Aisheng } 54276067540SDong Aisheng 54376067540SDong Aisheng master_saif->ongoing = 0; 5442a24f2ceSDong Aisheng 5452a24f2ceSDong Aisheng break; 5462a24f2ceSDong Aisheng default: 5472a24f2ceSDong Aisheng return -EINVAL; 5482a24f2ceSDong Aisheng } 5492a24f2ceSDong Aisheng 5502a24f2ceSDong Aisheng return 0; 5512a24f2ceSDong Aisheng } 5522a24f2ceSDong Aisheng 5532a24f2ceSDong Aisheng #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 5542a24f2ceSDong Aisheng #define MXS_SAIF_FORMATS \ 5552a24f2ceSDong Aisheng (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 5562a24f2ceSDong Aisheng SNDRV_PCM_FMTBIT_S24_LE) 5572a24f2ceSDong Aisheng 55885e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 5592a24f2ceSDong Aisheng .startup = mxs_saif_startup, 5602a24f2ceSDong Aisheng .trigger = mxs_saif_trigger, 5612a24f2ceSDong Aisheng .prepare = mxs_saif_prepare, 5622a24f2ceSDong Aisheng .hw_params = mxs_saif_hw_params, 5632a24f2ceSDong Aisheng .set_sysclk = mxs_saif_set_dai_sysclk, 5642a24f2ceSDong Aisheng .set_fmt = mxs_saif_set_dai_fmt, 5652a24f2ceSDong Aisheng }; 5662a24f2ceSDong Aisheng 5672a24f2ceSDong Aisheng static int mxs_saif_dai_probe(struct snd_soc_dai *dai) 5682a24f2ceSDong Aisheng { 5692a24f2ceSDong Aisheng struct mxs_saif *saif = dev_get_drvdata(dai->dev); 5702a24f2ceSDong Aisheng 5712a24f2ceSDong Aisheng snd_soc_dai_set_drvdata(dai, saif); 5722a24f2ceSDong Aisheng 5732a24f2ceSDong Aisheng return 0; 5742a24f2ceSDong Aisheng } 5752a24f2ceSDong Aisheng 5762a24f2ceSDong Aisheng static struct snd_soc_dai_driver mxs_saif_dai = { 5772a24f2ceSDong Aisheng .name = "mxs-saif", 5782a24f2ceSDong Aisheng .probe = mxs_saif_dai_probe, 5792a24f2ceSDong Aisheng .playback = { 5802a24f2ceSDong Aisheng .channels_min = 2, 5812a24f2ceSDong Aisheng .channels_max = 2, 5822a24f2ceSDong Aisheng .rates = MXS_SAIF_RATES, 5832a24f2ceSDong Aisheng .formats = MXS_SAIF_FORMATS, 5842a24f2ceSDong Aisheng }, 5852a24f2ceSDong Aisheng .capture = { 5862a24f2ceSDong Aisheng .channels_min = 2, 5872a24f2ceSDong Aisheng .channels_max = 2, 5882a24f2ceSDong Aisheng .rates = MXS_SAIF_RATES, 5892a24f2ceSDong Aisheng .formats = MXS_SAIF_FORMATS, 5902a24f2ceSDong Aisheng }, 5912a24f2ceSDong Aisheng .ops = &mxs_saif_dai_ops, 5922a24f2ceSDong Aisheng }; 5932a24f2ceSDong Aisheng 5942a24f2ceSDong Aisheng static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 5952a24f2ceSDong Aisheng { 5962a24f2ceSDong Aisheng struct mxs_saif *saif = dev_id; 5972a24f2ceSDong Aisheng unsigned int stat; 5982a24f2ceSDong Aisheng 5992a24f2ceSDong Aisheng stat = __raw_readl(saif->base + SAIF_STAT); 6002a24f2ceSDong Aisheng if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 6012a24f2ceSDong Aisheng BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 6022a24f2ceSDong Aisheng return IRQ_NONE; 6032a24f2ceSDong Aisheng 6042a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 6052a24f2ceSDong Aisheng dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 6062a24f2ceSDong Aisheng __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 6072a24f2ceSDong Aisheng saif->base + SAIF_STAT + MXS_CLR_ADDR); 6082a24f2ceSDong Aisheng } 6092a24f2ceSDong Aisheng 6102a24f2ceSDong Aisheng if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 6112a24f2ceSDong Aisheng dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 6122a24f2ceSDong Aisheng __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 6132a24f2ceSDong Aisheng saif->base + SAIF_STAT + MXS_CLR_ADDR); 6142a24f2ceSDong Aisheng } 6152a24f2ceSDong Aisheng 6162a24f2ceSDong Aisheng dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 6172a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_CTRL), 6182a24f2ceSDong Aisheng __raw_readl(saif->base + SAIF_STAT)); 6192a24f2ceSDong Aisheng 6202a24f2ceSDong Aisheng return IRQ_HANDLED; 6212a24f2ceSDong Aisheng } 6222a24f2ceSDong Aisheng 6232a24f2ceSDong Aisheng static int mxs_saif_probe(struct platform_device *pdev) 6242a24f2ceSDong Aisheng { 625226d0f22SJulia Lawall struct resource *iores, *dmares; 6262a24f2ceSDong Aisheng struct mxs_saif *saif; 62776067540SDong Aisheng struct mxs_saif_platform_data *pdata; 6282a24f2ceSDong Aisheng int ret = 0; 6292a24f2ceSDong Aisheng 6300bb98ba2SJulia Lawall if (pdev->id >= ARRAY_SIZE(mxs_saif)) 6310bb98ba2SJulia Lawall return -EINVAL; 6320bb98ba2SJulia Lawall 633830eb876SJulia Lawall saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 6342a24f2ceSDong Aisheng if (!saif) 6352a24f2ceSDong Aisheng return -ENOMEM; 6362a24f2ceSDong Aisheng 6372a24f2ceSDong Aisheng mxs_saif[pdev->id] = saif; 63876067540SDong Aisheng saif->id = pdev->id; 63976067540SDong Aisheng 64077882580SDong Aisheng pdata = pdev->dev.platform_data; 64177882580SDong Aisheng if (pdata && !pdata->master_mode) { 64277882580SDong Aisheng saif->master_id = pdata->master_id; 64376067540SDong Aisheng if (saif->master_id < 0 || 64477882580SDong Aisheng saif->master_id >= ARRAY_SIZE(mxs_saif) || 64577882580SDong Aisheng saif->master_id == saif->id) { 64677882580SDong Aisheng dev_err(&pdev->dev, "get wrong master id\n"); 64776067540SDong Aisheng return -EINVAL; 64876067540SDong Aisheng } 64977882580SDong Aisheng } else { 65077882580SDong Aisheng saif->master_id = saif->id; 65177882580SDong Aisheng } 6522a24f2ceSDong Aisheng 6532a24f2ceSDong Aisheng saif->clk = clk_get(&pdev->dev, NULL); 6542a24f2ceSDong Aisheng if (IS_ERR(saif->clk)) { 6552a24f2ceSDong Aisheng ret = PTR_ERR(saif->clk); 6562a24f2ceSDong Aisheng dev_err(&pdev->dev, "Cannot get the clock: %d\n", 6572a24f2ceSDong Aisheng ret); 658830eb876SJulia Lawall return ret; 6592a24f2ceSDong Aisheng } 6602a24f2ceSDong Aisheng 661226d0f22SJulia Lawall iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 6622a24f2ceSDong Aisheng 663830eb876SJulia Lawall saif->base = devm_request_and_ioremap(&pdev->dev, iores); 6642a24f2ceSDong Aisheng if (!saif->base) { 6652a24f2ceSDong Aisheng dev_err(&pdev->dev, "ioremap failed\n"); 6662a24f2ceSDong Aisheng ret = -ENODEV; 667830eb876SJulia Lawall goto failed_get_resource; 6682a24f2ceSDong Aisheng } 6692a24f2ceSDong Aisheng 670226d0f22SJulia Lawall dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 671226d0f22SJulia Lawall if (!dmares) { 6722a24f2ceSDong Aisheng ret = -ENODEV; 6732a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to get dma resource: %d\n", 6742a24f2ceSDong Aisheng ret); 675830eb876SJulia Lawall goto failed_get_resource; 6762a24f2ceSDong Aisheng } 677226d0f22SJulia Lawall saif->dma_param.chan_num = dmares->start; 6782a24f2ceSDong Aisheng 6792a24f2ceSDong Aisheng saif->irq = platform_get_irq(pdev, 0); 6802a24f2ceSDong Aisheng if (saif->irq < 0) { 6812a24f2ceSDong Aisheng ret = saif->irq; 6822a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to get irq resource: %d\n", 6832a24f2ceSDong Aisheng ret); 684830eb876SJulia Lawall goto failed_get_resource; 6852a24f2ceSDong Aisheng } 6862a24f2ceSDong Aisheng 6872a24f2ceSDong Aisheng saif->dev = &pdev->dev; 688830eb876SJulia Lawall ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0, 689830eb876SJulia Lawall "mxs-saif", saif); 6902a24f2ceSDong Aisheng if (ret) { 6912a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to request irq\n"); 692830eb876SJulia Lawall goto failed_get_resource; 6932a24f2ceSDong Aisheng } 6942a24f2ceSDong Aisheng 6952a24f2ceSDong Aisheng saif->dma_param.chan_irq = platform_get_irq(pdev, 1); 6962a24f2ceSDong Aisheng if (saif->dma_param.chan_irq < 0) { 6972a24f2ceSDong Aisheng ret = saif->dma_param.chan_irq; 6982a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to get dma irq resource: %d\n", 6992a24f2ceSDong Aisheng ret); 700830eb876SJulia Lawall goto failed_get_resource; 7012a24f2ceSDong Aisheng } 7022a24f2ceSDong Aisheng 7032a24f2ceSDong Aisheng platform_set_drvdata(pdev, saif); 7042a24f2ceSDong Aisheng 7052a24f2ceSDong Aisheng ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai); 7062a24f2ceSDong Aisheng if (ret) { 7072a24f2ceSDong Aisheng dev_err(&pdev->dev, "register DAI failed\n"); 708830eb876SJulia Lawall goto failed_get_resource; 7092a24f2ceSDong Aisheng } 7102a24f2ceSDong Aisheng 7112a24f2ceSDong Aisheng saif->soc_platform_pdev = platform_device_alloc( 7122a24f2ceSDong Aisheng "mxs-pcm-audio", pdev->id); 7132a24f2ceSDong Aisheng if (!saif->soc_platform_pdev) { 7142a24f2ceSDong Aisheng ret = -ENOMEM; 7152a24f2ceSDong Aisheng goto failed_pdev_alloc; 7162a24f2ceSDong Aisheng } 7172a24f2ceSDong Aisheng 7182a24f2ceSDong Aisheng platform_set_drvdata(saif->soc_platform_pdev, saif); 7192a24f2ceSDong Aisheng ret = platform_device_add(saif->soc_platform_pdev); 7202a24f2ceSDong Aisheng if (ret) { 7212a24f2ceSDong Aisheng dev_err(&pdev->dev, "failed to add soc platform device\n"); 7222a24f2ceSDong Aisheng goto failed_pdev_add; 7232a24f2ceSDong Aisheng } 7242a24f2ceSDong Aisheng 7252a24f2ceSDong Aisheng return 0; 7262a24f2ceSDong Aisheng 7272a24f2ceSDong Aisheng failed_pdev_add: 7282a24f2ceSDong Aisheng platform_device_put(saif->soc_platform_pdev); 7292a24f2ceSDong Aisheng failed_pdev_alloc: 7302a24f2ceSDong Aisheng snd_soc_unregister_dai(&pdev->dev); 7312a24f2ceSDong Aisheng failed_get_resource: 7322a24f2ceSDong Aisheng clk_put(saif->clk); 7332a24f2ceSDong Aisheng 7342a24f2ceSDong Aisheng return ret; 7352a24f2ceSDong Aisheng } 7362a24f2ceSDong Aisheng 7372a24f2ceSDong Aisheng static int __devexit mxs_saif_remove(struct platform_device *pdev) 7382a24f2ceSDong Aisheng { 7392a24f2ceSDong Aisheng struct mxs_saif *saif = platform_get_drvdata(pdev); 7402a24f2ceSDong Aisheng 7412a24f2ceSDong Aisheng platform_device_unregister(saif->soc_platform_pdev); 7422a24f2ceSDong Aisheng snd_soc_unregister_dai(&pdev->dev); 7432a24f2ceSDong Aisheng clk_put(saif->clk); 7442a24f2ceSDong Aisheng 7452a24f2ceSDong Aisheng return 0; 7462a24f2ceSDong Aisheng } 7472a24f2ceSDong Aisheng 7482a24f2ceSDong Aisheng static struct platform_driver mxs_saif_driver = { 7492a24f2ceSDong Aisheng .probe = mxs_saif_probe, 7502a24f2ceSDong Aisheng .remove = __devexit_p(mxs_saif_remove), 7512a24f2ceSDong Aisheng 7522a24f2ceSDong Aisheng .driver = { 7532a24f2ceSDong Aisheng .name = "mxs-saif", 7542a24f2ceSDong Aisheng .owner = THIS_MODULE, 7552a24f2ceSDong Aisheng }, 7562a24f2ceSDong Aisheng }; 7572a24f2ceSDong Aisheng 75885aa0960SAxel Lin module_platform_driver(mxs_saif_driver); 7592a24f2ceSDong Aisheng 7602a24f2ceSDong Aisheng MODULE_AUTHOR("Freescale Semiconductor, Inc."); 7612a24f2ceSDong Aisheng MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 7622a24f2ceSDong Aisheng MODULE_LICENSE("GPL"); 763