1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 // 3 // Copyright (c) 2018 BayLibre, SAS. 4 // Author: Jerome Brunet <jbrunet@baylibre.com> 5 6 #include <linux/module.h> 7 #include <linux/of_platform.h> 8 #include <linux/regmap.h> 9 #include <sound/soc.h> 10 #include <sound/soc-dai.h> 11 12 #include "axg-tdm-formatter.h" 13 14 #define TDMIN_CTRL 0x00 15 #define TDMIN_CTRL_ENABLE BIT(31) 16 #define TDMIN_CTRL_I2S_MODE BIT(30) 17 #define TDMIN_CTRL_RST_OUT BIT(29) 18 #define TDMIN_CTRL_RST_IN BIT(28) 19 #define TDMIN_CTRL_WS_INV BIT(25) 20 #define TDMIN_CTRL_SEL_SHIFT 20 21 #define TDMIN_CTRL_IN_BIT_SKEW_MASK GENMASK(18, 16) 22 #define TDMIN_CTRL_IN_BIT_SKEW(x) ((x) << 16) 23 #define TDMIN_CTRL_LSB_FIRST BIT(5) 24 #define TDMIN_CTRL_BITNUM_MASK GENMASK(4, 0) 25 #define TDMIN_CTRL_BITNUM(x) ((x) << 0) 26 #define TDMIN_SWAP 0x04 27 #define TDMIN_MASK0 0x08 28 #define TDMIN_MASK1 0x0c 29 #define TDMIN_MASK2 0x10 30 #define TDMIN_MASK3 0x14 31 #define TDMIN_STAT 0x18 32 #define TDMIN_MUTE_VAL 0x1c 33 #define TDMIN_MUTE0 0x20 34 #define TDMIN_MUTE1 0x24 35 #define TDMIN_MUTE2 0x28 36 #define TDMIN_MUTE3 0x2c 37 38 static const struct regmap_config axg_tdmin_regmap_cfg = { 39 .reg_bits = 32, 40 .val_bits = 32, 41 .reg_stride = 4, 42 .max_register = TDMIN_MUTE3, 43 }; 44 45 static const char * const axg_tdmin_sel_texts[] = { 46 "IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", 47 }; 48 49 /* Change to special mux control to reset dapm */ 50 static SOC_ENUM_SINGLE_DECL(axg_tdmin_sel_enum, TDMIN_CTRL, 51 TDMIN_CTRL_SEL_SHIFT, axg_tdmin_sel_texts); 52 53 static const struct snd_kcontrol_new axg_tdmin_in_mux = 54 SOC_DAPM_ENUM("Input Source", axg_tdmin_sel_enum); 55 56 static struct snd_soc_dai * 57 axg_tdmin_get_be(struct snd_soc_dapm_widget *w) 58 { 59 struct snd_soc_dapm_path *p = NULL; 60 struct snd_soc_dai *be; 61 62 snd_soc_dapm_widget_for_each_source_path(w, p) { 63 if (!p->connect) 64 continue; 65 66 if (p->source->id == snd_soc_dapm_dai_out) 67 return (struct snd_soc_dai *)p->source->priv; 68 69 be = axg_tdmin_get_be(p->source); 70 if (be) 71 return be; 72 } 73 74 return NULL; 75 } 76 77 static struct axg_tdm_stream * 78 axg_tdmin_get_tdm_stream(struct snd_soc_dapm_widget *w) 79 { 80 struct snd_soc_dai *be = axg_tdmin_get_be(w); 81 82 if (!be) 83 return NULL; 84 85 return be->capture_dma_data; 86 } 87 88 static void axg_tdmin_enable(struct regmap *map) 89 { 90 /* Apply both reset */ 91 regmap_update_bits(map, TDMIN_CTRL, 92 TDMIN_CTRL_RST_OUT | TDMIN_CTRL_RST_IN, 0); 93 94 /* Clear out reset before in reset */ 95 regmap_update_bits(map, TDMIN_CTRL, 96 TDMIN_CTRL_RST_OUT, TDMIN_CTRL_RST_OUT); 97 regmap_update_bits(map, TDMIN_CTRL, 98 TDMIN_CTRL_RST_IN, TDMIN_CTRL_RST_IN); 99 100 /* Actually enable tdmin */ 101 regmap_update_bits(map, TDMIN_CTRL, 102 TDMIN_CTRL_ENABLE, TDMIN_CTRL_ENABLE); 103 } 104 105 static void axg_tdmin_disable(struct regmap *map) 106 { 107 regmap_update_bits(map, TDMIN_CTRL, TDMIN_CTRL_ENABLE, 0); 108 } 109 110 static int axg_tdmin_prepare(struct regmap *map, 111 const struct axg_tdm_formatter_hw *quirks, 112 struct axg_tdm_stream *ts) 113 { 114 unsigned int val, skew = quirks->skew_offset; 115 116 /* Set stream skew */ 117 switch (ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 118 case SND_SOC_DAIFMT_I2S: 119 case SND_SOC_DAIFMT_DSP_A: 120 skew += 1; 121 break; 122 123 case SND_SOC_DAIFMT_LEFT_J: 124 case SND_SOC_DAIFMT_RIGHT_J: 125 case SND_SOC_DAIFMT_DSP_B: 126 break; 127 128 default: 129 pr_err("Unsupported format: %u\n", 130 ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK); 131 return -EINVAL; 132 } 133 134 val = TDMIN_CTRL_IN_BIT_SKEW(skew); 135 136 /* Set stream format mode */ 137 switch (ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 138 case SND_SOC_DAIFMT_I2S: 139 case SND_SOC_DAIFMT_LEFT_J: 140 case SND_SOC_DAIFMT_RIGHT_J: 141 val |= TDMIN_CTRL_I2S_MODE; 142 break; 143 } 144 145 /* If the sample clock is inverted, invert it back for the formatter */ 146 if (axg_tdm_lrclk_invert(ts->iface->fmt)) 147 val |= TDMIN_CTRL_WS_INV; 148 149 /* Set the slot width */ 150 val |= TDMIN_CTRL_BITNUM(ts->iface->slot_width - 1); 151 152 /* 153 * The following also reset LSB_FIRST which result in the formatter 154 * placing the first bit received at bit 31 155 */ 156 regmap_update_bits(map, TDMIN_CTRL, 157 (TDMIN_CTRL_IN_BIT_SKEW_MASK | TDMIN_CTRL_WS_INV | 158 TDMIN_CTRL_I2S_MODE | TDMIN_CTRL_LSB_FIRST | 159 TDMIN_CTRL_BITNUM_MASK), val); 160 161 /* Set static swap mask configuration */ 162 regmap_write(map, TDMIN_SWAP, 0x76543210); 163 164 return axg_tdm_formatter_set_channel_masks(map, ts, TDMIN_MASK0); 165 } 166 167 static const struct snd_soc_dapm_widget axg_tdmin_dapm_widgets[] = { 168 SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0), 169 SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0), 170 SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0), 171 SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0), 172 SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0), 173 SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0), 174 SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_tdmin_in_mux), 175 SND_SOC_DAPM_PGA_E("DEC", SND_SOC_NOPM, 0, 0, NULL, 0, 176 axg_tdm_formatter_event, 177 (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD)), 178 SND_SOC_DAPM_AIF_OUT("OUT", NULL, 0, SND_SOC_NOPM, 0, 0), 179 }; 180 181 static const struct snd_soc_dapm_route axg_tdmin_dapm_routes[] = { 182 { "SRC SEL", "IN 0", "IN 0" }, 183 { "SRC SEL", "IN 1", "IN 1" }, 184 { "SRC SEL", "IN 2", "IN 2" }, 185 { "SRC SEL", "IN 3", "IN 3" }, 186 { "SRC SEL", "IN 4", "IN 4" }, 187 { "SRC SEL", "IN 5", "IN 5" }, 188 { "DEC", NULL, "SRC SEL" }, 189 { "OUT", NULL, "DEC" }, 190 }; 191 192 static const struct snd_soc_component_driver axg_tdmin_component_drv = { 193 .dapm_widgets = axg_tdmin_dapm_widgets, 194 .num_dapm_widgets = ARRAY_SIZE(axg_tdmin_dapm_widgets), 195 .dapm_routes = axg_tdmin_dapm_routes, 196 .num_dapm_routes = ARRAY_SIZE(axg_tdmin_dapm_routes), 197 }; 198 199 static const struct axg_tdm_formatter_ops axg_tdmin_ops = { 200 .get_stream = axg_tdmin_get_tdm_stream, 201 .prepare = axg_tdmin_prepare, 202 .enable = axg_tdmin_enable, 203 .disable = axg_tdmin_disable, 204 }; 205 206 static const struct axg_tdm_formatter_driver axg_tdmin_drv = { 207 .component_drv = &axg_tdmin_component_drv, 208 .regmap_cfg = &axg_tdmin_regmap_cfg, 209 .ops = &axg_tdmin_ops, 210 .quirks = &(const struct axg_tdm_formatter_hw) { 211 .invert_sclk = false, 212 .skew_offset = 2, 213 }, 214 }; 215 216 static const struct of_device_id axg_tdmin_of_match[] = { 217 { 218 .compatible = "amlogic,axg-tdmin", 219 .data = &axg_tdmin_drv, 220 }, {} 221 }; 222 MODULE_DEVICE_TABLE(of, axg_tdmin_of_match); 223 224 static struct platform_driver axg_tdmin_pdrv = { 225 .probe = axg_tdm_formatter_probe, 226 .driver = { 227 .name = "axg-tdmin", 228 .of_match_table = axg_tdmin_of_match, 229 }, 230 }; 231 module_platform_driver(axg_tdmin_pdrv); 232 233 MODULE_DESCRIPTION("Amlogic AXG TDM input formatter driver"); 234 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 235 MODULE_LICENSE("GPL v2"); 236