1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 // 3 // Copyright (c) 2018 BayLibre, SAS. 4 // Author: Jerome Brunet <jbrunet@baylibre.com> 5 6 /* 7 * This driver implements the frontend playback DAI of AXG and G12A based SoCs 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/regmap.h> 12 #include <linux/module.h> 13 #include <linux/of_platform.h> 14 #include <sound/soc.h> 15 #include <sound/soc-dai.h> 16 17 #include "axg-fifo.h" 18 19 #define CTRL0_FRDDR_PP_MODE BIT(30) 20 #define CTRL0_SEL1_EN_SHIFT 3 21 #define CTRL0_SEL2_SHIFT 4 22 #define CTRL0_SEL2_EN_SHIFT 7 23 #define CTRL0_SEL3_SHIFT 8 24 #define CTRL0_SEL3_EN_SHIFT 11 25 #define CTRL1_FRDDR_FORCE_FINISH BIT(12) 26 #define CTRL2_SEL1_SHIFT 0 27 #define CTRL2_SEL1_EN_SHIFT 4 28 #define CTRL2_SEL2_SHIFT 8 29 #define CTRL2_SEL2_EN_SHIFT 12 30 #define CTRL2_SEL3_SHIFT 16 31 #define CTRL2_SEL3_EN_SHIFT 20 32 33 static int g12a_frddr_dai_prepare(struct snd_pcm_substream *substream, 34 struct snd_soc_dai *dai) 35 { 36 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); 37 38 /* Reset the read pointer to the FIFO_INIT_ADDR */ 39 regmap_update_bits(fifo->map, FIFO_CTRL1, 40 CTRL1_FRDDR_FORCE_FINISH, 0); 41 regmap_update_bits(fifo->map, FIFO_CTRL1, 42 CTRL1_FRDDR_FORCE_FINISH, CTRL1_FRDDR_FORCE_FINISH); 43 regmap_update_bits(fifo->map, FIFO_CTRL1, 44 CTRL1_FRDDR_FORCE_FINISH, 0); 45 46 return 0; 47 } 48 49 static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, 50 struct snd_soc_dai *dai) 51 { 52 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); 53 unsigned int fifo_depth; 54 int ret; 55 56 /* Enable pclk to access registers and clock the fifo ip */ 57 ret = clk_prepare_enable(fifo->pclk); 58 if (ret) 59 return ret; 60 61 /* Apply single buffer mode to the interface */ 62 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0); 63 64 /* 65 * TODO: We could adapt the fifo depth and the fifo threshold 66 * depending on the expected memory throughput and lantencies 67 * For now, we'll just use the same values as the vendor kernel 68 * Depth and threshold are zero based. 69 */ 70 fifo_depth = AXG_FIFO_MIN_CNT - 1; 71 regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK, 72 CTRL1_FRDDR_DEPTH(fifo_depth)); 73 74 return 0; 75 } 76 77 static void axg_frddr_dai_shutdown(struct snd_pcm_substream *substream, 78 struct snd_soc_dai *dai) 79 { 80 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); 81 82 clk_disable_unprepare(fifo->pclk); 83 } 84 85 static int axg_frddr_pcm_new(struct snd_soc_pcm_runtime *rtd, 86 struct snd_soc_dai *dai) 87 { 88 return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_PLAYBACK); 89 } 90 91 static const struct snd_soc_dai_ops axg_frddr_ops = { 92 .startup = axg_frddr_dai_startup, 93 .shutdown = axg_frddr_dai_shutdown, 94 }; 95 96 static struct snd_soc_dai_driver axg_frddr_dai_drv = { 97 .name = "FRDDR", 98 .playback = { 99 .stream_name = "Playback", 100 .channels_min = 1, 101 .channels_max = AXG_FIFO_CH_MAX, 102 .rates = AXG_FIFO_RATES, 103 .formats = AXG_FIFO_FORMATS, 104 }, 105 .ops = &axg_frddr_ops, 106 .pcm_new = axg_frddr_pcm_new, 107 }; 108 109 static const char * const axg_frddr_sel_texts[] = { 110 "OUT 0", "OUT 1", "OUT 2", "OUT 3", "OUT 4", "OUT 5", "OUT 6", "OUT 7", 111 }; 112 113 static SOC_ENUM_SINGLE_DECL(axg_frddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT, 114 axg_frddr_sel_texts); 115 116 static const struct snd_kcontrol_new axg_frddr_out_demux = 117 SOC_DAPM_ENUM("Output Sink", axg_frddr_sel_enum); 118 119 static const struct snd_soc_dapm_widget axg_frddr_dapm_widgets[] = { 120 SND_SOC_DAPM_DEMUX("SINK SEL", SND_SOC_NOPM, 0, 0, 121 &axg_frddr_out_demux), 122 SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0), 123 SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0), 124 SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0), 125 SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0), 126 SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0), 127 SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0), 128 SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0), 129 SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0), 130 }; 131 132 static const struct snd_soc_dapm_route axg_frddr_dapm_routes[] = { 133 { "SINK SEL", NULL, "Playback" }, 134 { "OUT 0", "OUT 0", "SINK SEL" }, 135 { "OUT 1", "OUT 1", "SINK SEL" }, 136 { "OUT 2", "OUT 2", "SINK SEL" }, 137 { "OUT 3", "OUT 3", "SINK SEL" }, 138 { "OUT 4", "OUT 4", "SINK SEL" }, 139 { "OUT 5", "OUT 5", "SINK SEL" }, 140 { "OUT 6", "OUT 6", "SINK SEL" }, 141 { "OUT 7", "OUT 7", "SINK SEL" }, 142 }; 143 144 static const struct snd_soc_component_driver axg_frddr_component_drv = { 145 .dapm_widgets = axg_frddr_dapm_widgets, 146 .num_dapm_widgets = ARRAY_SIZE(axg_frddr_dapm_widgets), 147 .dapm_routes = axg_frddr_dapm_routes, 148 .num_dapm_routes = ARRAY_SIZE(axg_frddr_dapm_routes), 149 .open = axg_fifo_pcm_open, 150 .close = axg_fifo_pcm_close, 151 .hw_params = axg_fifo_pcm_hw_params, 152 .hw_free = axg_fifo_pcm_hw_free, 153 .pointer = axg_fifo_pcm_pointer, 154 .trigger = axg_fifo_pcm_trigger, 155 }; 156 157 static const struct axg_fifo_match_data axg_frddr_match_data = { 158 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23), 159 .component_drv = &axg_frddr_component_drv, 160 .dai_drv = &axg_frddr_dai_drv 161 }; 162 163 static const struct snd_soc_dai_ops g12a_frddr_ops = { 164 .prepare = g12a_frddr_dai_prepare, 165 .startup = axg_frddr_dai_startup, 166 .shutdown = axg_frddr_dai_shutdown, 167 }; 168 169 static struct snd_soc_dai_driver g12a_frddr_dai_drv = { 170 .name = "FRDDR", 171 .playback = { 172 .stream_name = "Playback", 173 .channels_min = 1, 174 .channels_max = AXG_FIFO_CH_MAX, 175 .rates = AXG_FIFO_RATES, 176 .formats = AXG_FIFO_FORMATS, 177 }, 178 .ops = &g12a_frddr_ops, 179 .pcm_new = axg_frddr_pcm_new, 180 }; 181 182 static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel1_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT, 183 axg_frddr_sel_texts); 184 static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel2_enum, FIFO_CTRL0, CTRL0_SEL2_SHIFT, 185 axg_frddr_sel_texts); 186 static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel3_enum, FIFO_CTRL0, CTRL0_SEL3_SHIFT, 187 axg_frddr_sel_texts); 188 189 static const struct snd_kcontrol_new g12a_frddr_out1_demux = 190 SOC_DAPM_ENUM("Output Src 1", g12a_frddr_sel1_enum); 191 static const struct snd_kcontrol_new g12a_frddr_out2_demux = 192 SOC_DAPM_ENUM("Output Src 2", g12a_frddr_sel2_enum); 193 static const struct snd_kcontrol_new g12a_frddr_out3_demux = 194 SOC_DAPM_ENUM("Output Src 3", g12a_frddr_sel3_enum); 195 196 static const struct snd_kcontrol_new g12a_frddr_out1_enable = 197 SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0, 198 CTRL0_SEL1_EN_SHIFT, 1, 0); 199 static const struct snd_kcontrol_new g12a_frddr_out2_enable = 200 SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0, 201 CTRL0_SEL2_EN_SHIFT, 1, 0); 202 static const struct snd_kcontrol_new g12a_frddr_out3_enable = 203 SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0, 204 CTRL0_SEL3_EN_SHIFT, 1, 0); 205 206 static const struct snd_soc_dapm_widget g12a_frddr_dapm_widgets[] = { 207 SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0), 208 SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0), 209 SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0), 210 SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0, 211 &g12a_frddr_out1_enable), 212 SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0, 213 &g12a_frddr_out2_enable), 214 SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0, 215 &g12a_frddr_out3_enable), 216 SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0, 217 &g12a_frddr_out1_demux), 218 SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0, 219 &g12a_frddr_out2_demux), 220 SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0, 221 &g12a_frddr_out3_demux), 222 SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0), 223 SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0), 224 SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0), 225 SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0), 226 SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0), 227 SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0), 228 SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0), 229 SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0), 230 }; 231 232 static const struct snd_soc_dapm_route g12a_frddr_dapm_routes[] = { 233 { "SRC 1", NULL, "Playback" }, 234 { "SRC 2", NULL, "Playback" }, 235 { "SRC 3", NULL, "Playback" }, 236 { "SRC 1 EN", "Switch", "SRC 1" }, 237 { "SRC 2 EN", "Switch", "SRC 2" }, 238 { "SRC 3 EN", "Switch", "SRC 3" }, 239 { "SINK 1 SEL", NULL, "SRC 1 EN" }, 240 { "SINK 2 SEL", NULL, "SRC 2 EN" }, 241 { "SINK 3 SEL", NULL, "SRC 3 EN" }, 242 { "OUT 0", "OUT 0", "SINK 1 SEL" }, 243 { "OUT 1", "OUT 1", "SINK 1 SEL" }, 244 { "OUT 2", "OUT 2", "SINK 1 SEL" }, 245 { "OUT 3", "OUT 3", "SINK 1 SEL" }, 246 { "OUT 4", "OUT 4", "SINK 1 SEL" }, 247 { "OUT 5", "OUT 5", "SINK 1 SEL" }, 248 { "OUT 6", "OUT 6", "SINK 1 SEL" }, 249 { "OUT 7", "OUT 7", "SINK 1 SEL" }, 250 { "OUT 0", "OUT 0", "SINK 2 SEL" }, 251 { "OUT 1", "OUT 1", "SINK 2 SEL" }, 252 { "OUT 2", "OUT 2", "SINK 2 SEL" }, 253 { "OUT 3", "OUT 3", "SINK 2 SEL" }, 254 { "OUT 4", "OUT 4", "SINK 2 SEL" }, 255 { "OUT 5", "OUT 5", "SINK 2 SEL" }, 256 { "OUT 6", "OUT 6", "SINK 2 SEL" }, 257 { "OUT 7", "OUT 7", "SINK 2 SEL" }, 258 { "OUT 0", "OUT 0", "SINK 3 SEL" }, 259 { "OUT 1", "OUT 1", "SINK 3 SEL" }, 260 { "OUT 2", "OUT 2", "SINK 3 SEL" }, 261 { "OUT 3", "OUT 3", "SINK 3 SEL" }, 262 { "OUT 4", "OUT 4", "SINK 3 SEL" }, 263 { "OUT 5", "OUT 5", "SINK 3 SEL" }, 264 { "OUT 6", "OUT 6", "SINK 3 SEL" }, 265 { "OUT 7", "OUT 7", "SINK 3 SEL" }, 266 }; 267 268 static const struct snd_soc_component_driver g12a_frddr_component_drv = { 269 .dapm_widgets = g12a_frddr_dapm_widgets, 270 .num_dapm_widgets = ARRAY_SIZE(g12a_frddr_dapm_widgets), 271 .dapm_routes = g12a_frddr_dapm_routes, 272 .num_dapm_routes = ARRAY_SIZE(g12a_frddr_dapm_routes), 273 .open = axg_fifo_pcm_open, 274 .close = axg_fifo_pcm_close, 275 .hw_params = g12a_fifo_pcm_hw_params, 276 .hw_free = axg_fifo_pcm_hw_free, 277 .pointer = axg_fifo_pcm_pointer, 278 .trigger = axg_fifo_pcm_trigger, 279 }; 280 281 static const struct axg_fifo_match_data g12a_frddr_match_data = { 282 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23), 283 .component_drv = &g12a_frddr_component_drv, 284 .dai_drv = &g12a_frddr_dai_drv 285 }; 286 287 /* On SM1, the output selection in on CTRL2 */ 288 static const struct snd_kcontrol_new sm1_frddr_out1_enable = 289 SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2, 290 CTRL2_SEL1_EN_SHIFT, 1, 0); 291 static const struct snd_kcontrol_new sm1_frddr_out2_enable = 292 SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2, 293 CTRL2_SEL2_EN_SHIFT, 1, 0); 294 static const struct snd_kcontrol_new sm1_frddr_out3_enable = 295 SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2, 296 CTRL2_SEL3_EN_SHIFT, 1, 0); 297 298 static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel1_enum, FIFO_CTRL2, CTRL2_SEL1_SHIFT, 299 axg_frddr_sel_texts); 300 static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel2_enum, FIFO_CTRL2, CTRL2_SEL2_SHIFT, 301 axg_frddr_sel_texts); 302 static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel3_enum, FIFO_CTRL2, CTRL2_SEL3_SHIFT, 303 axg_frddr_sel_texts); 304 305 static const struct snd_kcontrol_new sm1_frddr_out1_demux = 306 SOC_DAPM_ENUM("Output Src 1", sm1_frddr_sel1_enum); 307 static const struct snd_kcontrol_new sm1_frddr_out2_demux = 308 SOC_DAPM_ENUM("Output Src 2", sm1_frddr_sel2_enum); 309 static const struct snd_kcontrol_new sm1_frddr_out3_demux = 310 SOC_DAPM_ENUM("Output Src 3", sm1_frddr_sel3_enum); 311 312 static const struct snd_soc_dapm_widget sm1_frddr_dapm_widgets[] = { 313 SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0), 314 SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0), 315 SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0), 316 SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0, 317 &sm1_frddr_out1_enable), 318 SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0, 319 &sm1_frddr_out2_enable), 320 SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0, 321 &sm1_frddr_out3_enable), 322 SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0, 323 &sm1_frddr_out1_demux), 324 SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0, 325 &sm1_frddr_out2_demux), 326 SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0, 327 &sm1_frddr_out3_demux), 328 SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0), 329 SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0), 330 SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0), 331 SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0), 332 SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0), 333 SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0), 334 SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0), 335 SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0), 336 }; 337 338 static const struct snd_soc_component_driver sm1_frddr_component_drv = { 339 .dapm_widgets = sm1_frddr_dapm_widgets, 340 .num_dapm_widgets = ARRAY_SIZE(sm1_frddr_dapm_widgets), 341 .dapm_routes = g12a_frddr_dapm_routes, 342 .num_dapm_routes = ARRAY_SIZE(g12a_frddr_dapm_routes), 343 .open = axg_fifo_pcm_open, 344 .close = axg_fifo_pcm_close, 345 .hw_params = g12a_fifo_pcm_hw_params, 346 .hw_free = axg_fifo_pcm_hw_free, 347 .pointer = axg_fifo_pcm_pointer, 348 .trigger = axg_fifo_pcm_trigger, 349 }; 350 351 static const struct axg_fifo_match_data sm1_frddr_match_data = { 352 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23), 353 .component_drv = &sm1_frddr_component_drv, 354 .dai_drv = &g12a_frddr_dai_drv 355 }; 356 357 static const struct of_device_id axg_frddr_of_match[] = { 358 { 359 .compatible = "amlogic,axg-frddr", 360 .data = &axg_frddr_match_data, 361 }, { 362 .compatible = "amlogic,g12a-frddr", 363 .data = &g12a_frddr_match_data, 364 }, { 365 .compatible = "amlogic,sm1-frddr", 366 .data = &sm1_frddr_match_data, 367 }, {} 368 }; 369 MODULE_DEVICE_TABLE(of, axg_frddr_of_match); 370 371 static struct platform_driver axg_frddr_pdrv = { 372 .probe = axg_fifo_probe, 373 .driver = { 374 .name = "axg-frddr", 375 .of_match_table = axg_frddr_of_match, 376 }, 377 }; 378 module_platform_driver(axg_frddr_pdrv); 379 380 MODULE_DESCRIPTION("Amlogic AXG/G12A playback fifo driver"); 381 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 382 MODULE_LICENSE("GPL v2"); 383