1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2020 BayLibre, SAS. 4 // Author: Jerome Brunet <jbrunet@baylibre.com> 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <sound/pcm_params.h> 9 #include <sound/soc.h> 10 #include <sound/soc-dai.h> 11 12 #include "aiu.h" 13 14 #define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0) 15 #define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5) 16 #define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9) 17 #define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11) 18 #define AIU_RST_SOFT_I2S_FAST BIT(0) 19 20 #define AIU_I2S_DAC_CFG_MSB_FIRST BIT(2) 21 #define AIU_I2S_MISC_HOLD_EN BIT(2) 22 #define AIU_CLK_CTRL_I2S_DIV_EN BIT(0) 23 #define AIU_CLK_CTRL_I2S_DIV GENMASK(3, 2) 24 #define AIU_CLK_CTRL_AOCLK_INVERT BIT(6) 25 #define AIU_CLK_CTRL_LRCLK_INVERT BIT(7) 26 #define AIU_CLK_CTRL_LRCLK_SKEW GENMASK(9, 8) 27 #define AIU_CLK_CTRL_MORE_HDMI_AMCLK BIT(6) 28 #define AIU_CLK_CTRL_MORE_I2S_DIV GENMASK(5, 0) 29 #define AIU_CODEC_DAC_LRCLK_CTRL_DIV GENMASK(11, 0) 30 31 static void aiu_encoder_i2s_divider_enable(struct snd_soc_component *component, 32 bool enable) 33 { 34 snd_soc_component_update_bits(component, AIU_CLK_CTRL, 35 AIU_CLK_CTRL_I2S_DIV_EN, 36 enable ? AIU_CLK_CTRL_I2S_DIV_EN : 0); 37 } 38 39 static void aiu_encoder_i2s_hold(struct snd_soc_component *component, 40 bool enable) 41 { 42 snd_soc_component_update_bits(component, AIU_I2S_MISC, 43 AIU_I2S_MISC_HOLD_EN, 44 enable ? AIU_I2S_MISC_HOLD_EN : 0); 45 } 46 47 static int aiu_encoder_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 48 struct snd_soc_dai *dai) 49 { 50 struct snd_soc_component *component = dai->component; 51 52 switch (cmd) { 53 case SNDRV_PCM_TRIGGER_START: 54 case SNDRV_PCM_TRIGGER_RESUME: 55 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 56 aiu_encoder_i2s_hold(component, false); 57 return 0; 58 59 case SNDRV_PCM_TRIGGER_STOP: 60 case SNDRV_PCM_TRIGGER_SUSPEND: 61 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 62 aiu_encoder_i2s_hold(component, true); 63 return 0; 64 65 default: 66 return -EINVAL; 67 } 68 } 69 70 static int aiu_encoder_i2s_setup_desc(struct snd_soc_component *component, 71 struct snd_pcm_hw_params *params) 72 { 73 /* Always operate in split (classic interleaved) mode */ 74 unsigned int desc = AIU_I2S_SOURCE_DESC_MODE_SPLIT; 75 unsigned int val; 76 77 /* Reset required to update the pipeline */ 78 snd_soc_component_write(component, AIU_RST_SOFT, AIU_RST_SOFT_I2S_FAST); 79 snd_soc_component_read(component, AIU_I2S_SYNC, &val); 80 81 switch (params_physical_width(params)) { 82 case 16: /* Nothing to do */ 83 break; 84 85 case 32: 86 desc |= (AIU_I2S_SOURCE_DESC_MODE_24BIT | 87 AIU_I2S_SOURCE_DESC_MODE_32BIT); 88 break; 89 90 default: 91 return -EINVAL; 92 } 93 94 switch (params_channels(params)) { 95 case 2: /* Nothing to do */ 96 break; 97 case 8: 98 desc |= AIU_I2S_SOURCE_DESC_MODE_8CH; 99 break; 100 default: 101 return -EINVAL; 102 } 103 104 snd_soc_component_update_bits(component, AIU_I2S_SOURCE_DESC, 105 AIU_I2S_SOURCE_DESC_MODE_8CH | 106 AIU_I2S_SOURCE_DESC_MODE_24BIT | 107 AIU_I2S_SOURCE_DESC_MODE_32BIT | 108 AIU_I2S_SOURCE_DESC_MODE_SPLIT, 109 desc); 110 111 return 0; 112 } 113 114 static int aiu_encoder_i2s_set_legacy_div(struct snd_soc_component *component, 115 struct snd_pcm_hw_params *params, 116 unsigned int bs) 117 { 118 switch (bs) { 119 case 1: 120 case 2: 121 case 4: 122 case 8: 123 /* These are the only valid legacy dividers */ 124 break; 125 126 default: 127 dev_err(component->dev, "Unsupported i2s divider: %u\n", bs); 128 return -EINVAL; 129 } 130 131 snd_soc_component_update_bits(component, AIU_CLK_CTRL, 132 AIU_CLK_CTRL_I2S_DIV, 133 FIELD_PREP(AIU_CLK_CTRL_I2S_DIV, 134 __ffs(bs))); 135 136 snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE, 137 AIU_CLK_CTRL_MORE_I2S_DIV, 138 FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV, 139 0)); 140 141 return 0; 142 } 143 144 static int aiu_encoder_i2s_set_more_div(struct snd_soc_component *component, 145 struct snd_pcm_hw_params *params, 146 unsigned int bs) 147 { 148 /* 149 * NOTE: this HW is odd. 150 * In most configuration, the i2s divider is 'mclk / blck'. 151 * However, in 16 bits - 8ch mode, this factor needs to be 152 * increased by 50% to get the correct output rate. 153 * No idea why ! 154 */ 155 if (params_width(params) == 16 && params_channels(params) == 8) { 156 if (bs % 2) { 157 dev_err(component->dev, 158 "Cannot increase i2s divider by 50%%\n"); 159 return -EINVAL; 160 } 161 bs += bs / 2; 162 } 163 164 /* Use CLK_MORE for mclk to bclk divider */ 165 snd_soc_component_update_bits(component, AIU_CLK_CTRL, 166 AIU_CLK_CTRL_I2S_DIV, 167 FIELD_PREP(AIU_CLK_CTRL_I2S_DIV, 0)); 168 169 snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE, 170 AIU_CLK_CTRL_MORE_I2S_DIV, 171 FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV, 172 bs - 1)); 173 174 return 0; 175 } 176 177 static int aiu_encoder_i2s_set_clocks(struct snd_soc_component *component, 178 struct snd_pcm_hw_params *params) 179 { 180 struct aiu *aiu = snd_soc_component_get_drvdata(component); 181 unsigned int srate = params_rate(params); 182 unsigned int fs, bs; 183 int ret; 184 185 /* Get the oversampling factor */ 186 fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate); 187 188 if (fs % 64) 189 return -EINVAL; 190 191 /* Send data MSB first */ 192 snd_soc_component_update_bits(component, AIU_I2S_DAC_CFG, 193 AIU_I2S_DAC_CFG_MSB_FIRST, 194 AIU_I2S_DAC_CFG_MSB_FIRST); 195 196 /* Set bclk to lrlck ratio */ 197 snd_soc_component_update_bits(component, AIU_CODEC_DAC_LRCLK_CTRL, 198 AIU_CODEC_DAC_LRCLK_CTRL_DIV, 199 FIELD_PREP(AIU_CODEC_DAC_LRCLK_CTRL_DIV, 200 64 - 1)); 201 202 bs = fs / 64; 203 204 if (aiu->platform->has_clk_ctrl_more_i2s_div) 205 ret = aiu_encoder_i2s_set_more_div(component, params, bs); 206 else 207 ret = aiu_encoder_i2s_set_legacy_div(component, params, bs); 208 209 if (ret) 210 return ret; 211 212 /* Make sure amclk is used for HDMI i2s as well */ 213 snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE, 214 AIU_CLK_CTRL_MORE_HDMI_AMCLK, 215 AIU_CLK_CTRL_MORE_HDMI_AMCLK); 216 217 return 0; 218 } 219 220 static int aiu_encoder_i2s_hw_params(struct snd_pcm_substream *substream, 221 struct snd_pcm_hw_params *params, 222 struct snd_soc_dai *dai) 223 { 224 struct snd_soc_component *component = dai->component; 225 int ret; 226 227 /* Disable the clock while changing the settings */ 228 aiu_encoder_i2s_divider_enable(component, false); 229 230 ret = aiu_encoder_i2s_setup_desc(component, params); 231 if (ret) { 232 dev_err(dai->dev, "setting i2s desc failed\n"); 233 return ret; 234 } 235 236 ret = aiu_encoder_i2s_set_clocks(component, params); 237 if (ret) { 238 dev_err(dai->dev, "setting i2s clocks failed\n"); 239 return ret; 240 } 241 242 aiu_encoder_i2s_divider_enable(component, true); 243 244 return 0; 245 } 246 247 static int aiu_encoder_i2s_hw_free(struct snd_pcm_substream *substream, 248 struct snd_soc_dai *dai) 249 { 250 struct snd_soc_component *component = dai->component; 251 252 aiu_encoder_i2s_divider_enable(component, false); 253 254 return 0; 255 } 256 257 static int aiu_encoder_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 258 { 259 struct snd_soc_component *component = dai->component; 260 unsigned int inv = fmt & SND_SOC_DAIFMT_INV_MASK; 261 unsigned int val = 0; 262 unsigned int skew; 263 264 /* Only CPU Master / Codec Slave supported ATM */ 265 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) 266 return -EINVAL; 267 268 if (inv == SND_SOC_DAIFMT_NB_IF || 269 inv == SND_SOC_DAIFMT_IB_IF) 270 val |= AIU_CLK_CTRL_LRCLK_INVERT; 271 272 if (inv == SND_SOC_DAIFMT_IB_NF || 273 inv == SND_SOC_DAIFMT_IB_IF) 274 val |= AIU_CLK_CTRL_AOCLK_INVERT; 275 276 /* Signal skew */ 277 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 278 case SND_SOC_DAIFMT_I2S: 279 /* Invert sample clock for i2s */ 280 val ^= AIU_CLK_CTRL_LRCLK_INVERT; 281 skew = 1; 282 break; 283 case SND_SOC_DAIFMT_LEFT_J: 284 skew = 0; 285 break; 286 default: 287 return -EINVAL; 288 } 289 290 val |= FIELD_PREP(AIU_CLK_CTRL_LRCLK_SKEW, skew); 291 snd_soc_component_update_bits(component, AIU_CLK_CTRL, 292 AIU_CLK_CTRL_LRCLK_INVERT | 293 AIU_CLK_CTRL_AOCLK_INVERT | 294 AIU_CLK_CTRL_LRCLK_SKEW, 295 val); 296 297 return 0; 298 } 299 300 static int aiu_encoder_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 301 unsigned int freq, int dir) 302 { 303 struct aiu *aiu = snd_soc_component_get_drvdata(dai->component); 304 int ret; 305 306 if (WARN_ON(clk_id != 0)) 307 return -EINVAL; 308 309 if (dir == SND_SOC_CLOCK_IN) 310 return 0; 311 312 ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq); 313 if (ret) 314 dev_err(dai->dev, "Failed to set sysclk to %uHz", freq); 315 316 return ret; 317 } 318 319 static const unsigned int hw_channels[] = {2, 8}; 320 static const struct snd_pcm_hw_constraint_list hw_channel_constraints = { 321 .list = hw_channels, 322 .count = ARRAY_SIZE(hw_channels), 323 .mask = 0, 324 }; 325 326 static int aiu_encoder_i2s_startup(struct snd_pcm_substream *substream, 327 struct snd_soc_dai *dai) 328 { 329 struct aiu *aiu = snd_soc_component_get_drvdata(dai->component); 330 int ret; 331 332 /* Make sure the encoder gets either 2 or 8 channels */ 333 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 334 SNDRV_PCM_HW_PARAM_CHANNELS, 335 &hw_channel_constraints); 336 if (ret) { 337 dev_err(dai->dev, "adding channels constraints failed\n"); 338 return ret; 339 } 340 341 ret = clk_bulk_prepare_enable(aiu->i2s.clk_num, aiu->i2s.clks); 342 if (ret) 343 dev_err(dai->dev, "failed to enable i2s clocks\n"); 344 345 return ret; 346 } 347 348 static void aiu_encoder_i2s_shutdown(struct snd_pcm_substream *substream, 349 struct snd_soc_dai *dai) 350 { 351 struct aiu *aiu = snd_soc_component_get_drvdata(dai->component); 352 353 clk_bulk_disable_unprepare(aiu->i2s.clk_num, aiu->i2s.clks); 354 } 355 356 const struct snd_soc_dai_ops aiu_encoder_i2s_dai_ops = { 357 .trigger = aiu_encoder_i2s_trigger, 358 .hw_params = aiu_encoder_i2s_hw_params, 359 .hw_free = aiu_encoder_i2s_hw_free, 360 .set_fmt = aiu_encoder_i2s_set_fmt, 361 .set_sysclk = aiu_encoder_i2s_set_sysclk, 362 .startup = aiu_encoder_i2s_startup, 363 .shutdown = aiu_encoder_i2s_shutdown, 364 }; 365 366