13de3eba5STrevor Wu // SPDX-License-Identifier: GPL-2.0 23de3eba5STrevor Wu /* 33de3eba5STrevor Wu * MediaTek ALSA SoC Audio DAI ADDA Control 43de3eba5STrevor Wu * 53de3eba5STrevor Wu * Copyright (c) 2021 MediaTek Inc. 63de3eba5STrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 73de3eba5STrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 83de3eba5STrevor Wu */ 93de3eba5STrevor Wu 103de3eba5STrevor Wu #include <linux/delay.h> 113de3eba5STrevor Wu #include <linux/regmap.h> 123de3eba5STrevor Wu #include "mt8195-afe-clk.h" 133de3eba5STrevor Wu #include "mt8195-afe-common.h" 143de3eba5STrevor Wu #include "mt8195-reg.h" 153de3eba5STrevor Wu 163de3eba5STrevor Wu #define ADDA_DL_GAIN_LOOPBACK 0x1800 173de3eba5STrevor Wu #define ADDA_HIRES_THRES 48000 183de3eba5STrevor Wu 193de3eba5STrevor Wu enum { 203de3eba5STrevor Wu SUPPLY_SEQ_CLOCK_SEL, 213de3eba5STrevor Wu SUPPLY_SEQ_CLOCK_ON, 223de3eba5STrevor Wu SUPPLY_SEQ_ADDA_DL_ON, 233de3eba5STrevor Wu SUPPLY_SEQ_ADDA_MTKAIF_CFG, 243de3eba5STrevor Wu SUPPLY_SEQ_ADDA_UL_ON, 253de3eba5STrevor Wu SUPPLY_SEQ_ADDA_AFE_ON, 263de3eba5STrevor Wu }; 273de3eba5STrevor Wu 283de3eba5STrevor Wu enum { 293de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_8K = 0, 303de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_11K = 1, 313de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_12K = 2, 323de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_16K = 3, 333de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_22K = 4, 343de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_24K = 5, 353de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_32K = 6, 363de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_44K = 7, 373de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_48K = 8, 383de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_96K = 9, 393de3eba5STrevor Wu MTK_AFE_ADDA_DL_RATE_192K = 10, 403de3eba5STrevor Wu }; 413de3eba5STrevor Wu 423de3eba5STrevor Wu enum { 433de3eba5STrevor Wu MTK_AFE_ADDA_UL_RATE_8K = 0, 443de3eba5STrevor Wu MTK_AFE_ADDA_UL_RATE_16K = 1, 453de3eba5STrevor Wu MTK_AFE_ADDA_UL_RATE_32K = 2, 463de3eba5STrevor Wu MTK_AFE_ADDA_UL_RATE_48K = 3, 473de3eba5STrevor Wu MTK_AFE_ADDA_UL_RATE_96K = 4, 483de3eba5STrevor Wu MTK_AFE_ADDA_UL_RATE_192K = 5, 493de3eba5STrevor Wu }; 503de3eba5STrevor Wu 513de3eba5STrevor Wu enum { 523de3eba5STrevor Wu DELAY_DATA_MISO1 = 0, 533de3eba5STrevor Wu DELAY_DATA_MISO0 = 1, 543de3eba5STrevor Wu DELAY_DATA_MISO2 = 1, 553de3eba5STrevor Wu }; 563de3eba5STrevor Wu 573de3eba5STrevor Wu enum { 583de3eba5STrevor Wu MTK_AFE_ADDA, 593de3eba5STrevor Wu MTK_AFE_ADDA6, 603de3eba5STrevor Wu }; 613de3eba5STrevor Wu 623de3eba5STrevor Wu struct mtk_dai_adda_priv { 633de3eba5STrevor Wu bool hires_required; 643de3eba5STrevor Wu }; 653de3eba5STrevor Wu 663de3eba5STrevor Wu static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe, 673de3eba5STrevor Wu unsigned int rate) 683de3eba5STrevor Wu { 693de3eba5STrevor Wu switch (rate) { 703de3eba5STrevor Wu case 8000: 713de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_8K; 723de3eba5STrevor Wu case 11025: 733de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_11K; 743de3eba5STrevor Wu case 12000: 753de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_12K; 763de3eba5STrevor Wu case 16000: 773de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_16K; 783de3eba5STrevor Wu case 22050: 793de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_22K; 803de3eba5STrevor Wu case 24000: 813de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_24K; 823de3eba5STrevor Wu case 32000: 833de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_32K; 843de3eba5STrevor Wu case 44100: 853de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_44K; 863de3eba5STrevor Wu case 48000: 873de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_48K; 883de3eba5STrevor Wu case 96000: 893de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_96K; 903de3eba5STrevor Wu case 192000: 913de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_192K; 923de3eba5STrevor Wu default: 933de3eba5STrevor Wu dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 943de3eba5STrevor Wu __func__, rate); 953de3eba5STrevor Wu return MTK_AFE_ADDA_DL_RATE_48K; 963de3eba5STrevor Wu } 973de3eba5STrevor Wu } 983de3eba5STrevor Wu 993de3eba5STrevor Wu static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe, 1003de3eba5STrevor Wu unsigned int rate) 1013de3eba5STrevor Wu { 1023de3eba5STrevor Wu switch (rate) { 1033de3eba5STrevor Wu case 8000: 1043de3eba5STrevor Wu return MTK_AFE_ADDA_UL_RATE_8K; 1053de3eba5STrevor Wu case 16000: 1063de3eba5STrevor Wu return MTK_AFE_ADDA_UL_RATE_16K; 1073de3eba5STrevor Wu case 32000: 1083de3eba5STrevor Wu return MTK_AFE_ADDA_UL_RATE_32K; 1093de3eba5STrevor Wu case 48000: 1103de3eba5STrevor Wu return MTK_AFE_ADDA_UL_RATE_48K; 1113de3eba5STrevor Wu case 96000: 1123de3eba5STrevor Wu return MTK_AFE_ADDA_UL_RATE_96K; 1133de3eba5STrevor Wu case 192000: 1143de3eba5STrevor Wu return MTK_AFE_ADDA_UL_RATE_192K; 1153de3eba5STrevor Wu default: 1163de3eba5STrevor Wu dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 1173de3eba5STrevor Wu __func__, rate); 1183de3eba5STrevor Wu return MTK_AFE_ADDA_UL_RATE_48K; 1193de3eba5STrevor Wu } 1203de3eba5STrevor Wu } 1213de3eba5STrevor Wu 1223de3eba5STrevor Wu static int mt8195_adda_mtkaif_init(struct mtk_base_afe *afe) 1233de3eba5STrevor Wu { 1243de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1253de3eba5STrevor Wu struct mtkaif_param *param = &afe_priv->mtkaif_params; 1263de3eba5STrevor Wu int delay_data; 1273de3eba5STrevor Wu int delay_cycle; 1283de3eba5STrevor Wu unsigned int mask = 0; 1293de3eba5STrevor Wu unsigned int val = 0; 1303de3eba5STrevor Wu 1313de3eba5STrevor Wu /* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */ 1323de3eba5STrevor Wu mask = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2); 1333de3eba5STrevor Wu val = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2); 1343de3eba5STrevor Wu 1353de3eba5STrevor Wu regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, mask, val); 1363de3eba5STrevor Wu regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, mask, val); 1373de3eba5STrevor Wu 1383de3eba5STrevor Wu mask = RG_RX_PROTOCOL2; 1393de3eba5STrevor Wu val = RG_RX_PROTOCOL2; 1403de3eba5STrevor Wu regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, mask, val); 1413de3eba5STrevor Wu 1423de3eba5STrevor Wu if (!param->mtkaif_calibration_ok) { 1433de3eba5STrevor Wu dev_info(afe->dev, "%s(), calibration fail\n", __func__); 1443de3eba5STrevor Wu return 0; 1453de3eba5STrevor Wu } 1463de3eba5STrevor Wu 1473de3eba5STrevor Wu /* set delay for ch1, ch2 */ 1483de3eba5STrevor Wu if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] >= 1493de3eba5STrevor Wu param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) { 1503de3eba5STrevor Wu delay_data = DELAY_DATA_MISO1; 1513de3eba5STrevor Wu delay_cycle = 1523de3eba5STrevor Wu param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] - 1533de3eba5STrevor Wu param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]; 1543de3eba5STrevor Wu } else { 1553de3eba5STrevor Wu delay_data = DELAY_DATA_MISO0; 1563de3eba5STrevor Wu delay_cycle = 1573de3eba5STrevor Wu param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] - 1583de3eba5STrevor Wu param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0]; 1593de3eba5STrevor Wu } 1603de3eba5STrevor Wu 1613de3eba5STrevor Wu val = 0; 1623de3eba5STrevor Wu mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK); 1633de3eba5STrevor Wu val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) & 1643de3eba5STrevor Wu MTKAIF_RXIF_DELAY_CYCLE_MASK; 1653de3eba5STrevor Wu val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT; 1663de3eba5STrevor Wu regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val); 1673de3eba5STrevor Wu 1683de3eba5STrevor Wu /* set delay between ch3 and ch2 */ 1693de3eba5STrevor Wu if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] >= 1703de3eba5STrevor Wu param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) { 1713de3eba5STrevor Wu delay_data = DELAY_DATA_MISO1; 1723de3eba5STrevor Wu delay_cycle = 1733de3eba5STrevor Wu param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] - 1743de3eba5STrevor Wu param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]; 1753de3eba5STrevor Wu } else { 1763de3eba5STrevor Wu delay_data = DELAY_DATA_MISO2; 1773de3eba5STrevor Wu delay_cycle = 1783de3eba5STrevor Wu param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] - 1793de3eba5STrevor Wu param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2]; 1803de3eba5STrevor Wu } 1813de3eba5STrevor Wu 1823de3eba5STrevor Wu val = 0; 1833de3eba5STrevor Wu mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK); 1843de3eba5STrevor Wu val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) & 1853de3eba5STrevor Wu MTKAIF_RXIF_DELAY_CYCLE_MASK; 1863de3eba5STrevor Wu val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT; 1873de3eba5STrevor Wu regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_RX_CFG2, mask, val); 1883de3eba5STrevor Wu 1893de3eba5STrevor Wu return 0; 1903de3eba5STrevor Wu } 1913de3eba5STrevor Wu 1923de3eba5STrevor Wu static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w, 1933de3eba5STrevor Wu struct snd_kcontrol *kcontrol, 1943de3eba5STrevor Wu int event) 1953de3eba5STrevor Wu { 1963de3eba5STrevor Wu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1973de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 1983de3eba5STrevor Wu 1993de3eba5STrevor Wu dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 2003de3eba5STrevor Wu __func__, w->name, event); 2013de3eba5STrevor Wu 2023de3eba5STrevor Wu switch (event) { 2033de3eba5STrevor Wu case SND_SOC_DAPM_PRE_PMU: 2043de3eba5STrevor Wu mt8195_adda_mtkaif_init(afe); 2053de3eba5STrevor Wu break; 2063de3eba5STrevor Wu default: 2073de3eba5STrevor Wu break; 2083de3eba5STrevor Wu } 2093de3eba5STrevor Wu 2103de3eba5STrevor Wu return 0; 2113de3eba5STrevor Wu } 2123de3eba5STrevor Wu 2133de3eba5STrevor Wu static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w, 2143de3eba5STrevor Wu struct snd_kcontrol *kcontrol, 2153de3eba5STrevor Wu int event) 2163de3eba5STrevor Wu { 2173de3eba5STrevor Wu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 2183de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 2193de3eba5STrevor Wu 2203de3eba5STrevor Wu dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 2213de3eba5STrevor Wu __func__, w->name, event); 2223de3eba5STrevor Wu 2233de3eba5STrevor Wu switch (event) { 2243de3eba5STrevor Wu case SND_SOC_DAPM_POST_PMD: 2253de3eba5STrevor Wu /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 2263de3eba5STrevor Wu usleep_range(125, 135); 2273de3eba5STrevor Wu break; 2283de3eba5STrevor Wu default: 2293de3eba5STrevor Wu break; 2303de3eba5STrevor Wu } 2313de3eba5STrevor Wu 2323de3eba5STrevor Wu return 0; 2333de3eba5STrevor Wu } 2343de3eba5STrevor Wu 2353de3eba5STrevor Wu static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, int adda, bool dmic) 2363de3eba5STrevor Wu { 2373de3eba5STrevor Wu unsigned int reg = 0; 2383de3eba5STrevor Wu unsigned int mask = 0; 2393de3eba5STrevor Wu unsigned int val = 0; 2403de3eba5STrevor Wu 2413de3eba5STrevor Wu switch (adda) { 2423de3eba5STrevor Wu case MTK_AFE_ADDA: 2433de3eba5STrevor Wu reg = AFE_ADDA_UL_SRC_CON0; 2443de3eba5STrevor Wu break; 2453de3eba5STrevor Wu case MTK_AFE_ADDA6: 2463de3eba5STrevor Wu reg = AFE_ADDA6_UL_SRC_CON0; 2473de3eba5STrevor Wu break; 2483de3eba5STrevor Wu default: 2493de3eba5STrevor Wu dev_info(afe->dev, "%s(), wrong parameter\n", __func__); 2503de3eba5STrevor Wu return; 2513de3eba5STrevor Wu } 2523de3eba5STrevor Wu 2533de3eba5STrevor Wu mask = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL | 2543de3eba5STrevor Wu UL_MODE_3P25M_CH2_CTL); 2553de3eba5STrevor Wu 2563de3eba5STrevor Wu /* turn on dmic, ch1, ch2 */ 2573de3eba5STrevor Wu if (dmic) 2583de3eba5STrevor Wu val = mask; 2593de3eba5STrevor Wu 2603de3eba5STrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 2613de3eba5STrevor Wu } 2623de3eba5STrevor Wu 2633de3eba5STrevor Wu static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 2643de3eba5STrevor Wu struct snd_kcontrol *kcontrol, 2653de3eba5STrevor Wu int event) 2663de3eba5STrevor Wu { 2673de3eba5STrevor Wu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 2683de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 2693de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2703de3eba5STrevor Wu struct mtkaif_param *param = &afe_priv->mtkaif_params; 2713de3eba5STrevor Wu 2723de3eba5STrevor Wu dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 2733de3eba5STrevor Wu __func__, w->name, event); 2743de3eba5STrevor Wu 2753de3eba5STrevor Wu switch (event) { 2763de3eba5STrevor Wu case SND_SOC_DAPM_PRE_PMU: 2773de3eba5STrevor Wu mtk_adda_ul_mictype(afe, MTK_AFE_ADDA, param->mtkaif_dmic_on); 2783de3eba5STrevor Wu break; 2793de3eba5STrevor Wu case SND_SOC_DAPM_POST_PMD: 2803de3eba5STrevor Wu /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 2813de3eba5STrevor Wu usleep_range(125, 135); 2823de3eba5STrevor Wu break; 2833de3eba5STrevor Wu default: 2843de3eba5STrevor Wu break; 2853de3eba5STrevor Wu } 2863de3eba5STrevor Wu 2873de3eba5STrevor Wu return 0; 2883de3eba5STrevor Wu } 2893de3eba5STrevor Wu 2903de3eba5STrevor Wu static int mtk_adda6_ul_event(struct snd_soc_dapm_widget *w, 2913de3eba5STrevor Wu struct snd_kcontrol *kcontrol, 2923de3eba5STrevor Wu int event) 2933de3eba5STrevor Wu { 2943de3eba5STrevor Wu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 2953de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 2963de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2973de3eba5STrevor Wu struct mtkaif_param *param = &afe_priv->mtkaif_params; 2983de3eba5STrevor Wu unsigned int val; 2993de3eba5STrevor Wu 3003de3eba5STrevor Wu dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 3013de3eba5STrevor Wu __func__, w->name, event); 3023de3eba5STrevor Wu 3033de3eba5STrevor Wu switch (event) { 3043de3eba5STrevor Wu case SND_SOC_DAPM_PRE_PMU: 3053de3eba5STrevor Wu mtk_adda_ul_mictype(afe, MTK_AFE_ADDA6, param->mtkaif_dmic_on); 3063de3eba5STrevor Wu 3073de3eba5STrevor Wu val = (param->mtkaif_adda6_only ? 3083de3eba5STrevor Wu ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE : 0); 3093de3eba5STrevor Wu 3103de3eba5STrevor Wu regmap_update_bits(afe->regmap, 3113de3eba5STrevor Wu AFE_ADDA_MTKAIF_SYNCWORD_CFG, 3123de3eba5STrevor Wu ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE, 3133de3eba5STrevor Wu val); 3143de3eba5STrevor Wu break; 3153de3eba5STrevor Wu case SND_SOC_DAPM_POST_PMD: 3163de3eba5STrevor Wu /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 3173de3eba5STrevor Wu usleep_range(125, 135); 3183de3eba5STrevor Wu break; 3193de3eba5STrevor Wu default: 3203de3eba5STrevor Wu break; 3213de3eba5STrevor Wu } 3223de3eba5STrevor Wu 3233de3eba5STrevor Wu return 0; 3243de3eba5STrevor Wu } 3253de3eba5STrevor Wu 3263de3eba5STrevor Wu static int mtk_audio_hires_event(struct snd_soc_dapm_widget *w, 3273de3eba5STrevor Wu struct snd_kcontrol *kcontrol, 3283de3eba5STrevor Wu int event) 3293de3eba5STrevor Wu { 3303de3eba5STrevor Wu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 3313de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 3323de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 3333de3eba5STrevor Wu struct clk *clk = afe_priv->clk[MT8195_CLK_TOP_AUDIO_H_SEL]; 3343de3eba5STrevor Wu struct clk *clk_parent; 3353de3eba5STrevor Wu 3363de3eba5STrevor Wu dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 3373de3eba5STrevor Wu __func__, w->name, event); 3383de3eba5STrevor Wu 3393de3eba5STrevor Wu switch (event) { 3403de3eba5STrevor Wu case SND_SOC_DAPM_PRE_PMU: 3413de3eba5STrevor Wu clk_parent = afe_priv->clk[MT8195_CLK_TOP_APLL1]; 3423de3eba5STrevor Wu break; 3433de3eba5STrevor Wu case SND_SOC_DAPM_POST_PMD: 3443de3eba5STrevor Wu clk_parent = afe_priv->clk[MT8195_CLK_XTAL_26M]; 3453de3eba5STrevor Wu break; 3463de3eba5STrevor Wu default: 3473de3eba5STrevor Wu return 0; 3483de3eba5STrevor Wu } 3493de3eba5STrevor Wu mt8195_afe_set_clk_parent(afe, clk, clk_parent); 3503de3eba5STrevor Wu 3513de3eba5STrevor Wu return 0; 3523de3eba5STrevor Wu } 3533de3eba5STrevor Wu 3543de3eba5STrevor Wu static struct mtk_dai_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe, 3553de3eba5STrevor Wu const char *name) 3563de3eba5STrevor Wu { 3573de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 3583de3eba5STrevor Wu int dai_id; 3593de3eba5STrevor Wu 3603de3eba5STrevor Wu if (strstr(name, "aud_adc_hires")) 3613de3eba5STrevor Wu dai_id = MT8195_AFE_IO_UL_SRC1; 3623de3eba5STrevor Wu else if (strstr(name, "aud_adda6_adc_hires")) 3633de3eba5STrevor Wu dai_id = MT8195_AFE_IO_UL_SRC2; 3643de3eba5STrevor Wu else if (strstr(name, "aud_dac_hires")) 3653de3eba5STrevor Wu dai_id = MT8195_AFE_IO_DL_SRC; 3663de3eba5STrevor Wu else 3673de3eba5STrevor Wu return NULL; 3683de3eba5STrevor Wu 3693de3eba5STrevor Wu return afe_priv->dai_priv[dai_id]; 3703de3eba5STrevor Wu } 3713de3eba5STrevor Wu 3723de3eba5STrevor Wu static int mtk_afe_adda_hires_connect(struct snd_soc_dapm_widget *source, 3733de3eba5STrevor Wu struct snd_soc_dapm_widget *sink) 3743de3eba5STrevor Wu { 3753de3eba5STrevor Wu struct snd_soc_dapm_widget *w = source; 3763de3eba5STrevor Wu struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 3773de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 3783de3eba5STrevor Wu struct mtk_dai_adda_priv *adda_priv; 3793de3eba5STrevor Wu 3803de3eba5STrevor Wu adda_priv = get_adda_priv_by_name(afe, w->name); 3813de3eba5STrevor Wu 3823de3eba5STrevor Wu if (!adda_priv) { 3833de3eba5STrevor Wu dev_info(afe->dev, "adda_priv == NULL"); 3843de3eba5STrevor Wu return 0; 3853de3eba5STrevor Wu } 3863de3eba5STrevor Wu 3873de3eba5STrevor Wu return (adda_priv->hires_required) ? 1 : 0; 3883de3eba5STrevor Wu } 3893de3eba5STrevor Wu 3903de3eba5STrevor Wu static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = { 3913de3eba5STrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0), 3923de3eba5STrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0), 3933de3eba5STrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0), 3943de3eba5STrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0), 3953de3eba5STrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0), 3963de3eba5STrevor Wu }; 3973de3eba5STrevor Wu 3983de3eba5STrevor Wu static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = { 3993de3eba5STrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0), 4003de3eba5STrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0), 4013de3eba5STrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0), 4023de3eba5STrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0), 4033de3eba5STrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0), 4043de3eba5STrevor Wu }; 4053de3eba5STrevor Wu 4063de3eba5STrevor Wu static const char * const adda_dlgain_mux_map[] = { 4073de3eba5STrevor Wu "Bypass", "Connect", 4083de3eba5STrevor Wu }; 4093de3eba5STrevor Wu 4103de3eba5STrevor Wu static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum, 4113de3eba5STrevor Wu SND_SOC_NOPM, 0, 4123de3eba5STrevor Wu adda_dlgain_mux_map); 4133de3eba5STrevor Wu 4143de3eba5STrevor Wu static const struct snd_kcontrol_new adda_dlgain_mux_control = 4153de3eba5STrevor Wu SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum); 4163de3eba5STrevor Wu 4173de3eba5STrevor Wu static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 4183de3eba5STrevor Wu SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0), 4193de3eba5STrevor Wu SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0), 4203de3eba5STrevor Wu SND_SOC_DAPM_MIXER("I170", SND_SOC_NOPM, 0, 0, NULL, 0), 4213de3eba5STrevor Wu SND_SOC_DAPM_MIXER("I171", SND_SOC_NOPM, 0, 0, NULL, 0), 4223de3eba5STrevor Wu 4233de3eba5STrevor Wu SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0, 4243de3eba5STrevor Wu mtk_dai_adda_o176_mix, 4253de3eba5STrevor Wu ARRAY_SIZE(mtk_dai_adda_o176_mix)), 4263de3eba5STrevor Wu SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0, 4273de3eba5STrevor Wu mtk_dai_adda_o177_mix, 4283de3eba5STrevor Wu ARRAY_SIZE(mtk_dai_adda_o177_mix)), 4293de3eba5STrevor Wu 4303de3eba5STrevor Wu SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 4313de3eba5STrevor Wu AFE_ADDA_UL_DL_CON0, 4323de3eba5STrevor Wu ADDA_AFE_ON_SHIFT, 0, 4333de3eba5STrevor Wu NULL, 4343de3eba5STrevor Wu 0), 4353de3eba5STrevor Wu 4363de3eba5STrevor Wu SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 4373de3eba5STrevor Wu AFE_ADDA_DL_SRC2_CON0, 4383de3eba5STrevor Wu DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0, 4393de3eba5STrevor Wu mtk_adda_dl_event, 4403de3eba5STrevor Wu SND_SOC_DAPM_POST_PMD), 4413de3eba5STrevor Wu 4423de3eba5STrevor Wu SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 4433de3eba5STrevor Wu AFE_ADDA_UL_SRC_CON0, 4443de3eba5STrevor Wu UL_SRC_ON_TMP_CTL_SHIFT, 0, 4453de3eba5STrevor Wu mtk_adda_ul_event, 4463de3eba5STrevor Wu SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4473de3eba5STrevor Wu 4483de3eba5STrevor Wu SND_SOC_DAPM_SUPPLY_S("ADDA6 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 4493de3eba5STrevor Wu AFE_ADDA6_UL_SRC_CON0, 4503de3eba5STrevor Wu UL_SRC_ON_TMP_CTL_SHIFT, 0, 4513de3eba5STrevor Wu mtk_adda6_ul_event, 4523de3eba5STrevor Wu SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4533de3eba5STrevor Wu 4543de3eba5STrevor Wu SND_SOC_DAPM_SUPPLY_S("AUDIO_HIRES", SUPPLY_SEQ_CLOCK_SEL, 4553de3eba5STrevor Wu SND_SOC_NOPM, 4563de3eba5STrevor Wu 0, 0, 4573de3eba5STrevor Wu mtk_audio_hires_event, 4583de3eba5STrevor Wu SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4593de3eba5STrevor Wu 4603de3eba5STrevor Wu SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 4613de3eba5STrevor Wu SND_SOC_NOPM, 4623de3eba5STrevor Wu 0, 0, 4633de3eba5STrevor Wu mtk_adda_mtkaif_cfg_event, 4643de3eba5STrevor Wu SND_SOC_DAPM_PRE_PMU), 4653de3eba5STrevor Wu 4663de3eba5STrevor Wu SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0, 4673de3eba5STrevor Wu &adda_dlgain_mux_control), 4683de3eba5STrevor Wu 4693de3eba5STrevor Wu SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0, 4703de3eba5STrevor Wu DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0), 4713de3eba5STrevor Wu 4723de3eba5STrevor Wu SND_SOC_DAPM_INPUT("ADDA_INPUT"), 4733de3eba5STrevor Wu SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"), 4743de3eba5STrevor Wu 4753de3eba5STrevor Wu SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"), 4763de3eba5STrevor Wu SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"), 4773de3eba5STrevor Wu SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc"), 4783de3eba5STrevor Wu SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"), 4793de3eba5STrevor Wu SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"), 4803de3eba5STrevor Wu SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_hires"), 4813de3eba5STrevor Wu }; 4823de3eba5STrevor Wu 4833de3eba5STrevor Wu static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 4843de3eba5STrevor Wu {"ADDA Capture", NULL, "ADDA Enable"}, 4853de3eba5STrevor Wu {"ADDA Capture", NULL, "ADDA Capture Enable"}, 4863de3eba5STrevor Wu {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 4873de3eba5STrevor Wu {"ADDA Capture", NULL, "aud_adc"}, 4883de3eba5STrevor Wu {"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adda_hires_connect}, 4893de3eba5STrevor Wu {"aud_adc_hires", NULL, "AUDIO_HIRES"}, 4903de3eba5STrevor Wu 4913de3eba5STrevor Wu {"ADDA6 Capture", NULL, "ADDA Enable"}, 4923de3eba5STrevor Wu {"ADDA6 Capture", NULL, "ADDA6 Capture Enable"}, 4933de3eba5STrevor Wu {"ADDA6 Capture", NULL, "ADDA_MTKAIF_CFG"}, 4943de3eba5STrevor Wu {"ADDA6 Capture", NULL, "aud_adda6_adc"}, 4953de3eba5STrevor Wu {"ADDA6 Capture", NULL, "aud_adda6_adc_hires", 4963de3eba5STrevor Wu mtk_afe_adda_hires_connect}, 4973de3eba5STrevor Wu {"aud_adda6_adc_hires", NULL, "AUDIO_HIRES"}, 4983de3eba5STrevor Wu 4993de3eba5STrevor Wu {"I168", NULL, "ADDA Capture"}, 5003de3eba5STrevor Wu {"I169", NULL, "ADDA Capture"}, 5013de3eba5STrevor Wu {"I170", NULL, "ADDA6 Capture"}, 5023de3eba5STrevor Wu {"I171", NULL, "ADDA6 Capture"}, 5033de3eba5STrevor Wu 5043de3eba5STrevor Wu {"ADDA Playback", NULL, "ADDA Enable"}, 5053de3eba5STrevor Wu {"ADDA Playback", NULL, "ADDA Playback Enable"}, 5063de3eba5STrevor Wu {"ADDA Playback", NULL, "aud_dac"}, 5073de3eba5STrevor Wu {"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_adda_hires_connect}, 5083de3eba5STrevor Wu {"aud_dac_hires", NULL, "AUDIO_HIRES"}, 5093de3eba5STrevor Wu 5103de3eba5STrevor Wu {"DL_GAIN", NULL, "O176"}, 5113de3eba5STrevor Wu {"DL_GAIN", NULL, "O177"}, 5123de3eba5STrevor Wu 5133de3eba5STrevor Wu {"DL_GAIN_MUX", "Bypass", "O176"}, 5143de3eba5STrevor Wu {"DL_GAIN_MUX", "Bypass", "O177"}, 5153de3eba5STrevor Wu {"DL_GAIN_MUX", "Connect", "DL_GAIN"}, 5163de3eba5STrevor Wu 5173de3eba5STrevor Wu {"ADDA Playback", NULL, "DL_GAIN_MUX"}, 5183de3eba5STrevor Wu 5193de3eba5STrevor Wu {"O176", "I000 Switch", "I000"}, 5203de3eba5STrevor Wu {"O177", "I001 Switch", "I001"}, 5213de3eba5STrevor Wu 5223de3eba5STrevor Wu {"O176", "I002 Switch", "I002"}, 5233de3eba5STrevor Wu {"O177", "I003 Switch", "I003"}, 5243de3eba5STrevor Wu 5253de3eba5STrevor Wu {"O176", "I020 Switch", "I020"}, 5263de3eba5STrevor Wu {"O177", "I021 Switch", "I021"}, 5273de3eba5STrevor Wu 5283de3eba5STrevor Wu {"O176", "I022 Switch", "I022"}, 5293de3eba5STrevor Wu {"O177", "I023 Switch", "I023"}, 5303de3eba5STrevor Wu 5313de3eba5STrevor Wu {"O176", "I070 Switch", "I070"}, 5323de3eba5STrevor Wu {"O177", "I071 Switch", "I071"}, 5333de3eba5STrevor Wu 5343de3eba5STrevor Wu {"ADDA Capture", NULL, "ADDA_INPUT"}, 5353de3eba5STrevor Wu {"ADDA6 Capture", NULL, "ADDA_INPUT"}, 5363de3eba5STrevor Wu {"ADDA_OUTPUT", NULL, "ADDA Playback"}, 5373de3eba5STrevor Wu }; 5383de3eba5STrevor Wu 5393de3eba5STrevor Wu static int mt8195_adda_dl_gain_put(struct snd_kcontrol *kcontrol, 5403de3eba5STrevor Wu struct snd_ctl_elem_value *ucontrol) 5413de3eba5STrevor Wu { 5423de3eba5STrevor Wu struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 5433de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 5443de3eba5STrevor Wu unsigned int reg = AFE_ADDA_DL_SRC2_CON1; 5453de3eba5STrevor Wu unsigned int mask = DL_2_GAIN_CTL_PRE_MASK; 5463de3eba5STrevor Wu unsigned int value = (unsigned int)(ucontrol->value.integer.value[0]); 5473de3eba5STrevor Wu 5483de3eba5STrevor Wu regmap_update_bits(afe->regmap, reg, mask, DL_2_GAIN_CTL_PRE(value)); 5493de3eba5STrevor Wu return 0; 5503de3eba5STrevor Wu } 5513de3eba5STrevor Wu 5523de3eba5STrevor Wu static int mt8195_adda_dl_gain_get(struct snd_kcontrol *kcontrol, 5533de3eba5STrevor Wu struct snd_ctl_elem_value *ucontrol) 5543de3eba5STrevor Wu { 5553de3eba5STrevor Wu struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 5563de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 5573de3eba5STrevor Wu unsigned int reg = AFE_ADDA_DL_SRC2_CON1; 5583de3eba5STrevor Wu unsigned int mask = DL_2_GAIN_CTL_PRE_MASK; 5593de3eba5STrevor Wu unsigned int value = 0; 5603de3eba5STrevor Wu 5613de3eba5STrevor Wu regmap_read(afe->regmap, reg, &value); 5623de3eba5STrevor Wu 5633de3eba5STrevor Wu ucontrol->value.integer.value[0] = ((value & mask) >> 5643de3eba5STrevor Wu DL_2_GAIN_CTL_PRE_SHIFT); 5653de3eba5STrevor Wu return 0; 5663de3eba5STrevor Wu } 5673de3eba5STrevor Wu 5683de3eba5STrevor Wu static int mt8195_adda6_only_get(struct snd_kcontrol *kcontrol, 5693de3eba5STrevor Wu struct snd_ctl_elem_value *ucontrol) 5703de3eba5STrevor Wu { 5713de3eba5STrevor Wu struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 5723de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 5733de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 5743de3eba5STrevor Wu struct mtkaif_param *param = &afe_priv->mtkaif_params; 5753de3eba5STrevor Wu 5763de3eba5STrevor Wu ucontrol->value.integer.value[0] = param->mtkaif_adda6_only; 5773de3eba5STrevor Wu return 0; 5783de3eba5STrevor Wu } 5793de3eba5STrevor Wu 5803de3eba5STrevor Wu static int mt8195_adda6_only_set(struct snd_kcontrol *kcontrol, 5813de3eba5STrevor Wu struct snd_ctl_elem_value *ucontrol) 5823de3eba5STrevor Wu { 5833de3eba5STrevor Wu struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 5843de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 5853de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 5863de3eba5STrevor Wu struct mtkaif_param *param = &afe_priv->mtkaif_params; 5873de3eba5STrevor Wu int mtkaif_adda6_only; 5883de3eba5STrevor Wu 5893de3eba5STrevor Wu mtkaif_adda6_only = ucontrol->value.integer.value[0]; 5903de3eba5STrevor Wu 5913de3eba5STrevor Wu dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_adda6_only %d\n", 5923de3eba5STrevor Wu __func__, kcontrol->id.name, mtkaif_adda6_only); 5933de3eba5STrevor Wu 5943de3eba5STrevor Wu param->mtkaif_adda6_only = mtkaif_adda6_only; 5953de3eba5STrevor Wu 5963de3eba5STrevor Wu return 0; 5973de3eba5STrevor Wu } 5983de3eba5STrevor Wu 5993de3eba5STrevor Wu static int mt8195_adda_dmic_get(struct snd_kcontrol *kcontrol, 6003de3eba5STrevor Wu struct snd_ctl_elem_value *ucontrol) 6013de3eba5STrevor Wu { 6023de3eba5STrevor Wu struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 6033de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 6043de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 6053de3eba5STrevor Wu struct mtkaif_param *param = &afe_priv->mtkaif_params; 6063de3eba5STrevor Wu 6073de3eba5STrevor Wu ucontrol->value.integer.value[0] = param->mtkaif_dmic_on; 6083de3eba5STrevor Wu return 0; 6093de3eba5STrevor Wu } 6103de3eba5STrevor Wu 6113de3eba5STrevor Wu static int mt8195_adda_dmic_set(struct snd_kcontrol *kcontrol, 6123de3eba5STrevor Wu struct snd_ctl_elem_value *ucontrol) 6133de3eba5STrevor Wu { 6143de3eba5STrevor Wu struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 6153de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 6163de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 6173de3eba5STrevor Wu struct mtkaif_param *param = &afe_priv->mtkaif_params; 6183de3eba5STrevor Wu int dmic_on; 6193de3eba5STrevor Wu 6203de3eba5STrevor Wu dmic_on = ucontrol->value.integer.value[0]; 6213de3eba5STrevor Wu 6223de3eba5STrevor Wu dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n", 6233de3eba5STrevor Wu __func__, kcontrol->id.name, dmic_on); 6243de3eba5STrevor Wu 6253de3eba5STrevor Wu param->mtkaif_dmic_on = dmic_on; 6263de3eba5STrevor Wu return 0; 6273de3eba5STrevor Wu } 6283de3eba5STrevor Wu 6293de3eba5STrevor Wu static const struct snd_kcontrol_new mtk_dai_adda_controls[] = { 6303de3eba5STrevor Wu SOC_SINGLE_EXT("ADDA_DL_Gain", SND_SOC_NOPM, 0, 65535, 0, 6313de3eba5STrevor Wu mt8195_adda_dl_gain_get, mt8195_adda_dl_gain_put), 6323de3eba5STrevor Wu SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC", 0, 6333de3eba5STrevor Wu mt8195_adda_dmic_get, mt8195_adda_dmic_set), 6343de3eba5STrevor Wu SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY", 0, 6353de3eba5STrevor Wu mt8195_adda6_only_get, 6363de3eba5STrevor Wu mt8195_adda6_only_set), 6373de3eba5STrevor Wu }; 6383de3eba5STrevor Wu 6393de3eba5STrevor Wu static int mtk_dai_da_configure(struct mtk_base_afe *afe, 6403de3eba5STrevor Wu unsigned int rate, int id) 6413de3eba5STrevor Wu { 6423de3eba5STrevor Wu unsigned int val = 0; 6433de3eba5STrevor Wu unsigned int mask = 0; 6443de3eba5STrevor Wu 6453de3eba5STrevor Wu /* set sampling rate */ 6463de3eba5STrevor Wu mask |= DL_2_INPUT_MODE_CTL_MASK; 6473de3eba5STrevor Wu val |= DL_2_INPUT_MODE_CTL(afe_adda_dl_rate_transform(afe, rate)); 6483de3eba5STrevor Wu 6493de3eba5STrevor Wu /* turn off saturation */ 6503de3eba5STrevor Wu mask |= DL_2_CH1_SATURATION_EN_CTL; 6513de3eba5STrevor Wu mask |= DL_2_CH2_SATURATION_EN_CTL; 6523de3eba5STrevor Wu 6533de3eba5STrevor Wu /* turn off mute function */ 6543de3eba5STrevor Wu mask |= DL_2_MUTE_CH1_OFF_CTL_PRE; 6553de3eba5STrevor Wu mask |= DL_2_MUTE_CH2_OFF_CTL_PRE; 6563de3eba5STrevor Wu val |= DL_2_MUTE_CH1_OFF_CTL_PRE; 6573de3eba5STrevor Wu val |= DL_2_MUTE_CH2_OFF_CTL_PRE; 6583de3eba5STrevor Wu 6593de3eba5STrevor Wu /* set voice input data if input sample rate is 8k or 16k */ 6603de3eba5STrevor Wu mask |= DL_2_VOICE_MODE_CTL_PRE; 6613de3eba5STrevor Wu if (rate == 8000 || rate == 16000) 6623de3eba5STrevor Wu val |= DL_2_VOICE_MODE_CTL_PRE; 6633de3eba5STrevor Wu 6643de3eba5STrevor Wu regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val); 6653de3eba5STrevor Wu 6663de3eba5STrevor Wu mask = 0; 6673de3eba5STrevor Wu val = 0; 6683de3eba5STrevor Wu 6693de3eba5STrevor Wu /* new 2nd sdm */ 6703de3eba5STrevor Wu mask |= DL_USE_NEW_2ND_SDM; 6713de3eba5STrevor Wu val |= DL_USE_NEW_2ND_SDM; 6723de3eba5STrevor Wu regmap_update_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, mask, val); 6733de3eba5STrevor Wu 6743de3eba5STrevor Wu return 0; 6753de3eba5STrevor Wu } 6763de3eba5STrevor Wu 6773de3eba5STrevor Wu static int mtk_dai_ad_configure(struct mtk_base_afe *afe, 6783de3eba5STrevor Wu unsigned int rate, int id) 6793de3eba5STrevor Wu { 6803de3eba5STrevor Wu unsigned int val = 0; 6813de3eba5STrevor Wu unsigned int mask = 0; 6823de3eba5STrevor Wu 6833de3eba5STrevor Wu mask |= UL_VOICE_MODE_CTL_MASK; 6843de3eba5STrevor Wu val |= UL_VOICE_MODE_CTL(afe_adda_ul_rate_transform(afe, rate)); 6853de3eba5STrevor Wu 6863de3eba5STrevor Wu switch (id) { 6873de3eba5STrevor Wu case MT8195_AFE_IO_UL_SRC1: 6883de3eba5STrevor Wu regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 6893de3eba5STrevor Wu mask, val); 6903de3eba5STrevor Wu break; 6913de3eba5STrevor Wu case MT8195_AFE_IO_UL_SRC2: 6923de3eba5STrevor Wu regmap_update_bits(afe->regmap, AFE_ADDA6_UL_SRC_CON0, 6933de3eba5STrevor Wu mask, val); 6943de3eba5STrevor Wu break; 6953de3eba5STrevor Wu default: 6963de3eba5STrevor Wu break; 6973de3eba5STrevor Wu } 6983de3eba5STrevor Wu return 0; 6993de3eba5STrevor Wu } 7003de3eba5STrevor Wu 7013de3eba5STrevor Wu static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 7023de3eba5STrevor Wu struct snd_pcm_hw_params *params, 7033de3eba5STrevor Wu struct snd_soc_dai *dai) 7043de3eba5STrevor Wu { 7053de3eba5STrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 7063de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 7073de3eba5STrevor Wu struct mtk_dai_adda_priv *adda_priv = afe_priv->dai_priv[dai->id]; 7083de3eba5STrevor Wu unsigned int rate = params_rate(params); 7093de3eba5STrevor Wu int id = dai->id; 7103de3eba5STrevor Wu int ret = 0; 7113de3eba5STrevor Wu 7123de3eba5STrevor Wu dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n", 7133de3eba5STrevor Wu __func__, id, substream->stream, rate); 7143de3eba5STrevor Wu 7153de3eba5STrevor Wu if (rate > ADDA_HIRES_THRES) 7163de3eba5STrevor Wu adda_priv->hires_required = 1; 7173de3eba5STrevor Wu else 7183de3eba5STrevor Wu adda_priv->hires_required = 0; 7193de3eba5STrevor Wu 7203de3eba5STrevor Wu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 7213de3eba5STrevor Wu ret = mtk_dai_da_configure(afe, rate, id); 7223de3eba5STrevor Wu else 7233de3eba5STrevor Wu ret = mtk_dai_ad_configure(afe, rate, id); 7243de3eba5STrevor Wu 7253de3eba5STrevor Wu return ret; 7263de3eba5STrevor Wu } 7273de3eba5STrevor Wu 7283de3eba5STrevor Wu static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 7293de3eba5STrevor Wu .hw_params = mtk_dai_adda_hw_params, 7303de3eba5STrevor Wu }; 7313de3eba5STrevor Wu 7323de3eba5STrevor Wu /* dai driver */ 7333de3eba5STrevor Wu #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 7343de3eba5STrevor Wu SNDRV_PCM_RATE_96000 |\ 7353de3eba5STrevor Wu SNDRV_PCM_RATE_192000) 7363de3eba5STrevor Wu 7373de3eba5STrevor Wu #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 7383de3eba5STrevor Wu SNDRV_PCM_RATE_16000 |\ 7393de3eba5STrevor Wu SNDRV_PCM_RATE_32000 |\ 7403de3eba5STrevor Wu SNDRV_PCM_RATE_48000 |\ 7413de3eba5STrevor Wu SNDRV_PCM_RATE_96000 |\ 7423de3eba5STrevor Wu SNDRV_PCM_RATE_192000) 7433de3eba5STrevor Wu 7443de3eba5STrevor Wu #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 7453de3eba5STrevor Wu SNDRV_PCM_FMTBIT_S24_LE |\ 7463de3eba5STrevor Wu SNDRV_PCM_FMTBIT_S32_LE) 7473de3eba5STrevor Wu 7483de3eba5STrevor Wu static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 7493de3eba5STrevor Wu { 7503de3eba5STrevor Wu .name = "DL_SRC", 7513de3eba5STrevor Wu .id = MT8195_AFE_IO_DL_SRC, 7523de3eba5STrevor Wu .playback = { 7533de3eba5STrevor Wu .stream_name = "ADDA Playback", 7543de3eba5STrevor Wu .channels_min = 1, 7553de3eba5STrevor Wu .channels_max = 2, 7563de3eba5STrevor Wu .rates = MTK_ADDA_PLAYBACK_RATES, 7573de3eba5STrevor Wu .formats = MTK_ADDA_FORMATS, 7583de3eba5STrevor Wu }, 7593de3eba5STrevor Wu .ops = &mtk_dai_adda_ops, 7603de3eba5STrevor Wu }, 7613de3eba5STrevor Wu { 7623de3eba5STrevor Wu .name = "UL_SRC1", 7633de3eba5STrevor Wu .id = MT8195_AFE_IO_UL_SRC1, 7643de3eba5STrevor Wu .capture = { 7653de3eba5STrevor Wu .stream_name = "ADDA Capture", 7663de3eba5STrevor Wu .channels_min = 1, 7673de3eba5STrevor Wu .channels_max = 2, 7683de3eba5STrevor Wu .rates = MTK_ADDA_CAPTURE_RATES, 7693de3eba5STrevor Wu .formats = MTK_ADDA_FORMATS, 7703de3eba5STrevor Wu }, 7713de3eba5STrevor Wu .ops = &mtk_dai_adda_ops, 7723de3eba5STrevor Wu }, 7733de3eba5STrevor Wu { 7743de3eba5STrevor Wu .name = "UL_SRC2", 7753de3eba5STrevor Wu .id = MT8195_AFE_IO_UL_SRC2, 7763de3eba5STrevor Wu .capture = { 7773de3eba5STrevor Wu .stream_name = "ADDA6 Capture", 7783de3eba5STrevor Wu .channels_min = 1, 7793de3eba5STrevor Wu .channels_max = 2, 7803de3eba5STrevor Wu .rates = MTK_ADDA_CAPTURE_RATES, 7813de3eba5STrevor Wu .formats = MTK_ADDA_FORMATS, 7823de3eba5STrevor Wu }, 7833de3eba5STrevor Wu .ops = &mtk_dai_adda_ops, 7843de3eba5STrevor Wu }, 7853de3eba5STrevor Wu }; 7863de3eba5STrevor Wu 7873de3eba5STrevor Wu static int init_adda_priv_data(struct mtk_base_afe *afe) 7883de3eba5STrevor Wu { 7893de3eba5STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 7903de3eba5STrevor Wu struct mtk_dai_adda_priv *adda_priv; 791*ce3f9357SColin Ian King static const int adda_dai_list[] = { 792*ce3f9357SColin Ian King MT8195_AFE_IO_DL_SRC, 7933de3eba5STrevor Wu MT8195_AFE_IO_UL_SRC1, 794*ce3f9357SColin Ian King MT8195_AFE_IO_UL_SRC2 795*ce3f9357SColin Ian King }; 7963de3eba5STrevor Wu int i; 7973de3eba5STrevor Wu 7983de3eba5STrevor Wu for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) { 7993de3eba5STrevor Wu adda_priv = devm_kzalloc(afe->dev, 8003de3eba5STrevor Wu sizeof(struct mtk_dai_adda_priv), 8013de3eba5STrevor Wu GFP_KERNEL); 8023de3eba5STrevor Wu if (!adda_priv) 8033de3eba5STrevor Wu return -ENOMEM; 8043de3eba5STrevor Wu 8053de3eba5STrevor Wu afe_priv->dai_priv[adda_dai_list[i]] = adda_priv; 8063de3eba5STrevor Wu } 8073de3eba5STrevor Wu 8083de3eba5STrevor Wu return 0; 8093de3eba5STrevor Wu } 8103de3eba5STrevor Wu 8113de3eba5STrevor Wu int mt8195_dai_adda_register(struct mtk_base_afe *afe) 8123de3eba5STrevor Wu { 8133de3eba5STrevor Wu struct mtk_base_afe_dai *dai; 8143de3eba5STrevor Wu 8153de3eba5STrevor Wu dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 8163de3eba5STrevor Wu if (!dai) 8173de3eba5STrevor Wu return -ENOMEM; 8183de3eba5STrevor Wu 8193de3eba5STrevor Wu list_add(&dai->list, &afe->sub_dais); 8203de3eba5STrevor Wu 8213de3eba5STrevor Wu dai->dai_drivers = mtk_dai_adda_driver; 8223de3eba5STrevor Wu dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 8233de3eba5STrevor Wu 8243de3eba5STrevor Wu dai->dapm_widgets = mtk_dai_adda_widgets; 8253de3eba5STrevor Wu dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 8263de3eba5STrevor Wu dai->dapm_routes = mtk_dai_adda_routes; 8273de3eba5STrevor Wu dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 8283de3eba5STrevor Wu dai->controls = mtk_dai_adda_controls; 8293de3eba5STrevor Wu dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls); 8303de3eba5STrevor Wu 8313de3eba5STrevor Wu return init_adda_priv_data(afe); 8323de3eba5STrevor Wu } 833