1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mediatek ALSA SoC AFE platform driver for 8195 4 * 5 * Copyright (c) 2021 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_platform.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/pm_runtime.h> 19 #include "mt8195-afe-common.h" 20 #include "mt8195-afe-clk.h" 21 #include "mt8195-reg.h" 22 #include "../common/mtk-afe-platform-driver.h" 23 #include "../common/mtk-afe-fe-dai.h" 24 25 #define MT8195_MEMIF_BUFFER_BYTES_ALIGN (0x40) 26 #define MT8195_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff) 27 28 struct mtk_dai_memif_priv { 29 unsigned int asys_timing_sel; 30 }; 31 32 static const struct snd_pcm_hardware mt8195_afe_hardware = { 33 .info = SNDRV_PCM_INFO_MMAP | 34 SNDRV_PCM_INFO_INTERLEAVED | 35 SNDRV_PCM_INFO_MMAP_VALID, 36 .formats = SNDRV_PCM_FMTBIT_S16_LE | 37 SNDRV_PCM_FMTBIT_S24_LE | 38 SNDRV_PCM_FMTBIT_S32_LE, 39 .period_bytes_min = 64, 40 .period_bytes_max = 256 * 1024, 41 .periods_min = 2, 42 .periods_max = 256, 43 .buffer_bytes_max = 256 * 2 * 1024, 44 }; 45 46 struct mt8195_afe_rate { 47 unsigned int rate; 48 unsigned int reg_value; 49 }; 50 51 static const struct mt8195_afe_rate mt8195_afe_rates[] = { 52 { .rate = 8000, .reg_value = 0, }, 53 { .rate = 12000, .reg_value = 1, }, 54 { .rate = 16000, .reg_value = 2, }, 55 { .rate = 24000, .reg_value = 3, }, 56 { .rate = 32000, .reg_value = 4, }, 57 { .rate = 48000, .reg_value = 5, }, 58 { .rate = 96000, .reg_value = 6, }, 59 { .rate = 192000, .reg_value = 7, }, 60 { .rate = 384000, .reg_value = 8, }, 61 { .rate = 7350, .reg_value = 16, }, 62 { .rate = 11025, .reg_value = 17, }, 63 { .rate = 14700, .reg_value = 18, }, 64 { .rate = 22050, .reg_value = 19, }, 65 { .rate = 29400, .reg_value = 20, }, 66 { .rate = 44100, .reg_value = 21, }, 67 { .rate = 88200, .reg_value = 22, }, 68 { .rate = 176400, .reg_value = 23, }, 69 { .rate = 352800, .reg_value = 24, }, 70 }; 71 72 int mt8195_afe_fs_timing(unsigned int rate) 73 { 74 int i; 75 76 for (i = 0; i < ARRAY_SIZE(mt8195_afe_rates); i++) 77 if (mt8195_afe_rates[i].rate == rate) 78 return mt8195_afe_rates[i].reg_value; 79 80 return -EINVAL; 81 } 82 83 static int mt8195_memif_fs(struct snd_pcm_substream *substream, 84 unsigned int rate) 85 { 86 struct snd_soc_pcm_runtime *rtd = substream->private_data; 87 struct snd_soc_component *component = 88 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 89 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 90 int id = asoc_rtd_to_cpu(rtd, 0)->id; 91 struct mtk_base_afe_memif *memif = &afe->memif[id]; 92 int fs = mt8195_afe_fs_timing(rate); 93 94 switch (memif->data->id) { 95 case MT8195_AFE_MEMIF_DL10: 96 fs = MT8195_ETDM_OUT3_1X_EN; 97 break; 98 case MT8195_AFE_MEMIF_UL8: 99 fs = MT8195_ETDM_IN1_NX_EN; 100 break; 101 case MT8195_AFE_MEMIF_UL3: 102 fs = MT8195_ETDM_IN2_NX_EN; 103 break; 104 default: 105 break; 106 } 107 108 return fs; 109 } 110 111 static int mt8195_irq_fs(struct snd_pcm_substream *substream, 112 unsigned int rate) 113 { 114 int fs = mt8195_memif_fs(substream, rate); 115 116 switch (fs) { 117 case MT8195_ETDM_IN1_NX_EN: 118 fs = MT8195_ETDM_IN1_1X_EN; 119 break; 120 case MT8195_ETDM_IN2_NX_EN: 121 fs = MT8195_ETDM_IN2_1X_EN; 122 break; 123 default: 124 break; 125 } 126 127 return fs; 128 } 129 130 enum { 131 MT8195_AFE_CM0, 132 MT8195_AFE_CM1, 133 MT8195_AFE_CM2, 134 MT8195_AFE_CM_NUM, 135 }; 136 137 struct mt8195_afe_channel_merge { 138 int id; 139 int reg; 140 unsigned int sel_shift; 141 unsigned int sel_maskbit; 142 unsigned int sel_default; 143 unsigned int ch_num_shift; 144 unsigned int ch_num_maskbit; 145 unsigned int en_shift; 146 unsigned int en_maskbit; 147 unsigned int update_cnt_shift; 148 unsigned int update_cnt_maskbit; 149 unsigned int update_cnt_default; 150 }; 151 152 static const struct mt8195_afe_channel_merge 153 mt8195_afe_cm[MT8195_AFE_CM_NUM] = { 154 [MT8195_AFE_CM0] = { 155 .id = MT8195_AFE_CM0, 156 .reg = AFE_CM0_CON, 157 .sel_shift = 30, 158 .sel_maskbit = 0x1, 159 .sel_default = 1, 160 .ch_num_shift = 2, 161 .ch_num_maskbit = 0x3f, 162 .en_shift = 0, 163 .en_maskbit = 0x1, 164 .update_cnt_shift = 16, 165 .update_cnt_maskbit = 0x1fff, 166 .update_cnt_default = 0x3, 167 }, 168 [MT8195_AFE_CM1] = { 169 .id = MT8195_AFE_CM1, 170 .reg = AFE_CM1_CON, 171 .sel_shift = 30, 172 .sel_maskbit = 0x1, 173 .sel_default = 1, 174 .ch_num_shift = 2, 175 .ch_num_maskbit = 0x1f, 176 .en_shift = 0, 177 .en_maskbit = 0x1, 178 .update_cnt_shift = 16, 179 .update_cnt_maskbit = 0x1fff, 180 .update_cnt_default = 0x3, 181 }, 182 [MT8195_AFE_CM2] = { 183 .id = MT8195_AFE_CM2, 184 .reg = AFE_CM2_CON, 185 .sel_shift = 30, 186 .sel_maskbit = 0x1, 187 .sel_default = 1, 188 .ch_num_shift = 2, 189 .ch_num_maskbit = 0x1f, 190 .en_shift = 0, 191 .en_maskbit = 0x1, 192 .update_cnt_shift = 16, 193 .update_cnt_maskbit = 0x1fff, 194 .update_cnt_default = 0x3, 195 }, 196 }; 197 198 static int mt8195_afe_memif_is_ul(int id) 199 { 200 if (id >= MT8195_AFE_MEMIF_UL_START && id < MT8195_AFE_MEMIF_END) 201 return 1; 202 else 203 return 0; 204 } 205 206 static const struct mt8195_afe_channel_merge* 207 mt8195_afe_found_cm(struct snd_soc_dai *dai) 208 { 209 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 210 int id = -EINVAL; 211 212 if (mt8195_afe_memif_is_ul(dai->id) == 0) 213 return NULL; 214 215 switch (dai->id) { 216 case MT8195_AFE_MEMIF_UL9: 217 id = MT8195_AFE_CM0; 218 break; 219 case MT8195_AFE_MEMIF_UL2: 220 id = MT8195_AFE_CM1; 221 break; 222 case MT8195_AFE_MEMIF_UL10: 223 id = MT8195_AFE_CM2; 224 break; 225 default: 226 break; 227 } 228 229 if (id < 0) { 230 dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n", 231 __func__, dai->id); 232 return NULL; 233 } 234 235 return &mt8195_afe_cm[id]; 236 } 237 238 static int mt8195_afe_config_cm(struct mtk_base_afe *afe, 239 const struct mt8195_afe_channel_merge *cm, 240 unsigned int channels) 241 { 242 if (!cm) 243 return -EINVAL; 244 245 regmap_update_bits(afe->regmap, 246 cm->reg, 247 cm->sel_maskbit << cm->sel_shift, 248 cm->sel_default << cm->sel_shift); 249 250 regmap_update_bits(afe->regmap, 251 cm->reg, 252 cm->ch_num_maskbit << cm->ch_num_shift, 253 (channels - 1) << cm->ch_num_shift); 254 255 regmap_update_bits(afe->regmap, 256 cm->reg, 257 cm->update_cnt_maskbit << cm->update_cnt_shift, 258 cm->update_cnt_default << cm->update_cnt_shift); 259 260 return 0; 261 } 262 263 static int mt8195_afe_enable_cm(struct mtk_base_afe *afe, 264 const struct mt8195_afe_channel_merge *cm, 265 bool enable) 266 { 267 if (!cm) 268 return -EINVAL; 269 270 regmap_update_bits(afe->regmap, 271 cm->reg, 272 cm->en_maskbit << cm->en_shift, 273 enable << cm->en_shift); 274 275 return 0; 276 } 277 278 static int 279 mt8195_afe_paired_memif_clk_prepare(struct snd_pcm_substream *substream, 280 struct snd_soc_dai *dai, 281 int enable) 282 { 283 struct snd_soc_pcm_runtime *rtd = substream->private_data; 284 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 285 struct mt8195_afe_private *afe_priv = afe->platform_priv; 286 int id = asoc_rtd_to_cpu(rtd, 0)->id; 287 int clk_id; 288 289 if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10) 290 return 0; 291 292 if (enable) { 293 clk_id = MT8195_CLK_AUD_MEMIF_DL10; 294 mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]); 295 clk_id = MT8195_CLK_AUD_MEMIF_DL8; 296 mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]); 297 } else { 298 clk_id = MT8195_CLK_AUD_MEMIF_DL8; 299 mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]); 300 clk_id = MT8195_CLK_AUD_MEMIF_DL10; 301 mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]); 302 } 303 304 return 0; 305 } 306 307 static int 308 mt8195_afe_paired_memif_clk_enable(struct snd_pcm_substream *substream, 309 struct snd_soc_dai *dai, 310 int enable) 311 { 312 struct snd_soc_pcm_runtime *rtd = substream->private_data; 313 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 314 struct mt8195_afe_private *afe_priv = afe->platform_priv; 315 int id = asoc_rtd_to_cpu(rtd, 0)->id; 316 int clk_id; 317 318 if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10) 319 return 0; 320 321 if (enable) { 322 /* DL8_DL10_MEM */ 323 clk_id = MT8195_CLK_AUD_MEMIF_DL10; 324 mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]); 325 udelay(1); 326 /* DL8_DL10_AGENT */ 327 clk_id = MT8195_CLK_AUD_MEMIF_DL8; 328 mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]); 329 } else { 330 /* DL8_DL10_AGENT */ 331 clk_id = MT8195_CLK_AUD_MEMIF_DL8; 332 mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]); 333 /* DL8_DL10_MEM */ 334 clk_id = MT8195_CLK_AUD_MEMIF_DL10; 335 mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]); 336 } 337 338 return 0; 339 } 340 341 static int mt8195_afe_fe_startup(struct snd_pcm_substream *substream, 342 struct snd_soc_dai *dai) 343 { 344 struct snd_soc_pcm_runtime *rtd = substream->private_data; 345 struct snd_pcm_runtime *runtime = substream->runtime; 346 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 347 int id = asoc_rtd_to_cpu(rtd, 0)->id; 348 int ret = 0; 349 350 mt8195_afe_paired_memif_clk_prepare(substream, dai, 1); 351 352 ret = mtk_afe_fe_startup(substream, dai); 353 354 snd_pcm_hw_constraint_step(runtime, 0, 355 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 356 MT8195_MEMIF_BUFFER_BYTES_ALIGN); 357 358 if (id != MT8195_AFE_MEMIF_DL7) 359 goto out; 360 361 ret = snd_pcm_hw_constraint_minmax(runtime, 362 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 363 1, 364 MT8195_MEMIF_DL7_MAX_PERIOD_SIZE); 365 if (ret < 0) 366 dev_dbg(afe->dev, "hw_constraint_minmax failed\n"); 367 out: 368 return ret; 369 } 370 371 static void mt8195_afe_fe_shutdown(struct snd_pcm_substream *substream, 372 struct snd_soc_dai *dai) 373 { 374 mtk_afe_fe_shutdown(substream, dai); 375 mt8195_afe_paired_memif_clk_prepare(substream, dai, 0); 376 } 377 378 static int mt8195_afe_fe_hw_params(struct snd_pcm_substream *substream, 379 struct snd_pcm_hw_params *params, 380 struct snd_soc_dai *dai) 381 { 382 struct snd_soc_pcm_runtime *rtd = substream->private_data; 383 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 384 int id = asoc_rtd_to_cpu(rtd, 0)->id; 385 struct mtk_base_afe_memif *memif = &afe->memif[id]; 386 const struct mtk_base_memif_data *data = memif->data; 387 const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai); 388 unsigned int ch_num = params_channels(params); 389 390 mt8195_afe_config_cm(afe, cm, params_channels(params)); 391 392 if (data->ch_num_reg >= 0) { 393 regmap_update_bits(afe->regmap, data->ch_num_reg, 394 data->ch_num_maskbit << data->ch_num_shift, 395 ch_num << data->ch_num_shift); 396 } 397 398 return mtk_afe_fe_hw_params(substream, params, dai); 399 } 400 401 static int mt8195_afe_fe_hw_free(struct snd_pcm_substream *substream, 402 struct snd_soc_dai *dai) 403 { 404 return mtk_afe_fe_hw_free(substream, dai); 405 } 406 407 static int mt8195_afe_fe_prepare(struct snd_pcm_substream *substream, 408 struct snd_soc_dai *dai) 409 { 410 return mtk_afe_fe_prepare(substream, dai); 411 } 412 413 static int mt8195_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd, 414 struct snd_soc_dai *dai) 415 { 416 int ret = 0; 417 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 418 const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai); 419 420 switch (cmd) { 421 case SNDRV_PCM_TRIGGER_START: 422 case SNDRV_PCM_TRIGGER_RESUME: 423 mt8195_afe_enable_cm(afe, cm, true); 424 break; 425 case SNDRV_PCM_TRIGGER_STOP: 426 case SNDRV_PCM_TRIGGER_SUSPEND: 427 mt8195_afe_enable_cm(afe, cm, false); 428 break; 429 default: 430 break; 431 } 432 433 ret = mtk_afe_fe_trigger(substream, cmd, dai); 434 435 switch (cmd) { 436 case SNDRV_PCM_TRIGGER_START: 437 case SNDRV_PCM_TRIGGER_RESUME: 438 mt8195_afe_paired_memif_clk_enable(substream, dai, 1); 439 break; 440 case SNDRV_PCM_TRIGGER_STOP: 441 case SNDRV_PCM_TRIGGER_SUSPEND: 442 mt8195_afe_paired_memif_clk_enable(substream, dai, 0); 443 break; 444 default: 445 break; 446 } 447 448 return ret; 449 } 450 451 static int mt8195_afe_fe_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 452 { 453 return 0; 454 } 455 456 static const struct snd_soc_dai_ops mt8195_afe_fe_dai_ops = { 457 .startup = mt8195_afe_fe_startup, 458 .shutdown = mt8195_afe_fe_shutdown, 459 .hw_params = mt8195_afe_fe_hw_params, 460 .hw_free = mt8195_afe_fe_hw_free, 461 .prepare = mt8195_afe_fe_prepare, 462 .trigger = mt8195_afe_fe_trigger, 463 .set_fmt = mt8195_afe_fe_set_fmt, 464 }; 465 466 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 467 SNDRV_PCM_RATE_88200 |\ 468 SNDRV_PCM_RATE_96000 |\ 469 SNDRV_PCM_RATE_176400 |\ 470 SNDRV_PCM_RATE_192000 |\ 471 SNDRV_PCM_RATE_352800 |\ 472 SNDRV_PCM_RATE_384000) 473 474 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 475 SNDRV_PCM_FMTBIT_S24_LE |\ 476 SNDRV_PCM_FMTBIT_S32_LE) 477 478 static struct snd_soc_dai_driver mt8195_memif_dai_driver[] = { 479 /* FE DAIs: memory intefaces to CPU */ 480 { 481 .name = "DL2", 482 .id = MT8195_AFE_MEMIF_DL2, 483 .playback = { 484 .stream_name = "DL2", 485 .channels_min = 1, 486 .channels_max = 2, 487 .rates = MTK_PCM_RATES, 488 .formats = MTK_PCM_FORMATS, 489 }, 490 .ops = &mt8195_afe_fe_dai_ops, 491 }, 492 { 493 .name = "DL3", 494 .id = MT8195_AFE_MEMIF_DL3, 495 .playback = { 496 .stream_name = "DL3", 497 .channels_min = 1, 498 .channels_max = 2, 499 .rates = MTK_PCM_RATES, 500 .formats = MTK_PCM_FORMATS, 501 }, 502 .ops = &mt8195_afe_fe_dai_ops, 503 }, 504 { 505 .name = "DL6", 506 .id = MT8195_AFE_MEMIF_DL6, 507 .playback = { 508 .stream_name = "DL6", 509 .channels_min = 1, 510 .channels_max = 2, 511 .rates = MTK_PCM_RATES, 512 .formats = MTK_PCM_FORMATS, 513 }, 514 .ops = &mt8195_afe_fe_dai_ops, 515 }, 516 { 517 .name = "DL7", 518 .id = MT8195_AFE_MEMIF_DL7, 519 .playback = { 520 .stream_name = "DL7", 521 .channels_min = 1, 522 .channels_max = 2, 523 .rates = MTK_PCM_RATES, 524 .formats = MTK_PCM_FORMATS, 525 }, 526 .ops = &mt8195_afe_fe_dai_ops, 527 }, 528 { 529 .name = "DL8", 530 .id = MT8195_AFE_MEMIF_DL8, 531 .playback = { 532 .stream_name = "DL8", 533 .channels_min = 1, 534 .channels_max = 24, 535 .rates = MTK_PCM_RATES, 536 .formats = MTK_PCM_FORMATS, 537 }, 538 .ops = &mt8195_afe_fe_dai_ops, 539 }, 540 { 541 .name = "DL10", 542 .id = MT8195_AFE_MEMIF_DL10, 543 .playback = { 544 .stream_name = "DL10", 545 .channels_min = 1, 546 .channels_max = 8, 547 .rates = MTK_PCM_RATES, 548 .formats = MTK_PCM_FORMATS, 549 }, 550 .ops = &mt8195_afe_fe_dai_ops, 551 }, 552 { 553 .name = "DL11", 554 .id = MT8195_AFE_MEMIF_DL11, 555 .playback = { 556 .stream_name = "DL11", 557 .channels_min = 1, 558 .channels_max = 48, 559 .rates = MTK_PCM_RATES, 560 .formats = MTK_PCM_FORMATS, 561 }, 562 .ops = &mt8195_afe_fe_dai_ops, 563 }, 564 { 565 .name = "UL1", 566 .id = MT8195_AFE_MEMIF_UL1, 567 .capture = { 568 .stream_name = "UL1", 569 .channels_min = 1, 570 .channels_max = 8, 571 .rates = MTK_PCM_RATES, 572 .formats = MTK_PCM_FORMATS, 573 }, 574 .ops = &mt8195_afe_fe_dai_ops, 575 }, 576 { 577 .name = "UL2", 578 .id = MT8195_AFE_MEMIF_UL2, 579 .capture = { 580 .stream_name = "UL2", 581 .channels_min = 1, 582 .channels_max = 8, 583 .rates = MTK_PCM_RATES, 584 .formats = MTK_PCM_FORMATS, 585 }, 586 .ops = &mt8195_afe_fe_dai_ops, 587 }, 588 { 589 .name = "UL3", 590 .id = MT8195_AFE_MEMIF_UL3, 591 .capture = { 592 .stream_name = "UL3", 593 .channels_min = 1, 594 .channels_max = 16, 595 .rates = MTK_PCM_RATES, 596 .formats = MTK_PCM_FORMATS, 597 }, 598 .ops = &mt8195_afe_fe_dai_ops, 599 }, 600 { 601 .name = "UL4", 602 .id = MT8195_AFE_MEMIF_UL4, 603 .capture = { 604 .stream_name = "UL4", 605 .channels_min = 1, 606 .channels_max = 2, 607 .rates = MTK_PCM_RATES, 608 .formats = MTK_PCM_FORMATS, 609 }, 610 .ops = &mt8195_afe_fe_dai_ops, 611 }, 612 { 613 .name = "UL5", 614 .id = MT8195_AFE_MEMIF_UL5, 615 .capture = { 616 .stream_name = "UL5", 617 .channels_min = 1, 618 .channels_max = 2, 619 .rates = MTK_PCM_RATES, 620 .formats = MTK_PCM_FORMATS, 621 }, 622 .ops = &mt8195_afe_fe_dai_ops, 623 }, 624 { 625 .name = "UL6", 626 .id = MT8195_AFE_MEMIF_UL6, 627 .capture = { 628 .stream_name = "UL6", 629 .channels_min = 1, 630 .channels_max = 8, 631 .rates = MTK_PCM_RATES, 632 .formats = MTK_PCM_FORMATS, 633 }, 634 .ops = &mt8195_afe_fe_dai_ops, 635 }, 636 { 637 .name = "UL8", 638 .id = MT8195_AFE_MEMIF_UL8, 639 .capture = { 640 .stream_name = "UL8", 641 .channels_min = 1, 642 .channels_max = 24, 643 .rates = MTK_PCM_RATES, 644 .formats = MTK_PCM_FORMATS, 645 }, 646 .ops = &mt8195_afe_fe_dai_ops, 647 }, 648 { 649 .name = "UL9", 650 .id = MT8195_AFE_MEMIF_UL9, 651 .capture = { 652 .stream_name = "UL9", 653 .channels_min = 1, 654 .channels_max = 32, 655 .rates = MTK_PCM_RATES, 656 .formats = MTK_PCM_FORMATS, 657 }, 658 .ops = &mt8195_afe_fe_dai_ops, 659 }, 660 { 661 .name = "UL10", 662 .id = MT8195_AFE_MEMIF_UL10, 663 .capture = { 664 .stream_name = "UL10", 665 .channels_min = 1, 666 .channels_max = 4, 667 .rates = MTK_PCM_RATES, 668 .formats = MTK_PCM_FORMATS, 669 }, 670 .ops = &mt8195_afe_fe_dai_ops, 671 }, 672 }; 673 674 static const struct snd_kcontrol_new o002_mix[] = { 675 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0), 676 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0), 677 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0), 678 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0), 679 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0), 680 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0), 681 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0), 682 }; 683 684 static const struct snd_kcontrol_new o003_mix[] = { 685 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0), 686 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0), 687 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0), 688 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0), 689 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0), 690 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0), 691 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0), 692 }; 693 694 static const struct snd_kcontrol_new o004_mix[] = { 695 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0), 696 SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0), 697 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0), 698 SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0), 699 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN4_5, 10, 1, 0), 700 }; 701 702 static const struct snd_kcontrol_new o005_mix[] = { 703 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0), 704 SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0), 705 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0), 706 SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0), 707 SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN5_5, 11, 1, 0), 708 }; 709 710 static const struct snd_kcontrol_new o006_mix[] = { 711 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0), 712 SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0), 713 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0), 714 SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0), 715 }; 716 717 static const struct snd_kcontrol_new o007_mix[] = { 718 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0), 719 SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0), 720 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0), 721 SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0), 722 }; 723 724 static const struct snd_kcontrol_new o008_mix[] = { 725 SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0), 726 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0), 727 SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0), 728 }; 729 730 static const struct snd_kcontrol_new o009_mix[] = { 731 SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0), 732 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0), 733 SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0), 734 }; 735 736 static const struct snd_kcontrol_new o010_mix[] = { 737 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0), 738 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0), 739 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0), 740 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0), 741 }; 742 743 static const struct snd_kcontrol_new o011_mix[] = { 744 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0), 745 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0), 746 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0), 747 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0), 748 }; 749 750 static const struct snd_kcontrol_new o012_mix[] = { 751 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0), 752 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0), 753 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0), 754 SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0), 755 }; 756 757 static const struct snd_kcontrol_new o013_mix[] = { 758 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0), 759 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0), 760 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0), 761 SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0), 762 }; 763 764 static const struct snd_kcontrol_new o014_mix[] = { 765 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0), 766 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0), 767 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0), 768 SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0), 769 }; 770 771 static const struct snd_kcontrol_new o015_mix[] = { 772 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0), 773 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0), 774 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0), 775 SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0), 776 }; 777 778 static const struct snd_kcontrol_new o016_mix[] = { 779 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0), 780 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0), 781 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0), 782 SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0), 783 }; 784 785 static const struct snd_kcontrol_new o017_mix[] = { 786 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0), 787 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0), 788 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0), 789 SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0), 790 }; 791 792 static const struct snd_kcontrol_new o018_mix[] = { 793 SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN18_1, 6, 1, 0), 794 SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0), 795 }; 796 797 static const struct snd_kcontrol_new o019_mix[] = { 798 SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN19_1, 7, 1, 0), 799 SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0), 800 }; 801 802 static const struct snd_kcontrol_new o020_mix[] = { 803 SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN20_1, 8, 1, 0), 804 SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0), 805 }; 806 807 static const struct snd_kcontrol_new o021_mix[] = { 808 SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN21_1, 9, 1, 0), 809 SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0), 810 }; 811 812 static const struct snd_kcontrol_new o022_mix[] = { 813 SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN22_1, 10, 1, 0), 814 SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0), 815 }; 816 817 static const struct snd_kcontrol_new o023_mix[] = { 818 SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN23_1, 11, 1, 0), 819 SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0), 820 }; 821 822 static const struct snd_kcontrol_new o024_mix[] = { 823 SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN24_1, 12, 1, 0), 824 SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0), 825 }; 826 827 static const struct snd_kcontrol_new o025_mix[] = { 828 SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN25_1, 13, 1, 0), 829 SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0), 830 }; 831 832 static const struct snd_kcontrol_new o026_mix[] = { 833 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0), 834 SOC_DAPM_SINGLE_AUTODISABLE("I088 Switch", AFE_CONN26_2, 24, 1, 0), 835 }; 836 837 static const struct snd_kcontrol_new o027_mix[] = { 838 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0), 839 SOC_DAPM_SINGLE_AUTODISABLE("I089 Switch", AFE_CONN27_2, 25, 1, 0), 840 }; 841 842 static const struct snd_kcontrol_new o028_mix[] = { 843 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0), 844 SOC_DAPM_SINGLE_AUTODISABLE("I090 Switch", AFE_CONN28_2, 26, 1, 0), 845 }; 846 847 static const struct snd_kcontrol_new o029_mix[] = { 848 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0), 849 SOC_DAPM_SINGLE_AUTODISABLE("I091 Switch", AFE_CONN29_2, 27, 1, 0), 850 }; 851 852 static const struct snd_kcontrol_new o030_mix[] = { 853 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0), 854 SOC_DAPM_SINGLE_AUTODISABLE("I092 Switch", AFE_CONN30_2, 28, 1, 0), 855 }; 856 857 static const struct snd_kcontrol_new o031_mix[] = { 858 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0), 859 SOC_DAPM_SINGLE_AUTODISABLE("I093 Switch", AFE_CONN31_2, 29, 1, 0), 860 }; 861 862 static const struct snd_kcontrol_new o032_mix[] = { 863 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0), 864 SOC_DAPM_SINGLE_AUTODISABLE("I094 Switch", AFE_CONN32_2, 30, 1, 0), 865 }; 866 867 static const struct snd_kcontrol_new o033_mix[] = { 868 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0), 869 SOC_DAPM_SINGLE_AUTODISABLE("I095 Switch", AFE_CONN33_2, 31, 1, 0), 870 }; 871 872 static const struct snd_kcontrol_new o034_mix[] = { 873 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0), 874 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0), 875 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0), 876 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0), 877 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0), 878 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0), 879 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0), 880 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN34_5, 10, 1, 0), 881 }; 882 883 static const struct snd_kcontrol_new o035_mix[] = { 884 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0), 885 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0), 886 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0), 887 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0), 888 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0), 889 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0), 890 SOC_DAPM_SINGLE_AUTODISABLE("I137 Switch", AFE_CONN35_4, 9, 1, 0), 891 SOC_DAPM_SINGLE_AUTODISABLE("I139 Switch", AFE_CONN35_4, 11, 1, 0), 892 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0), 893 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0), 894 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN35_5, 10, 1, 0), 895 SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN35_5, 11, 1, 0), 896 }; 897 898 static const struct snd_kcontrol_new o036_mix[] = { 899 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0), 900 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0), 901 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0), 902 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0), 903 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0), 904 }; 905 906 static const struct snd_kcontrol_new o037_mix[] = { 907 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0), 908 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0), 909 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0), 910 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0), 911 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0), 912 }; 913 914 static const struct snd_kcontrol_new o038_mix[] = { 915 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0), 916 }; 917 918 static const struct snd_kcontrol_new o039_mix[] = { 919 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0), 920 }; 921 922 static const struct snd_kcontrol_new o040_mix[] = { 923 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0), 924 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0), 925 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0), 926 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0), 927 }; 928 929 static const struct snd_kcontrol_new o041_mix[] = { 930 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0), 931 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0), 932 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0), 933 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0), 934 }; 935 936 static const struct snd_kcontrol_new o042_mix[] = { 937 SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0), 938 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0), 939 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN42_5, 10, 1, 0), 940 }; 941 942 static const struct snd_kcontrol_new o043_mix[] = { 943 SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0), 944 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0), 945 SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN43_5, 11, 1, 0), 946 }; 947 948 static const struct snd_kcontrol_new o044_mix[] = { 949 SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0), 950 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0), 951 }; 952 953 static const struct snd_kcontrol_new o045_mix[] = { 954 SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0), 955 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0), 956 }; 957 958 static const struct snd_kcontrol_new o046_mix[] = { 959 SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0), 960 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0), 961 }; 962 963 static const struct snd_kcontrol_new o047_mix[] = { 964 SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0), 965 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0), 966 }; 967 968 static const struct snd_kcontrol_new o182_mix[] = { 969 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0), 970 }; 971 972 static const struct snd_kcontrol_new o183_mix[] = { 973 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0), 974 }; 975 976 static const char * const dl8_dl11_data_sel_mux_text[] = { 977 "dl8", "dl11", 978 }; 979 980 static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum, 981 AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text); 982 983 static const struct snd_kcontrol_new dl8_dl11_data_sel_mux = 984 SOC_DAPM_ENUM("DL8_DL11 Sink", dl8_dl11_data_sel_mux_enum); 985 986 static const struct snd_soc_dapm_widget mt8195_memif_widgets[] = { 987 /* DL6 */ 988 SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0), 989 SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0), 990 991 /* DL3 */ 992 SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0), 993 SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0), 994 995 /* DL11 */ 996 SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0), 997 SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0), 998 SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0), 999 SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0), 1000 SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0), 1001 SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0), 1002 SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0), 1003 SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0), 1004 SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0), 1005 SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0), 1006 SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0), 1007 SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0), 1008 SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0), 1009 SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0), 1010 SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0), 1011 SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0), 1012 SND_SOC_DAPM_MIXER("I038", SND_SOC_NOPM, 0, 0, NULL, 0), 1013 SND_SOC_DAPM_MIXER("I039", SND_SOC_NOPM, 0, 0, NULL, 0), 1014 SND_SOC_DAPM_MIXER("I040", SND_SOC_NOPM, 0, 0, NULL, 0), 1015 SND_SOC_DAPM_MIXER("I041", SND_SOC_NOPM, 0, 0, NULL, 0), 1016 SND_SOC_DAPM_MIXER("I042", SND_SOC_NOPM, 0, 0, NULL, 0), 1017 SND_SOC_DAPM_MIXER("I043", SND_SOC_NOPM, 0, 0, NULL, 0), 1018 SND_SOC_DAPM_MIXER("I044", SND_SOC_NOPM, 0, 0, NULL, 0), 1019 SND_SOC_DAPM_MIXER("I045", SND_SOC_NOPM, 0, 0, NULL, 0), 1020 1021 /* DL11/DL8 */ 1022 SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0), 1023 SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0), 1024 SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0), 1025 SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0), 1026 SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0), 1027 SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0), 1028 SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0), 1029 SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0), 1030 SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0), 1031 SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0), 1032 SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0), 1033 SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0), 1034 SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0), 1035 SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0), 1036 SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0), 1037 SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0), 1038 SND_SOC_DAPM_MIXER("I062", SND_SOC_NOPM, 0, 0, NULL, 0), 1039 SND_SOC_DAPM_MIXER("I063", SND_SOC_NOPM, 0, 0, NULL, 0), 1040 SND_SOC_DAPM_MIXER("I064", SND_SOC_NOPM, 0, 0, NULL, 0), 1041 SND_SOC_DAPM_MIXER("I065", SND_SOC_NOPM, 0, 0, NULL, 0), 1042 SND_SOC_DAPM_MIXER("I066", SND_SOC_NOPM, 0, 0, NULL, 0), 1043 SND_SOC_DAPM_MIXER("I067", SND_SOC_NOPM, 0, 0, NULL, 0), 1044 SND_SOC_DAPM_MIXER("I068", SND_SOC_NOPM, 0, 0, NULL, 0), 1045 SND_SOC_DAPM_MIXER("I069", SND_SOC_NOPM, 0, 0, NULL, 0), 1046 1047 /* DL2 */ 1048 SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0), 1049 SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0), 1050 1051 SND_SOC_DAPM_MUX("DL8_DL11 Mux", 1052 SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux), 1053 1054 /* UL9 */ 1055 SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0, 1056 o002_mix, ARRAY_SIZE(o002_mix)), 1057 SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0, 1058 o003_mix, ARRAY_SIZE(o003_mix)), 1059 SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0, 1060 o004_mix, ARRAY_SIZE(o004_mix)), 1061 SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0, 1062 o005_mix, ARRAY_SIZE(o005_mix)), 1063 SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0, 1064 o006_mix, ARRAY_SIZE(o006_mix)), 1065 SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0, 1066 o007_mix, ARRAY_SIZE(o007_mix)), 1067 SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0, 1068 o008_mix, ARRAY_SIZE(o008_mix)), 1069 SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0, 1070 o009_mix, ARRAY_SIZE(o009_mix)), 1071 SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0, 1072 o010_mix, ARRAY_SIZE(o010_mix)), 1073 SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0, 1074 o011_mix, ARRAY_SIZE(o011_mix)), 1075 SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0, 1076 o012_mix, ARRAY_SIZE(o012_mix)), 1077 SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0, 1078 o013_mix, ARRAY_SIZE(o013_mix)), 1079 SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0, 1080 o014_mix, ARRAY_SIZE(o014_mix)), 1081 SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0, 1082 o015_mix, ARRAY_SIZE(o015_mix)), 1083 SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0, 1084 o016_mix, ARRAY_SIZE(o016_mix)), 1085 SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0, 1086 o017_mix, ARRAY_SIZE(o017_mix)), 1087 SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0, 1088 o018_mix, ARRAY_SIZE(o018_mix)), 1089 SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0, 1090 o019_mix, ARRAY_SIZE(o019_mix)), 1091 SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0, 1092 o020_mix, ARRAY_SIZE(o020_mix)), 1093 SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0, 1094 o021_mix, ARRAY_SIZE(o021_mix)), 1095 SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0, 1096 o022_mix, ARRAY_SIZE(o022_mix)), 1097 SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0, 1098 o023_mix, ARRAY_SIZE(o023_mix)), 1099 SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0, 1100 o024_mix, ARRAY_SIZE(o024_mix)), 1101 SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0, 1102 o025_mix, ARRAY_SIZE(o025_mix)), 1103 SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0, 1104 o026_mix, ARRAY_SIZE(o026_mix)), 1105 SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0, 1106 o027_mix, ARRAY_SIZE(o027_mix)), 1107 SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0, 1108 o028_mix, ARRAY_SIZE(o028_mix)), 1109 SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0, 1110 o029_mix, ARRAY_SIZE(o029_mix)), 1111 SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0, 1112 o030_mix, ARRAY_SIZE(o030_mix)), 1113 SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0, 1114 o031_mix, ARRAY_SIZE(o031_mix)), 1115 SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0, 1116 o032_mix, ARRAY_SIZE(o032_mix)), 1117 SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0, 1118 o033_mix, ARRAY_SIZE(o033_mix)), 1119 1120 /* UL4 */ 1121 SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0, 1122 o034_mix, ARRAY_SIZE(o034_mix)), 1123 SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0, 1124 o035_mix, ARRAY_SIZE(o035_mix)), 1125 1126 /* UL5 */ 1127 SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0, 1128 o036_mix, ARRAY_SIZE(o036_mix)), 1129 SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0, 1130 o037_mix, ARRAY_SIZE(o037_mix)), 1131 1132 /* UL10 */ 1133 SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0, 1134 o038_mix, ARRAY_SIZE(o038_mix)), 1135 SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0, 1136 o039_mix, ARRAY_SIZE(o039_mix)), 1137 SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0, 1138 o182_mix, ARRAY_SIZE(o182_mix)), 1139 SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0, 1140 o183_mix, ARRAY_SIZE(o183_mix)), 1141 1142 /* UL2 */ 1143 SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0, 1144 o040_mix, ARRAY_SIZE(o040_mix)), 1145 SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0, 1146 o041_mix, ARRAY_SIZE(o041_mix)), 1147 SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0, 1148 o042_mix, ARRAY_SIZE(o042_mix)), 1149 SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0, 1150 o043_mix, ARRAY_SIZE(o043_mix)), 1151 SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0, 1152 o044_mix, ARRAY_SIZE(o044_mix)), 1153 SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0, 1154 o045_mix, ARRAY_SIZE(o045_mix)), 1155 SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0, 1156 o046_mix, ARRAY_SIZE(o046_mix)), 1157 SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0, 1158 o047_mix, ARRAY_SIZE(o047_mix)), 1159 }; 1160 1161 static const struct snd_soc_dapm_route mt8195_memif_routes[] = { 1162 {"I000", NULL, "DL6"}, 1163 {"I001", NULL, "DL6"}, 1164 1165 {"I020", NULL, "DL3"}, 1166 {"I021", NULL, "DL3"}, 1167 1168 {"I022", NULL, "DL11"}, 1169 {"I023", NULL, "DL11"}, 1170 {"I024", NULL, "DL11"}, 1171 {"I025", NULL, "DL11"}, 1172 {"I026", NULL, "DL11"}, 1173 {"I027", NULL, "DL11"}, 1174 {"I028", NULL, "DL11"}, 1175 {"I029", NULL, "DL11"}, 1176 {"I030", NULL, "DL11"}, 1177 {"I031", NULL, "DL11"}, 1178 {"I032", NULL, "DL11"}, 1179 {"I033", NULL, "DL11"}, 1180 {"I034", NULL, "DL11"}, 1181 {"I035", NULL, "DL11"}, 1182 {"I036", NULL, "DL11"}, 1183 {"I037", NULL, "DL11"}, 1184 {"I038", NULL, "DL11"}, 1185 {"I039", NULL, "DL11"}, 1186 {"I040", NULL, "DL11"}, 1187 {"I041", NULL, "DL11"}, 1188 {"I042", NULL, "DL11"}, 1189 {"I043", NULL, "DL11"}, 1190 {"I044", NULL, "DL11"}, 1191 {"I045", NULL, "DL11"}, 1192 1193 {"DL8_DL11 Mux", "dl8", "DL8"}, 1194 {"DL8_DL11 Mux", "dl11", "DL11"}, 1195 1196 {"I046", NULL, "DL8_DL11 Mux"}, 1197 {"I047", NULL, "DL8_DL11 Mux"}, 1198 {"I048", NULL, "DL8_DL11 Mux"}, 1199 {"I049", NULL, "DL8_DL11 Mux"}, 1200 {"I050", NULL, "DL8_DL11 Mux"}, 1201 {"I051", NULL, "DL8_DL11 Mux"}, 1202 {"I052", NULL, "DL8_DL11 Mux"}, 1203 {"I053", NULL, "DL8_DL11 Mux"}, 1204 {"I054", NULL, "DL8_DL11 Mux"}, 1205 {"I055", NULL, "DL8_DL11 Mux"}, 1206 {"I056", NULL, "DL8_DL11 Mux"}, 1207 {"I057", NULL, "DL8_DL11 Mux"}, 1208 {"I058", NULL, "DL8_DL11 Mux"}, 1209 {"I059", NULL, "DL8_DL11 Mux"}, 1210 {"I060", NULL, "DL8_DL11 Mux"}, 1211 {"I061", NULL, "DL8_DL11 Mux"}, 1212 {"I062", NULL, "DL8_DL11 Mux"}, 1213 {"I063", NULL, "DL8_DL11 Mux"}, 1214 {"I064", NULL, "DL8_DL11 Mux"}, 1215 {"I065", NULL, "DL8_DL11 Mux"}, 1216 {"I066", NULL, "DL8_DL11 Mux"}, 1217 {"I067", NULL, "DL8_DL11 Mux"}, 1218 {"I068", NULL, "DL8_DL11 Mux"}, 1219 {"I069", NULL, "DL8_DL11 Mux"}, 1220 1221 {"I070", NULL, "DL2"}, 1222 {"I071", NULL, "DL2"}, 1223 1224 {"UL9", NULL, "O002"}, 1225 {"UL9", NULL, "O003"}, 1226 {"UL9", NULL, "O004"}, 1227 {"UL9", NULL, "O005"}, 1228 {"UL9", NULL, "O006"}, 1229 {"UL9", NULL, "O007"}, 1230 {"UL9", NULL, "O008"}, 1231 {"UL9", NULL, "O009"}, 1232 {"UL9", NULL, "O010"}, 1233 {"UL9", NULL, "O011"}, 1234 {"UL9", NULL, "O012"}, 1235 {"UL9", NULL, "O013"}, 1236 {"UL9", NULL, "O014"}, 1237 {"UL9", NULL, "O015"}, 1238 {"UL9", NULL, "O016"}, 1239 {"UL9", NULL, "O017"}, 1240 {"UL9", NULL, "O018"}, 1241 {"UL9", NULL, "O019"}, 1242 {"UL9", NULL, "O020"}, 1243 {"UL9", NULL, "O021"}, 1244 {"UL9", NULL, "O022"}, 1245 {"UL9", NULL, "O023"}, 1246 {"UL9", NULL, "O024"}, 1247 {"UL9", NULL, "O025"}, 1248 {"UL9", NULL, "O026"}, 1249 {"UL9", NULL, "O027"}, 1250 {"UL9", NULL, "O028"}, 1251 {"UL9", NULL, "O029"}, 1252 {"UL9", NULL, "O030"}, 1253 {"UL9", NULL, "O031"}, 1254 {"UL9", NULL, "O032"}, 1255 {"UL9", NULL, "O033"}, 1256 1257 {"UL4", NULL, "O034"}, 1258 {"UL4", NULL, "O035"}, 1259 1260 {"UL5", NULL, "O036"}, 1261 {"UL5", NULL, "O037"}, 1262 1263 {"UL10", NULL, "O038"}, 1264 {"UL10", NULL, "O039"}, 1265 {"UL10", NULL, "O182"}, 1266 {"UL10", NULL, "O183"}, 1267 1268 {"UL2", NULL, "O040"}, 1269 {"UL2", NULL, "O041"}, 1270 {"UL2", NULL, "O042"}, 1271 {"UL2", NULL, "O043"}, 1272 {"UL2", NULL, "O044"}, 1273 {"UL2", NULL, "O045"}, 1274 {"UL2", NULL, "O046"}, 1275 {"UL2", NULL, "O047"}, 1276 1277 {"O004", "I000 Switch", "I000"}, 1278 {"O005", "I001 Switch", "I001"}, 1279 1280 {"O006", "I000 Switch", "I000"}, 1281 {"O007", "I001 Switch", "I001"}, 1282 1283 {"O010", "I022 Switch", "I022"}, 1284 {"O011", "I023 Switch", "I023"}, 1285 {"O012", "I024 Switch", "I024"}, 1286 {"O013", "I025 Switch", "I025"}, 1287 {"O014", "I026 Switch", "I026"}, 1288 {"O015", "I027 Switch", "I027"}, 1289 {"O016", "I028 Switch", "I028"}, 1290 {"O017", "I029 Switch", "I029"}, 1291 1292 {"O010", "I046 Switch", "I046"}, 1293 {"O011", "I047 Switch", "I047"}, 1294 {"O012", "I048 Switch", "I048"}, 1295 {"O013", "I049 Switch", "I049"}, 1296 {"O014", "I050 Switch", "I050"}, 1297 {"O015", "I051 Switch", "I051"}, 1298 {"O016", "I052 Switch", "I052"}, 1299 {"O017", "I053 Switch", "I053"}, 1300 {"O002", "I022 Switch", "I022"}, 1301 {"O003", "I023 Switch", "I023"}, 1302 {"O004", "I024 Switch", "I024"}, 1303 {"O005", "I025 Switch", "I025"}, 1304 {"O006", "I026 Switch", "I026"}, 1305 {"O007", "I027 Switch", "I027"}, 1306 {"O008", "I028 Switch", "I028"}, 1307 {"O009", "I029 Switch", "I029"}, 1308 {"O010", "I030 Switch", "I030"}, 1309 {"O011", "I031 Switch", "I031"}, 1310 {"O012", "I032 Switch", "I032"}, 1311 {"O013", "I033 Switch", "I033"}, 1312 {"O014", "I034 Switch", "I034"}, 1313 {"O015", "I035 Switch", "I035"}, 1314 {"O016", "I036 Switch", "I036"}, 1315 {"O017", "I037 Switch", "I037"}, 1316 {"O018", "I038 Switch", "I038"}, 1317 {"O019", "I039 Switch", "I039"}, 1318 {"O020", "I040 Switch", "I040"}, 1319 {"O021", "I041 Switch", "I041"}, 1320 {"O022", "I042 Switch", "I042"}, 1321 {"O023", "I043 Switch", "I043"}, 1322 {"O024", "I044 Switch", "I044"}, 1323 {"O025", "I045 Switch", "I045"}, 1324 {"O026", "I046 Switch", "I046"}, 1325 {"O027", "I047 Switch", "I047"}, 1326 {"O028", "I048 Switch", "I048"}, 1327 {"O029", "I049 Switch", "I049"}, 1328 {"O030", "I050 Switch", "I050"}, 1329 {"O031", "I051 Switch", "I051"}, 1330 {"O032", "I052 Switch", "I052"}, 1331 {"O033", "I053 Switch", "I053"}, 1332 1333 {"O002", "I000 Switch", "I000"}, 1334 {"O003", "I001 Switch", "I001"}, 1335 {"O002", "I020 Switch", "I020"}, 1336 {"O003", "I021 Switch", "I021"}, 1337 {"O002", "I070 Switch", "I070"}, 1338 {"O003", "I071 Switch", "I071"}, 1339 1340 {"O034", "I000 Switch", "I000"}, 1341 {"O035", "I001 Switch", "I001"}, 1342 {"O034", "I002 Switch", "I002"}, 1343 {"O035", "I003 Switch", "I003"}, 1344 {"O034", "I012 Switch", "I012"}, 1345 {"O035", "I013 Switch", "I013"}, 1346 {"O034", "I020 Switch", "I020"}, 1347 {"O035", "I021 Switch", "I021"}, 1348 {"O034", "I070 Switch", "I070"}, 1349 {"O035", "I071 Switch", "I071"}, 1350 {"O034", "I072 Switch", "I072"}, 1351 {"O035", "I073 Switch", "I073"}, 1352 1353 {"O036", "I000 Switch", "I000"}, 1354 {"O037", "I001 Switch", "I001"}, 1355 {"O036", "I012 Switch", "I012"}, 1356 {"O037", "I013 Switch", "I013"}, 1357 {"O036", "I020 Switch", "I020"}, 1358 {"O037", "I021 Switch", "I021"}, 1359 {"O036", "I070 Switch", "I070"}, 1360 {"O037", "I071 Switch", "I071"}, 1361 {"O036", "I168 Switch", "I168"}, 1362 {"O037", "I169 Switch", "I169"}, 1363 1364 {"O038", "I022 Switch", "I022"}, 1365 {"O039", "I023 Switch", "I023"}, 1366 {"O182", "I024 Switch", "I024"}, 1367 {"O183", "I025 Switch", "I025"}, 1368 1369 {"O040", "I022 Switch", "I022"}, 1370 {"O041", "I023 Switch", "I023"}, 1371 {"O042", "I024 Switch", "I024"}, 1372 {"O043", "I025 Switch", "I025"}, 1373 {"O044", "I026 Switch", "I026"}, 1374 {"O045", "I027 Switch", "I027"}, 1375 {"O046", "I028 Switch", "I028"}, 1376 {"O047", "I029 Switch", "I029"}, 1377 1378 {"O040", "I002 Switch", "I002"}, 1379 {"O041", "I003 Switch", "I003"}, 1380 {"O002", "I012 Switch", "I012"}, 1381 {"O003", "I013 Switch", "I013"}, 1382 {"O004", "I014 Switch", "I014"}, 1383 {"O005", "I015 Switch", "I015"}, 1384 {"O006", "I016 Switch", "I016"}, 1385 {"O007", "I017 Switch", "I017"}, 1386 {"O008", "I018 Switch", "I018"}, 1387 {"O009", "I019 Switch", "I019"}, 1388 1389 {"O040", "I012 Switch", "I012"}, 1390 {"O041", "I013 Switch", "I013"}, 1391 {"O042", "I014 Switch", "I014"}, 1392 {"O043", "I015 Switch", "I015"}, 1393 {"O044", "I016 Switch", "I016"}, 1394 {"O045", "I017 Switch", "I017"}, 1395 {"O046", "I018 Switch", "I018"}, 1396 {"O047", "I019 Switch", "I019"}, 1397 1398 {"O002", "I072 Switch", "I072"}, 1399 {"O003", "I073 Switch", "I073"}, 1400 {"O004", "I074 Switch", "I074"}, 1401 {"O005", "I075 Switch", "I075"}, 1402 {"O006", "I076 Switch", "I076"}, 1403 {"O007", "I077 Switch", "I077"}, 1404 {"O008", "I078 Switch", "I078"}, 1405 {"O009", "I079 Switch", "I079"}, 1406 1407 {"O010", "I072 Switch", "I072"}, 1408 {"O011", "I073 Switch", "I073"}, 1409 {"O012", "I074 Switch", "I074"}, 1410 {"O013", "I075 Switch", "I075"}, 1411 {"O014", "I076 Switch", "I076"}, 1412 {"O015", "I077 Switch", "I077"}, 1413 {"O016", "I078 Switch", "I078"}, 1414 {"O017", "I079 Switch", "I079"}, 1415 {"O018", "I080 Switch", "I080"}, 1416 {"O019", "I081 Switch", "I081"}, 1417 {"O020", "I082 Switch", "I082"}, 1418 {"O021", "I083 Switch", "I083"}, 1419 {"O022", "I084 Switch", "I084"}, 1420 {"O023", "I085 Switch", "I085"}, 1421 {"O024", "I086 Switch", "I086"}, 1422 {"O025", "I087 Switch", "I087"}, 1423 {"O026", "I088 Switch", "I088"}, 1424 {"O027", "I089 Switch", "I089"}, 1425 {"O028", "I090 Switch", "I090"}, 1426 {"O029", "I091 Switch", "I091"}, 1427 {"O030", "I092 Switch", "I092"}, 1428 {"O031", "I093 Switch", "I093"}, 1429 {"O032", "I094 Switch", "I094"}, 1430 {"O033", "I095 Switch", "I095"}, 1431 1432 {"O002", "I168 Switch", "I168"}, 1433 {"O003", "I169 Switch", "I169"}, 1434 {"O004", "I170 Switch", "I170"}, 1435 {"O005", "I171 Switch", "I171"}, 1436 1437 {"O034", "I168 Switch", "I168"}, 1438 {"O035", "I168 Switch", "I168"}, 1439 {"O035", "I169 Switch", "I169"}, 1440 1441 {"O034", "I170 Switch", "I170"}, 1442 {"O035", "I170 Switch", "I170"}, 1443 {"O035", "I171 Switch", "I171"}, 1444 1445 {"O040", "I168 Switch", "I168"}, 1446 {"O041", "I169 Switch", "I169"}, 1447 {"O042", "I170 Switch", "I170"}, 1448 {"O043", "I171 Switch", "I171"}, 1449 }; 1450 1451 static const char * const mt8195_afe_1x_en_sel_text[] = { 1452 "a1sys_a2sys", "a3sys", "a4sys", 1453 }; 1454 1455 static const unsigned int mt8195_afe_1x_en_sel_values[] = { 1456 0, 1, 2, 1457 }; 1458 1459 static int mt8195_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol, 1460 struct snd_ctl_elem_value *ucontrol) 1461 { 1462 struct snd_soc_component *component = 1463 snd_soc_kcontrol_component(kcontrol); 1464 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1465 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1466 struct mtk_dai_memif_priv *memif_priv; 1467 unsigned int dai_id = kcontrol->id.device; 1468 long val = ucontrol->value.integer.value[0]; 1469 int ret = 0; 1470 1471 memif_priv = afe_priv->dai_priv[dai_id]; 1472 1473 if (val == memif_priv->asys_timing_sel) 1474 return 0; 1475 1476 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1477 1478 memif_priv->asys_timing_sel = val; 1479 1480 return ret; 1481 } 1482 1483 static int mt8195_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol, 1484 struct snd_ctl_elem_value *ucontrol) 1485 { 1486 struct snd_soc_component *component = 1487 snd_soc_kcontrol_component(kcontrol); 1488 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1489 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1490 unsigned int id = kcontrol->id.device; 1491 long val = ucontrol->value.integer.value[0]; 1492 int ret = 0; 1493 1494 if (val == afe_priv->irq_priv[id].asys_timing_sel) 1495 return 0; 1496 1497 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1498 1499 afe_priv->irq_priv[id].asys_timing_sel = val; 1500 1501 return ret; 1502 } 1503 1504 static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum, 1505 A3_A4_TIMING_SEL1, 18, 0x3, 1506 mt8195_afe_1x_en_sel_text, 1507 mt8195_afe_1x_en_sel_values); 1508 static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum, 1509 A3_A4_TIMING_SEL1, 20, 0x3, 1510 mt8195_afe_1x_en_sel_text, 1511 mt8195_afe_1x_en_sel_values); 1512 static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum, 1513 A3_A4_TIMING_SEL1, 22, 0x3, 1514 mt8195_afe_1x_en_sel_text, 1515 mt8195_afe_1x_en_sel_values); 1516 static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum, 1517 A3_A4_TIMING_SEL1, 24, 0x3, 1518 mt8195_afe_1x_en_sel_text, 1519 mt8195_afe_1x_en_sel_values); 1520 static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum, 1521 A3_A4_TIMING_SEL1, 26, 0x3, 1522 mt8195_afe_1x_en_sel_text, 1523 mt8195_afe_1x_en_sel_values); 1524 static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum, 1525 A3_A4_TIMING_SEL1, 28, 0x3, 1526 mt8195_afe_1x_en_sel_text, 1527 mt8195_afe_1x_en_sel_values); 1528 static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum, 1529 A3_A4_TIMING_SEL1, 30, 0x3, 1530 mt8195_afe_1x_en_sel_text, 1531 mt8195_afe_1x_en_sel_values); 1532 static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum, 1533 A3_A4_TIMING_SEL1, 0, 0x3, 1534 mt8195_afe_1x_en_sel_text, 1535 mt8195_afe_1x_en_sel_values); 1536 static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum, 1537 A3_A4_TIMING_SEL1, 2, 0x3, 1538 mt8195_afe_1x_en_sel_text, 1539 mt8195_afe_1x_en_sel_values); 1540 static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum, 1541 A3_A4_TIMING_SEL1, 4, 0x3, 1542 mt8195_afe_1x_en_sel_text, 1543 mt8195_afe_1x_en_sel_values); 1544 static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum, 1545 A3_A4_TIMING_SEL1, 6, 0x3, 1546 mt8195_afe_1x_en_sel_text, 1547 mt8195_afe_1x_en_sel_values); 1548 static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum, 1549 A3_A4_TIMING_SEL1, 8, 0x3, 1550 mt8195_afe_1x_en_sel_text, 1551 mt8195_afe_1x_en_sel_values); 1552 static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum, 1553 A3_A4_TIMING_SEL1, 10, 0x3, 1554 mt8195_afe_1x_en_sel_text, 1555 mt8195_afe_1x_en_sel_values); 1556 static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum, 1557 A3_A4_TIMING_SEL1, 12, 0x3, 1558 mt8195_afe_1x_en_sel_text, 1559 mt8195_afe_1x_en_sel_values); 1560 static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum, 1561 A3_A4_TIMING_SEL1, 14, 0x3, 1562 mt8195_afe_1x_en_sel_text, 1563 mt8195_afe_1x_en_sel_values); 1564 static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum, 1565 A3_A4_TIMING_SEL1, 16, 0x3, 1566 mt8195_afe_1x_en_sel_text, 1567 mt8195_afe_1x_en_sel_values); 1568 1569 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum, 1570 A3_A4_TIMING_SEL6, 0, 0x3, 1571 mt8195_afe_1x_en_sel_text, 1572 mt8195_afe_1x_en_sel_values); 1573 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum, 1574 A3_A4_TIMING_SEL6, 2, 0x3, 1575 mt8195_afe_1x_en_sel_text, 1576 mt8195_afe_1x_en_sel_values); 1577 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum, 1578 A3_A4_TIMING_SEL6, 4, 0x3, 1579 mt8195_afe_1x_en_sel_text, 1580 mt8195_afe_1x_en_sel_values); 1581 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum, 1582 A3_A4_TIMING_SEL6, 6, 0x3, 1583 mt8195_afe_1x_en_sel_text, 1584 mt8195_afe_1x_en_sel_values); 1585 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum, 1586 A3_A4_TIMING_SEL6, 8, 0x3, 1587 mt8195_afe_1x_en_sel_text, 1588 mt8195_afe_1x_en_sel_values); 1589 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum, 1590 A3_A4_TIMING_SEL6, 10, 0x3, 1591 mt8195_afe_1x_en_sel_text, 1592 mt8195_afe_1x_en_sel_values); 1593 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum, 1594 A3_A4_TIMING_SEL6, 12, 0x3, 1595 mt8195_afe_1x_en_sel_text, 1596 mt8195_afe_1x_en_sel_values); 1597 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum, 1598 A3_A4_TIMING_SEL6, 14, 0x3, 1599 mt8195_afe_1x_en_sel_text, 1600 mt8195_afe_1x_en_sel_values); 1601 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum, 1602 A3_A4_TIMING_SEL6, 16, 0x3, 1603 mt8195_afe_1x_en_sel_text, 1604 mt8195_afe_1x_en_sel_values); 1605 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum, 1606 A3_A4_TIMING_SEL6, 18, 0x3, 1607 mt8195_afe_1x_en_sel_text, 1608 mt8195_afe_1x_en_sel_values); 1609 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum, 1610 A3_A4_TIMING_SEL6, 20, 0x3, 1611 mt8195_afe_1x_en_sel_text, 1612 mt8195_afe_1x_en_sel_values); 1613 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum, 1614 A3_A4_TIMING_SEL6, 22, 0x3, 1615 mt8195_afe_1x_en_sel_text, 1616 mt8195_afe_1x_en_sel_values); 1617 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum, 1618 A3_A4_TIMING_SEL6, 24, 0x3, 1619 mt8195_afe_1x_en_sel_text, 1620 mt8195_afe_1x_en_sel_values); 1621 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum, 1622 A3_A4_TIMING_SEL6, 26, 0x3, 1623 mt8195_afe_1x_en_sel_text, 1624 mt8195_afe_1x_en_sel_values); 1625 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum, 1626 A3_A4_TIMING_SEL6, 28, 0x3, 1627 mt8195_afe_1x_en_sel_text, 1628 mt8195_afe_1x_en_sel_values); 1629 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum, 1630 A3_A4_TIMING_SEL6, 30, 0x3, 1631 mt8195_afe_1x_en_sel_text, 1632 mt8195_afe_1x_en_sel_values); 1633 1634 static const struct snd_kcontrol_new mt8195_memif_controls[] = { 1635 MT8195_SOC_ENUM_EXT("dl2_1x_en_sel", 1636 dl2_1x_en_sel_enum, 1637 snd_soc_get_enum_double, 1638 mt8195_memif_1x_en_sel_put, 1639 MT8195_AFE_MEMIF_DL2), 1640 MT8195_SOC_ENUM_EXT("dl3_1x_en_sel", 1641 dl3_1x_en_sel_enum, 1642 snd_soc_get_enum_double, 1643 mt8195_memif_1x_en_sel_put, 1644 MT8195_AFE_MEMIF_DL3), 1645 MT8195_SOC_ENUM_EXT("dl6_1x_en_sel", 1646 dl6_1x_en_sel_enum, 1647 snd_soc_get_enum_double, 1648 mt8195_memif_1x_en_sel_put, 1649 MT8195_AFE_MEMIF_DL6), 1650 MT8195_SOC_ENUM_EXT("dl7_1x_en_sel", 1651 dl7_1x_en_sel_enum, 1652 snd_soc_get_enum_double, 1653 mt8195_memif_1x_en_sel_put, 1654 MT8195_AFE_MEMIF_DL7), 1655 MT8195_SOC_ENUM_EXT("dl8_1x_en_sel", 1656 dl8_1x_en_sel_enum, 1657 snd_soc_get_enum_double, 1658 mt8195_memif_1x_en_sel_put, 1659 MT8195_AFE_MEMIF_DL8), 1660 MT8195_SOC_ENUM_EXT("dl10_1x_en_sel", 1661 dl10_1x_en_sel_enum, 1662 snd_soc_get_enum_double, 1663 mt8195_memif_1x_en_sel_put, 1664 MT8195_AFE_MEMIF_DL10), 1665 MT8195_SOC_ENUM_EXT("dl11_1x_en_sel", 1666 dl11_1x_en_sel_enum, 1667 snd_soc_get_enum_double, 1668 mt8195_memif_1x_en_sel_put, 1669 MT8195_AFE_MEMIF_DL11), 1670 MT8195_SOC_ENUM_EXT("ul1_1x_en_sel", 1671 ul1_1x_en_sel_enum, 1672 snd_soc_get_enum_double, 1673 mt8195_memif_1x_en_sel_put, 1674 MT8195_AFE_MEMIF_UL1), 1675 MT8195_SOC_ENUM_EXT("ul2_1x_en_sel", 1676 ul2_1x_en_sel_enum, 1677 snd_soc_get_enum_double, 1678 mt8195_memif_1x_en_sel_put, 1679 MT8195_AFE_MEMIF_UL2), 1680 MT8195_SOC_ENUM_EXT("ul3_1x_en_sel", 1681 ul3_1x_en_sel_enum, 1682 snd_soc_get_enum_double, 1683 mt8195_memif_1x_en_sel_put, 1684 MT8195_AFE_MEMIF_UL3), 1685 MT8195_SOC_ENUM_EXT("ul4_1x_en_sel", 1686 ul4_1x_en_sel_enum, 1687 snd_soc_get_enum_double, 1688 mt8195_memif_1x_en_sel_put, 1689 MT8195_AFE_MEMIF_UL4), 1690 MT8195_SOC_ENUM_EXT("ul5_1x_en_sel", 1691 ul5_1x_en_sel_enum, 1692 snd_soc_get_enum_double, 1693 mt8195_memif_1x_en_sel_put, 1694 MT8195_AFE_MEMIF_UL5), 1695 MT8195_SOC_ENUM_EXT("ul6_1x_en_sel", 1696 ul6_1x_en_sel_enum, 1697 snd_soc_get_enum_double, 1698 mt8195_memif_1x_en_sel_put, 1699 MT8195_AFE_MEMIF_UL6), 1700 MT8195_SOC_ENUM_EXT("ul8_1x_en_sel", 1701 ul8_1x_en_sel_enum, 1702 snd_soc_get_enum_double, 1703 mt8195_memif_1x_en_sel_put, 1704 MT8195_AFE_MEMIF_UL8), 1705 MT8195_SOC_ENUM_EXT("ul9_1x_en_sel", 1706 ul9_1x_en_sel_enum, 1707 snd_soc_get_enum_double, 1708 mt8195_memif_1x_en_sel_put, 1709 MT8195_AFE_MEMIF_UL9), 1710 MT8195_SOC_ENUM_EXT("ul10_1x_en_sel", 1711 ul10_1x_en_sel_enum, 1712 snd_soc_get_enum_double, 1713 mt8195_memif_1x_en_sel_put, 1714 MT8195_AFE_MEMIF_UL10), 1715 MT8195_SOC_ENUM_EXT("asys_irq1_1x_en_sel", 1716 asys_irq1_1x_en_sel_enum, 1717 snd_soc_get_enum_double, 1718 mt8195_asys_irq_1x_en_sel_put, 1719 MT8195_AFE_IRQ_13), 1720 MT8195_SOC_ENUM_EXT("asys_irq2_1x_en_sel", 1721 asys_irq2_1x_en_sel_enum, 1722 snd_soc_get_enum_double, 1723 mt8195_asys_irq_1x_en_sel_put, 1724 MT8195_AFE_IRQ_14), 1725 MT8195_SOC_ENUM_EXT("asys_irq3_1x_en_sel", 1726 asys_irq3_1x_en_sel_enum, 1727 snd_soc_get_enum_double, 1728 mt8195_asys_irq_1x_en_sel_put, 1729 MT8195_AFE_IRQ_15), 1730 MT8195_SOC_ENUM_EXT("asys_irq4_1x_en_sel", 1731 asys_irq4_1x_en_sel_enum, 1732 snd_soc_get_enum_double, 1733 mt8195_asys_irq_1x_en_sel_put, 1734 MT8195_AFE_IRQ_16), 1735 MT8195_SOC_ENUM_EXT("asys_irq5_1x_en_sel", 1736 asys_irq5_1x_en_sel_enum, 1737 snd_soc_get_enum_double, 1738 mt8195_asys_irq_1x_en_sel_put, 1739 MT8195_AFE_IRQ_17), 1740 MT8195_SOC_ENUM_EXT("asys_irq6_1x_en_sel", 1741 asys_irq6_1x_en_sel_enum, 1742 snd_soc_get_enum_double, 1743 mt8195_asys_irq_1x_en_sel_put, 1744 MT8195_AFE_IRQ_18), 1745 MT8195_SOC_ENUM_EXT("asys_irq7_1x_en_sel", 1746 asys_irq7_1x_en_sel_enum, 1747 snd_soc_get_enum_double, 1748 mt8195_asys_irq_1x_en_sel_put, 1749 MT8195_AFE_IRQ_19), 1750 MT8195_SOC_ENUM_EXT("asys_irq8_1x_en_sel", 1751 asys_irq8_1x_en_sel_enum, 1752 snd_soc_get_enum_double, 1753 mt8195_asys_irq_1x_en_sel_put, 1754 MT8195_AFE_IRQ_20), 1755 MT8195_SOC_ENUM_EXT("asys_irq9_1x_en_sel", 1756 asys_irq9_1x_en_sel_enum, 1757 snd_soc_get_enum_double, 1758 mt8195_asys_irq_1x_en_sel_put, 1759 MT8195_AFE_IRQ_21), 1760 MT8195_SOC_ENUM_EXT("asys_irq10_1x_en_sel", 1761 asys_irq10_1x_en_sel_enum, 1762 snd_soc_get_enum_double, 1763 mt8195_asys_irq_1x_en_sel_put, 1764 MT8195_AFE_IRQ_22), 1765 MT8195_SOC_ENUM_EXT("asys_irq11_1x_en_sel", 1766 asys_irq11_1x_en_sel_enum, 1767 snd_soc_get_enum_double, 1768 mt8195_asys_irq_1x_en_sel_put, 1769 MT8195_AFE_IRQ_23), 1770 MT8195_SOC_ENUM_EXT("asys_irq12_1x_en_sel", 1771 asys_irq12_1x_en_sel_enum, 1772 snd_soc_get_enum_double, 1773 mt8195_asys_irq_1x_en_sel_put, 1774 MT8195_AFE_IRQ_24), 1775 MT8195_SOC_ENUM_EXT("asys_irq13_1x_en_sel", 1776 asys_irq13_1x_en_sel_enum, 1777 snd_soc_get_enum_double, 1778 mt8195_asys_irq_1x_en_sel_put, 1779 MT8195_AFE_IRQ_25), 1780 MT8195_SOC_ENUM_EXT("asys_irq14_1x_en_sel", 1781 asys_irq14_1x_en_sel_enum, 1782 snd_soc_get_enum_double, 1783 mt8195_asys_irq_1x_en_sel_put, 1784 MT8195_AFE_IRQ_26), 1785 MT8195_SOC_ENUM_EXT("asys_irq15_1x_en_sel", 1786 asys_irq15_1x_en_sel_enum, 1787 snd_soc_get_enum_double, 1788 mt8195_asys_irq_1x_en_sel_put, 1789 MT8195_AFE_IRQ_27), 1790 MT8195_SOC_ENUM_EXT("asys_irq16_1x_en_sel", 1791 asys_irq16_1x_en_sel_enum, 1792 snd_soc_get_enum_double, 1793 mt8195_asys_irq_1x_en_sel_put, 1794 MT8195_AFE_IRQ_28), 1795 }; 1796 1797 static const struct snd_soc_component_driver mt8195_afe_pcm_dai_component = { 1798 .name = "mt8195-afe-pcm-dai", 1799 }; 1800 1801 static const struct mtk_base_memif_data memif_data[MT8195_AFE_MEMIF_NUM] = { 1802 [MT8195_AFE_MEMIF_DL2] = { 1803 .name = "DL2", 1804 .id = MT8195_AFE_MEMIF_DL2, 1805 .reg_ofs_base = AFE_DL2_BASE, 1806 .reg_ofs_cur = AFE_DL2_CUR, 1807 .reg_ofs_end = AFE_DL2_END, 1808 .fs_reg = AFE_MEMIF_AGENT_FS_CON0, 1809 .fs_shift = 10, 1810 .fs_maskbit = 0x1f, 1811 .mono_reg = -1, 1812 .mono_shift = 0, 1813 .int_odd_flag_reg = -1, 1814 .int_odd_flag_shift = 0, 1815 .enable_reg = AFE_DAC_CON0, 1816 .enable_shift = 18, 1817 .hd_reg = AFE_DL2_CON0, 1818 .hd_shift = 5, 1819 .agent_disable_reg = AUDIO_TOP_CON5, 1820 .agent_disable_shift = 18, 1821 .ch_num_reg = AFE_DL2_CON0, 1822 .ch_num_shift = 0, 1823 .ch_num_maskbit = 0x1f, 1824 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1825 .msb_shift = 18, 1826 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1827 .msb_end_shift = 18, 1828 }, 1829 [MT8195_AFE_MEMIF_DL3] = { 1830 .name = "DL3", 1831 .id = MT8195_AFE_MEMIF_DL3, 1832 .reg_ofs_base = AFE_DL3_BASE, 1833 .reg_ofs_cur = AFE_DL3_CUR, 1834 .reg_ofs_end = AFE_DL3_END, 1835 .fs_reg = AFE_MEMIF_AGENT_FS_CON0, 1836 .fs_shift = 15, 1837 .fs_maskbit = 0x1f, 1838 .mono_reg = -1, 1839 .mono_shift = 0, 1840 .int_odd_flag_reg = -1, 1841 .int_odd_flag_shift = 0, 1842 .enable_reg = AFE_DAC_CON0, 1843 .enable_shift = 19, 1844 .hd_reg = AFE_DL3_CON0, 1845 .hd_shift = 5, 1846 .agent_disable_reg = AUDIO_TOP_CON5, 1847 .agent_disable_shift = 19, 1848 .ch_num_reg = AFE_DL3_CON0, 1849 .ch_num_shift = 0, 1850 .ch_num_maskbit = 0x1f, 1851 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1852 .msb_shift = 19, 1853 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1854 .msb_end_shift = 19, 1855 }, 1856 [MT8195_AFE_MEMIF_DL6] = { 1857 .name = "DL6", 1858 .id = MT8195_AFE_MEMIF_DL6, 1859 .reg_ofs_base = AFE_DL6_BASE, 1860 .reg_ofs_cur = AFE_DL6_CUR, 1861 .reg_ofs_end = AFE_DL6_END, 1862 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1863 .fs_shift = 0, 1864 .fs_maskbit = 0x1f, 1865 .mono_reg = -1, 1866 .mono_shift = 0, 1867 .int_odd_flag_reg = -1, 1868 .int_odd_flag_shift = 0, 1869 .enable_reg = AFE_DAC_CON0, 1870 .enable_shift = 22, 1871 .hd_reg = AFE_DL6_CON0, 1872 .hd_shift = 5, 1873 .agent_disable_reg = AUDIO_TOP_CON5, 1874 .agent_disable_shift = 22, 1875 .ch_num_reg = AFE_DL6_CON0, 1876 .ch_num_shift = 0, 1877 .ch_num_maskbit = 0x1f, 1878 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1879 .msb_shift = 22, 1880 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1881 .msb_end_shift = 22, 1882 }, 1883 [MT8195_AFE_MEMIF_DL7] = { 1884 .name = "DL7", 1885 .id = MT8195_AFE_MEMIF_DL7, 1886 .reg_ofs_base = AFE_DL7_BASE, 1887 .reg_ofs_cur = AFE_DL7_CUR, 1888 .reg_ofs_end = AFE_DL7_END, 1889 .fs_reg = -1, 1890 .fs_shift = 0, 1891 .fs_maskbit = 0, 1892 .mono_reg = -1, 1893 .mono_shift = 0, 1894 .int_odd_flag_reg = -1, 1895 .int_odd_flag_shift = 0, 1896 .enable_reg = AFE_DAC_CON0, 1897 .enable_shift = 23, 1898 .hd_reg = AFE_DL7_CON0, 1899 .hd_shift = 5, 1900 .agent_disable_reg = AUDIO_TOP_CON5, 1901 .agent_disable_shift = 23, 1902 .ch_num_reg = AFE_DL7_CON0, 1903 .ch_num_shift = 0, 1904 .ch_num_maskbit = 0x1f, 1905 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1906 .msb_shift = 23, 1907 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1908 .msb_end_shift = 23, 1909 }, 1910 [MT8195_AFE_MEMIF_DL8] = { 1911 .name = "DL8", 1912 .id = MT8195_AFE_MEMIF_DL8, 1913 .reg_ofs_base = AFE_DL8_BASE, 1914 .reg_ofs_cur = AFE_DL8_CUR, 1915 .reg_ofs_end = AFE_DL8_END, 1916 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1917 .fs_shift = 10, 1918 .fs_maskbit = 0x1f, 1919 .mono_reg = -1, 1920 .mono_shift = 0, 1921 .int_odd_flag_reg = -1, 1922 .int_odd_flag_shift = 0, 1923 .enable_reg = AFE_DAC_CON0, 1924 .enable_shift = 24, 1925 .hd_reg = AFE_DL8_CON0, 1926 .hd_shift = 6, 1927 .agent_disable_reg = -1, 1928 .agent_disable_shift = 0, 1929 .ch_num_reg = AFE_DL8_CON0, 1930 .ch_num_shift = 0, 1931 .ch_num_maskbit = 0x3f, 1932 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1933 .msb_shift = 24, 1934 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1935 .msb_end_shift = 24, 1936 }, 1937 [MT8195_AFE_MEMIF_DL10] = { 1938 .name = "DL10", 1939 .id = MT8195_AFE_MEMIF_DL10, 1940 .reg_ofs_base = AFE_DL10_BASE, 1941 .reg_ofs_cur = AFE_DL10_CUR, 1942 .reg_ofs_end = AFE_DL10_END, 1943 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1944 .fs_shift = 20, 1945 .fs_maskbit = 0x1f, 1946 .mono_reg = -1, 1947 .mono_shift = 0, 1948 .int_odd_flag_reg = -1, 1949 .int_odd_flag_shift = 0, 1950 .enable_reg = AFE_DAC_CON0, 1951 .enable_shift = 26, 1952 .hd_reg = AFE_DL10_CON0, 1953 .hd_shift = 5, 1954 .agent_disable_reg = -1, 1955 .agent_disable_shift = 0, 1956 .ch_num_reg = AFE_DL10_CON0, 1957 .ch_num_shift = 0, 1958 .ch_num_maskbit = 0x1f, 1959 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1960 .msb_shift = 26, 1961 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1962 .msb_end_shift = 26, 1963 }, 1964 [MT8195_AFE_MEMIF_DL11] = { 1965 .name = "DL11", 1966 .id = MT8195_AFE_MEMIF_DL11, 1967 .reg_ofs_base = AFE_DL11_BASE, 1968 .reg_ofs_cur = AFE_DL11_CUR, 1969 .reg_ofs_end = AFE_DL11_END, 1970 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1971 .fs_shift = 25, 1972 .fs_maskbit = 0x1f, 1973 .mono_reg = -1, 1974 .mono_shift = 0, 1975 .int_odd_flag_reg = -1, 1976 .int_odd_flag_shift = 0, 1977 .enable_reg = AFE_DAC_CON0, 1978 .enable_shift = 27, 1979 .hd_reg = AFE_DL11_CON0, 1980 .hd_shift = 7, 1981 .agent_disable_reg = AUDIO_TOP_CON5, 1982 .agent_disable_shift = 27, 1983 .ch_num_reg = AFE_DL11_CON0, 1984 .ch_num_shift = 0, 1985 .ch_num_maskbit = 0x7f, 1986 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1987 .msb_shift = 27, 1988 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1989 .msb_end_shift = 27, 1990 }, 1991 [MT8195_AFE_MEMIF_UL1] = { 1992 .name = "UL1", 1993 .id = MT8195_AFE_MEMIF_UL1, 1994 .reg_ofs_base = AFE_UL1_BASE, 1995 .reg_ofs_cur = AFE_UL1_CUR, 1996 .reg_ofs_end = AFE_UL1_END, 1997 .fs_reg = -1, 1998 .fs_shift = 0, 1999 .fs_maskbit = 0, 2000 .mono_reg = AFE_UL1_CON0, 2001 .mono_shift = 1, 2002 .int_odd_flag_reg = AFE_UL1_CON0, 2003 .int_odd_flag_shift = 0, 2004 .enable_reg = AFE_DAC_CON0, 2005 .enable_shift = 1, 2006 .hd_reg = AFE_UL1_CON0, 2007 .hd_shift = 5, 2008 .agent_disable_reg = AUDIO_TOP_CON5, 2009 .agent_disable_shift = 0, 2010 .ch_num_reg = -1, 2011 .ch_num_shift = 0, 2012 .ch_num_maskbit = 0, 2013 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2014 .msb_shift = 0, 2015 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2016 .msb_end_shift = 0, 2017 }, 2018 [MT8195_AFE_MEMIF_UL2] = { 2019 .name = "UL2", 2020 .id = MT8195_AFE_MEMIF_UL2, 2021 .reg_ofs_base = AFE_UL2_BASE, 2022 .reg_ofs_cur = AFE_UL2_CUR, 2023 .reg_ofs_end = AFE_UL2_END, 2024 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2025 .fs_shift = 5, 2026 .fs_maskbit = 0x1f, 2027 .mono_reg = AFE_UL2_CON0, 2028 .mono_shift = 1, 2029 .int_odd_flag_reg = AFE_UL2_CON0, 2030 .int_odd_flag_shift = 0, 2031 .enable_reg = AFE_DAC_CON0, 2032 .enable_shift = 2, 2033 .hd_reg = AFE_UL2_CON0, 2034 .hd_shift = 5, 2035 .agent_disable_reg = AUDIO_TOP_CON5, 2036 .agent_disable_shift = 1, 2037 .ch_num_reg = -1, 2038 .ch_num_shift = 0, 2039 .ch_num_maskbit = 0, 2040 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2041 .msb_shift = 1, 2042 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2043 .msb_end_shift = 1, 2044 }, 2045 [MT8195_AFE_MEMIF_UL3] = { 2046 .name = "UL3", 2047 .id = MT8195_AFE_MEMIF_UL3, 2048 .reg_ofs_base = AFE_UL3_BASE, 2049 .reg_ofs_cur = AFE_UL3_CUR, 2050 .reg_ofs_end = AFE_UL3_END, 2051 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2052 .fs_shift = 10, 2053 .fs_maskbit = 0x1f, 2054 .mono_reg = AFE_UL3_CON0, 2055 .mono_shift = 1, 2056 .int_odd_flag_reg = AFE_UL3_CON0, 2057 .int_odd_flag_shift = 0, 2058 .enable_reg = AFE_DAC_CON0, 2059 .enable_shift = 3, 2060 .hd_reg = AFE_UL3_CON0, 2061 .hd_shift = 5, 2062 .agent_disable_reg = AUDIO_TOP_CON5, 2063 .agent_disable_shift = 2, 2064 .ch_num_reg = -1, 2065 .ch_num_shift = 0, 2066 .ch_num_maskbit = 0, 2067 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2068 .msb_shift = 2, 2069 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2070 .msb_end_shift = 2, 2071 }, 2072 [MT8195_AFE_MEMIF_UL4] = { 2073 .name = "UL4", 2074 .id = MT8195_AFE_MEMIF_UL4, 2075 .reg_ofs_base = AFE_UL4_BASE, 2076 .reg_ofs_cur = AFE_UL4_CUR, 2077 .reg_ofs_end = AFE_UL4_END, 2078 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2079 .fs_shift = 15, 2080 .fs_maskbit = 0x1f, 2081 .mono_reg = AFE_UL4_CON0, 2082 .mono_shift = 1, 2083 .int_odd_flag_reg = AFE_UL4_CON0, 2084 .int_odd_flag_shift = 0, 2085 .enable_reg = AFE_DAC_CON0, 2086 .enable_shift = 4, 2087 .hd_reg = AFE_UL4_CON0, 2088 .hd_shift = 5, 2089 .agent_disable_reg = AUDIO_TOP_CON5, 2090 .agent_disable_shift = 3, 2091 .ch_num_reg = -1, 2092 .ch_num_shift = 0, 2093 .ch_num_maskbit = 0, 2094 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2095 .msb_shift = 3, 2096 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2097 .msb_end_shift = 3, 2098 }, 2099 [MT8195_AFE_MEMIF_UL5] = { 2100 .name = "UL5", 2101 .id = MT8195_AFE_MEMIF_UL5, 2102 .reg_ofs_base = AFE_UL5_BASE, 2103 .reg_ofs_cur = AFE_UL5_CUR, 2104 .reg_ofs_end = AFE_UL5_END, 2105 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2106 .fs_shift = 20, 2107 .fs_maskbit = 0x1f, 2108 .mono_reg = AFE_UL5_CON0, 2109 .mono_shift = 1, 2110 .int_odd_flag_reg = AFE_UL5_CON0, 2111 .int_odd_flag_shift = 0, 2112 .enable_reg = AFE_DAC_CON0, 2113 .enable_shift = 5, 2114 .hd_reg = AFE_UL5_CON0, 2115 .hd_shift = 5, 2116 .agent_disable_reg = AUDIO_TOP_CON5, 2117 .agent_disable_shift = 4, 2118 .ch_num_reg = -1, 2119 .ch_num_shift = 0, 2120 .ch_num_maskbit = 0, 2121 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2122 .msb_shift = 4, 2123 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2124 .msb_end_shift = 4, 2125 }, 2126 [MT8195_AFE_MEMIF_UL6] = { 2127 .name = "UL6", 2128 .id = MT8195_AFE_MEMIF_UL6, 2129 .reg_ofs_base = AFE_UL6_BASE, 2130 .reg_ofs_cur = AFE_UL6_CUR, 2131 .reg_ofs_end = AFE_UL6_END, 2132 .fs_reg = -1, 2133 .fs_shift = 0, 2134 .fs_maskbit = 0, 2135 .mono_reg = AFE_UL6_CON0, 2136 .mono_shift = 1, 2137 .int_odd_flag_reg = AFE_UL6_CON0, 2138 .int_odd_flag_shift = 0, 2139 .enable_reg = AFE_DAC_CON0, 2140 .enable_shift = 6, 2141 .hd_reg = AFE_UL6_CON0, 2142 .hd_shift = 5, 2143 .agent_disable_reg = AUDIO_TOP_CON5, 2144 .agent_disable_shift = 5, 2145 .ch_num_reg = -1, 2146 .ch_num_shift = 0, 2147 .ch_num_maskbit = 0, 2148 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2149 .msb_shift = 5, 2150 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2151 .msb_end_shift = 5, 2152 }, 2153 [MT8195_AFE_MEMIF_UL8] = { 2154 .name = "UL8", 2155 .id = MT8195_AFE_MEMIF_UL8, 2156 .reg_ofs_base = AFE_UL8_BASE, 2157 .reg_ofs_cur = AFE_UL8_CUR, 2158 .reg_ofs_end = AFE_UL8_END, 2159 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2160 .fs_shift = 5, 2161 .fs_maskbit = 0x1f, 2162 .mono_reg = AFE_UL8_CON0, 2163 .mono_shift = 1, 2164 .int_odd_flag_reg = AFE_UL8_CON0, 2165 .int_odd_flag_shift = 0, 2166 .enable_reg = AFE_DAC_CON0, 2167 .enable_shift = 8, 2168 .hd_reg = AFE_UL8_CON0, 2169 .hd_shift = 5, 2170 .agent_disable_reg = AUDIO_TOP_CON5, 2171 .agent_disable_shift = 7, 2172 .ch_num_reg = -1, 2173 .ch_num_shift = 0, 2174 .ch_num_maskbit = 0, 2175 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2176 .msb_shift = 7, 2177 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2178 .msb_end_shift = 7, 2179 }, 2180 [MT8195_AFE_MEMIF_UL9] = { 2181 .name = "UL9", 2182 .id = MT8195_AFE_MEMIF_UL9, 2183 .reg_ofs_base = AFE_UL9_BASE, 2184 .reg_ofs_cur = AFE_UL9_CUR, 2185 .reg_ofs_end = AFE_UL9_END, 2186 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2187 .fs_shift = 10, 2188 .fs_maskbit = 0x1f, 2189 .mono_reg = AFE_UL9_CON0, 2190 .mono_shift = 1, 2191 .int_odd_flag_reg = AFE_UL9_CON0, 2192 .int_odd_flag_shift = 0, 2193 .enable_reg = AFE_DAC_CON0, 2194 .enable_shift = 9, 2195 .hd_reg = AFE_UL9_CON0, 2196 .hd_shift = 5, 2197 .agent_disable_reg = AUDIO_TOP_CON5, 2198 .agent_disable_shift = 8, 2199 .ch_num_reg = -1, 2200 .ch_num_shift = 0, 2201 .ch_num_maskbit = 0, 2202 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2203 .msb_shift = 8, 2204 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2205 .msb_end_shift = 8, 2206 }, 2207 [MT8195_AFE_MEMIF_UL10] = { 2208 .name = "UL10", 2209 .id = MT8195_AFE_MEMIF_UL10, 2210 .reg_ofs_base = AFE_UL10_BASE, 2211 .reg_ofs_cur = AFE_UL10_CUR, 2212 .reg_ofs_end = AFE_UL10_END, 2213 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2214 .fs_shift = 15, 2215 .fs_maskbit = 0x1f, 2216 .mono_reg = AFE_UL10_CON0, 2217 .mono_shift = 1, 2218 .int_odd_flag_reg = AFE_UL10_CON0, 2219 .int_odd_flag_shift = 0, 2220 .enable_reg = AFE_DAC_CON0, 2221 .enable_shift = 10, 2222 .hd_reg = AFE_UL10_CON0, 2223 .hd_shift = 5, 2224 .agent_disable_reg = AUDIO_TOP_CON5, 2225 .agent_disable_shift = 9, 2226 .ch_num_reg = -1, 2227 .ch_num_shift = 0, 2228 .ch_num_maskbit = 0, 2229 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2230 .msb_shift = 9, 2231 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2232 .msb_end_shift = 9, 2233 }, 2234 }; 2235 2236 static const struct mtk_base_irq_data irq_data_array[MT8195_AFE_IRQ_NUM] = { 2237 [MT8195_AFE_IRQ_1] = { 2238 .id = MT8195_AFE_IRQ_1, 2239 .irq_cnt_reg = -1, 2240 .irq_cnt_shift = 0, 2241 .irq_cnt_maskbit = 0, 2242 .irq_fs_reg = -1, 2243 .irq_fs_shift = 0, 2244 .irq_fs_maskbit = 0, 2245 .irq_en_reg = AFE_IRQ1_CON, 2246 .irq_en_shift = 31, 2247 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2248 .irq_clr_shift = 0, 2249 .irq_status_shift = 16, 2250 }, 2251 [MT8195_AFE_IRQ_2] = { 2252 .id = MT8195_AFE_IRQ_2, 2253 .irq_cnt_reg = -1, 2254 .irq_cnt_shift = 0, 2255 .irq_cnt_maskbit = 0, 2256 .irq_fs_reg = -1, 2257 .irq_fs_shift = 0, 2258 .irq_fs_maskbit = 0, 2259 .irq_en_reg = AFE_IRQ2_CON, 2260 .irq_en_shift = 31, 2261 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2262 .irq_clr_shift = 1, 2263 .irq_status_shift = 17, 2264 }, 2265 [MT8195_AFE_IRQ_3] = { 2266 .id = MT8195_AFE_IRQ_3, 2267 .irq_cnt_reg = AFE_IRQ3_CON, 2268 .irq_cnt_shift = 0, 2269 .irq_cnt_maskbit = 0xffffff, 2270 .irq_fs_reg = -1, 2271 .irq_fs_shift = 0, 2272 .irq_fs_maskbit = 0, 2273 .irq_en_reg = AFE_IRQ3_CON, 2274 .irq_en_shift = 31, 2275 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2276 .irq_clr_shift = 2, 2277 .irq_status_shift = 18, 2278 }, 2279 [MT8195_AFE_IRQ_8] = { 2280 .id = MT8195_AFE_IRQ_8, 2281 .irq_cnt_reg = -1, 2282 .irq_cnt_shift = 0, 2283 .irq_cnt_maskbit = 0, 2284 .irq_fs_reg = -1, 2285 .irq_fs_shift = 0, 2286 .irq_fs_maskbit = 0, 2287 .irq_en_reg = AFE_IRQ8_CON, 2288 .irq_en_shift = 31, 2289 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2290 .irq_clr_shift = 7, 2291 .irq_status_shift = 23, 2292 }, 2293 [MT8195_AFE_IRQ_9] = { 2294 .id = MT8195_AFE_IRQ_9, 2295 .irq_cnt_reg = AFE_IRQ9_CON, 2296 .irq_cnt_shift = 0, 2297 .irq_cnt_maskbit = 0xffffff, 2298 .irq_fs_reg = -1, 2299 .irq_fs_shift = 0, 2300 .irq_fs_maskbit = 0, 2301 .irq_en_reg = AFE_IRQ9_CON, 2302 .irq_en_shift = 31, 2303 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2304 .irq_clr_shift = 8, 2305 .irq_status_shift = 24, 2306 }, 2307 [MT8195_AFE_IRQ_10] = { 2308 .id = MT8195_AFE_IRQ_10, 2309 .irq_cnt_reg = -1, 2310 .irq_cnt_shift = 0, 2311 .irq_cnt_maskbit = 0, 2312 .irq_fs_reg = -1, 2313 .irq_fs_shift = 0, 2314 .irq_fs_maskbit = 0, 2315 .irq_en_reg = AFE_IRQ10_CON, 2316 .irq_en_shift = 31, 2317 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2318 .irq_clr_shift = 9, 2319 .irq_status_shift = 25, 2320 }, 2321 [MT8195_AFE_IRQ_13] = { 2322 .id = MT8195_AFE_IRQ_13, 2323 .irq_cnt_reg = ASYS_IRQ1_CON, 2324 .irq_cnt_shift = 0, 2325 .irq_cnt_maskbit = 0xffffff, 2326 .irq_fs_reg = ASYS_IRQ1_CON, 2327 .irq_fs_shift = 24, 2328 .irq_fs_maskbit = 0x1ffff, 2329 .irq_en_reg = ASYS_IRQ1_CON, 2330 .irq_en_shift = 31, 2331 .irq_clr_reg = ASYS_IRQ_CLR, 2332 .irq_clr_shift = 0, 2333 .irq_status_shift = 0, 2334 }, 2335 [MT8195_AFE_IRQ_14] = { 2336 .id = MT8195_AFE_IRQ_14, 2337 .irq_cnt_reg = ASYS_IRQ2_CON, 2338 .irq_cnt_shift = 0, 2339 .irq_cnt_maskbit = 0xffffff, 2340 .irq_fs_reg = ASYS_IRQ2_CON, 2341 .irq_fs_shift = 24, 2342 .irq_fs_maskbit = 0x1ffff, 2343 .irq_en_reg = ASYS_IRQ2_CON, 2344 .irq_en_shift = 31, 2345 .irq_clr_reg = ASYS_IRQ_CLR, 2346 .irq_clr_shift = 1, 2347 .irq_status_shift = 1, 2348 }, 2349 [MT8195_AFE_IRQ_15] = { 2350 .id = MT8195_AFE_IRQ_15, 2351 .irq_cnt_reg = ASYS_IRQ3_CON, 2352 .irq_cnt_shift = 0, 2353 .irq_cnt_maskbit = 0xffffff, 2354 .irq_fs_reg = ASYS_IRQ3_CON, 2355 .irq_fs_shift = 24, 2356 .irq_fs_maskbit = 0x1ffff, 2357 .irq_en_reg = ASYS_IRQ3_CON, 2358 .irq_en_shift = 31, 2359 .irq_clr_reg = ASYS_IRQ_CLR, 2360 .irq_clr_shift = 2, 2361 .irq_status_shift = 2, 2362 }, 2363 [MT8195_AFE_IRQ_16] = { 2364 .id = MT8195_AFE_IRQ_16, 2365 .irq_cnt_reg = ASYS_IRQ4_CON, 2366 .irq_cnt_shift = 0, 2367 .irq_cnt_maskbit = 0xffffff, 2368 .irq_fs_reg = ASYS_IRQ4_CON, 2369 .irq_fs_shift = 24, 2370 .irq_fs_maskbit = 0x1ffff, 2371 .irq_en_reg = ASYS_IRQ4_CON, 2372 .irq_en_shift = 31, 2373 .irq_clr_reg = ASYS_IRQ_CLR, 2374 .irq_clr_shift = 3, 2375 .irq_status_shift = 3, 2376 }, 2377 [MT8195_AFE_IRQ_17] = { 2378 .id = MT8195_AFE_IRQ_17, 2379 .irq_cnt_reg = ASYS_IRQ5_CON, 2380 .irq_cnt_shift = 0, 2381 .irq_cnt_maskbit = 0xffffff, 2382 .irq_fs_reg = ASYS_IRQ5_CON, 2383 .irq_fs_shift = 24, 2384 .irq_fs_maskbit = 0x1ffff, 2385 .irq_en_reg = ASYS_IRQ5_CON, 2386 .irq_en_shift = 31, 2387 .irq_clr_reg = ASYS_IRQ_CLR, 2388 .irq_clr_shift = 4, 2389 .irq_status_shift = 4, 2390 }, 2391 [MT8195_AFE_IRQ_18] = { 2392 .id = MT8195_AFE_IRQ_18, 2393 .irq_cnt_reg = ASYS_IRQ6_CON, 2394 .irq_cnt_shift = 0, 2395 .irq_cnt_maskbit = 0xffffff, 2396 .irq_fs_reg = ASYS_IRQ6_CON, 2397 .irq_fs_shift = 24, 2398 .irq_fs_maskbit = 0x1ffff, 2399 .irq_en_reg = ASYS_IRQ6_CON, 2400 .irq_en_shift = 31, 2401 .irq_clr_reg = ASYS_IRQ_CLR, 2402 .irq_clr_shift = 5, 2403 .irq_status_shift = 5, 2404 }, 2405 [MT8195_AFE_IRQ_19] = { 2406 .id = MT8195_AFE_IRQ_19, 2407 .irq_cnt_reg = ASYS_IRQ7_CON, 2408 .irq_cnt_shift = 0, 2409 .irq_cnt_maskbit = 0xffffff, 2410 .irq_fs_reg = ASYS_IRQ7_CON, 2411 .irq_fs_shift = 24, 2412 .irq_fs_maskbit = 0x1ffff, 2413 .irq_en_reg = ASYS_IRQ7_CON, 2414 .irq_en_shift = 31, 2415 .irq_clr_reg = ASYS_IRQ_CLR, 2416 .irq_clr_shift = 6, 2417 .irq_status_shift = 6, 2418 }, 2419 [MT8195_AFE_IRQ_20] = { 2420 .id = MT8195_AFE_IRQ_20, 2421 .irq_cnt_reg = ASYS_IRQ8_CON, 2422 .irq_cnt_shift = 0, 2423 .irq_cnt_maskbit = 0xffffff, 2424 .irq_fs_reg = ASYS_IRQ8_CON, 2425 .irq_fs_shift = 24, 2426 .irq_fs_maskbit = 0x1ffff, 2427 .irq_en_reg = ASYS_IRQ8_CON, 2428 .irq_en_shift = 31, 2429 .irq_clr_reg = ASYS_IRQ_CLR, 2430 .irq_clr_shift = 7, 2431 .irq_status_shift = 7, 2432 }, 2433 [MT8195_AFE_IRQ_21] = { 2434 .id = MT8195_AFE_IRQ_21, 2435 .irq_cnt_reg = ASYS_IRQ9_CON, 2436 .irq_cnt_shift = 0, 2437 .irq_cnt_maskbit = 0xffffff, 2438 .irq_fs_reg = ASYS_IRQ9_CON, 2439 .irq_fs_shift = 24, 2440 .irq_fs_maskbit = 0x1ffff, 2441 .irq_en_reg = ASYS_IRQ9_CON, 2442 .irq_en_shift = 31, 2443 .irq_clr_reg = ASYS_IRQ_CLR, 2444 .irq_clr_shift = 8, 2445 .irq_status_shift = 8, 2446 }, 2447 [MT8195_AFE_IRQ_22] = { 2448 .id = MT8195_AFE_IRQ_22, 2449 .irq_cnt_reg = ASYS_IRQ10_CON, 2450 .irq_cnt_shift = 0, 2451 .irq_cnt_maskbit = 0xffffff, 2452 .irq_fs_reg = ASYS_IRQ10_CON, 2453 .irq_fs_shift = 24, 2454 .irq_fs_maskbit = 0x1ffff, 2455 .irq_en_reg = ASYS_IRQ10_CON, 2456 .irq_en_shift = 31, 2457 .irq_clr_reg = ASYS_IRQ_CLR, 2458 .irq_clr_shift = 9, 2459 .irq_status_shift = 9, 2460 }, 2461 [MT8195_AFE_IRQ_23] = { 2462 .id = MT8195_AFE_IRQ_23, 2463 .irq_cnt_reg = ASYS_IRQ11_CON, 2464 .irq_cnt_shift = 0, 2465 .irq_cnt_maskbit = 0xffffff, 2466 .irq_fs_reg = ASYS_IRQ11_CON, 2467 .irq_fs_shift = 24, 2468 .irq_fs_maskbit = 0x1ffff, 2469 .irq_en_reg = ASYS_IRQ11_CON, 2470 .irq_en_shift = 31, 2471 .irq_clr_reg = ASYS_IRQ_CLR, 2472 .irq_clr_shift = 10, 2473 .irq_status_shift = 10, 2474 }, 2475 [MT8195_AFE_IRQ_24] = { 2476 .id = MT8195_AFE_IRQ_24, 2477 .irq_cnt_reg = ASYS_IRQ12_CON, 2478 .irq_cnt_shift = 0, 2479 .irq_cnt_maskbit = 0xffffff, 2480 .irq_fs_reg = ASYS_IRQ12_CON, 2481 .irq_fs_shift = 24, 2482 .irq_fs_maskbit = 0x1ffff, 2483 .irq_en_reg = ASYS_IRQ12_CON, 2484 .irq_en_shift = 31, 2485 .irq_clr_reg = ASYS_IRQ_CLR, 2486 .irq_clr_shift = 11, 2487 .irq_status_shift = 11, 2488 }, 2489 [MT8195_AFE_IRQ_25] = { 2490 .id = MT8195_AFE_IRQ_25, 2491 .irq_cnt_reg = ASYS_IRQ13_CON, 2492 .irq_cnt_shift = 0, 2493 .irq_cnt_maskbit = 0xffffff, 2494 .irq_fs_reg = ASYS_IRQ13_CON, 2495 .irq_fs_shift = 24, 2496 .irq_fs_maskbit = 0x1ffff, 2497 .irq_en_reg = ASYS_IRQ13_CON, 2498 .irq_en_shift = 31, 2499 .irq_clr_reg = ASYS_IRQ_CLR, 2500 .irq_clr_shift = 12, 2501 .irq_status_shift = 12, 2502 }, 2503 [MT8195_AFE_IRQ_26] = { 2504 .id = MT8195_AFE_IRQ_26, 2505 .irq_cnt_reg = ASYS_IRQ14_CON, 2506 .irq_cnt_shift = 0, 2507 .irq_cnt_maskbit = 0xffffff, 2508 .irq_fs_reg = ASYS_IRQ14_CON, 2509 .irq_fs_shift = 24, 2510 .irq_fs_maskbit = 0x1ffff, 2511 .irq_en_reg = ASYS_IRQ14_CON, 2512 .irq_en_shift = 31, 2513 .irq_clr_reg = ASYS_IRQ_CLR, 2514 .irq_clr_shift = 13, 2515 .irq_status_shift = 13, 2516 }, 2517 [MT8195_AFE_IRQ_27] = { 2518 .id = MT8195_AFE_IRQ_27, 2519 .irq_cnt_reg = ASYS_IRQ15_CON, 2520 .irq_cnt_shift = 0, 2521 .irq_cnt_maskbit = 0xffffff, 2522 .irq_fs_reg = ASYS_IRQ15_CON, 2523 .irq_fs_shift = 24, 2524 .irq_fs_maskbit = 0x1ffff, 2525 .irq_en_reg = ASYS_IRQ15_CON, 2526 .irq_en_shift = 31, 2527 .irq_clr_reg = ASYS_IRQ_CLR, 2528 .irq_clr_shift = 14, 2529 .irq_status_shift = 14, 2530 }, 2531 [MT8195_AFE_IRQ_28] = { 2532 .id = MT8195_AFE_IRQ_28, 2533 .irq_cnt_reg = ASYS_IRQ16_CON, 2534 .irq_cnt_shift = 0, 2535 .irq_cnt_maskbit = 0xffffff, 2536 .irq_fs_reg = ASYS_IRQ16_CON, 2537 .irq_fs_shift = 24, 2538 .irq_fs_maskbit = 0x1ffff, 2539 .irq_en_reg = ASYS_IRQ16_CON, 2540 .irq_en_shift = 31, 2541 .irq_clr_reg = ASYS_IRQ_CLR, 2542 .irq_clr_shift = 15, 2543 .irq_status_shift = 15, 2544 }, 2545 }; 2546 2547 static const int mt8195_afe_memif_const_irqs[MT8195_AFE_MEMIF_NUM] = { 2548 [MT8195_AFE_MEMIF_DL2] = MT8195_AFE_IRQ_13, 2549 [MT8195_AFE_MEMIF_DL3] = MT8195_AFE_IRQ_14, 2550 [MT8195_AFE_MEMIF_DL6] = MT8195_AFE_IRQ_15, 2551 [MT8195_AFE_MEMIF_DL7] = MT8195_AFE_IRQ_1, 2552 [MT8195_AFE_MEMIF_DL8] = MT8195_AFE_IRQ_16, 2553 [MT8195_AFE_MEMIF_DL10] = MT8195_AFE_IRQ_17, 2554 [MT8195_AFE_MEMIF_DL11] = MT8195_AFE_IRQ_18, 2555 [MT8195_AFE_MEMIF_UL1] = MT8195_AFE_IRQ_3, 2556 [MT8195_AFE_MEMIF_UL2] = MT8195_AFE_IRQ_19, 2557 [MT8195_AFE_MEMIF_UL3] = MT8195_AFE_IRQ_20, 2558 [MT8195_AFE_MEMIF_UL4] = MT8195_AFE_IRQ_21, 2559 [MT8195_AFE_MEMIF_UL5] = MT8195_AFE_IRQ_22, 2560 [MT8195_AFE_MEMIF_UL6] = MT8195_AFE_IRQ_9, 2561 [MT8195_AFE_MEMIF_UL8] = MT8195_AFE_IRQ_23, 2562 [MT8195_AFE_MEMIF_UL9] = MT8195_AFE_IRQ_24, 2563 [MT8195_AFE_MEMIF_UL10] = MT8195_AFE_IRQ_25, 2564 }; 2565 2566 static bool mt8195_is_volatile_reg(struct device *dev, unsigned int reg) 2567 { 2568 /* these auto-gen reg has read-only bit, so put it as volatile */ 2569 /* volatile reg cannot be cached, so cannot be set when power off */ 2570 switch (reg) { 2571 case AUDIO_TOP_CON0: 2572 case AUDIO_TOP_CON1: 2573 case AUDIO_TOP_CON3: 2574 case AUDIO_TOP_CON4: 2575 case AUDIO_TOP_CON5: 2576 case AUDIO_TOP_CON6: 2577 case ASYS_IRQ_CLR: 2578 case ASYS_IRQ_STATUS: 2579 case ASYS_IRQ_MON1: 2580 case ASYS_IRQ_MON2: 2581 case AFE_IRQ_MCU_CLR: 2582 case AFE_IRQ_STATUS: 2583 case AFE_IRQ3_CON_MON: 2584 case AFE_IRQ_MCU_MON2: 2585 case ADSP_IRQ_STATUS: 2586 case AFE_APLL_TUNER_CFG: 2587 case AFE_APLL_TUNER_CFG1: 2588 case AUDIO_TOP_STA0: 2589 case AUDIO_TOP_STA1: 2590 case AFE_GAIN1_CUR: 2591 case AFE_GAIN2_CUR: 2592 case AFE_IEC_BURST_INFO: 2593 case AFE_IEC_CHL_STAT0: 2594 case AFE_IEC_CHL_STAT1: 2595 case AFE_IEC_CHR_STAT0: 2596 case AFE_IEC_CHR_STAT1: 2597 case AFE_SPDIFIN_CHSTS1: 2598 case AFE_SPDIFIN_CHSTS2: 2599 case AFE_SPDIFIN_CHSTS3: 2600 case AFE_SPDIFIN_CHSTS4: 2601 case AFE_SPDIFIN_CHSTS5: 2602 case AFE_SPDIFIN_CHSTS6: 2603 case AFE_SPDIFIN_DEBUG1: 2604 case AFE_SPDIFIN_DEBUG2: 2605 case AFE_SPDIFIN_DEBUG3: 2606 case AFE_SPDIFIN_DEBUG4: 2607 case AFE_SPDIFIN_EC: 2608 case AFE_SPDIFIN_CKLOCK_CFG: 2609 case AFE_SPDIFIN_BR_DBG1: 2610 case AFE_SPDIFIN_CKFBDIV: 2611 case AFE_SPDIFIN_INT_EXT: 2612 case AFE_SPDIFIN_INT_EXT2: 2613 case SPDIFIN_FREQ_STATUS: 2614 case SPDIFIN_USERCODE1: 2615 case SPDIFIN_USERCODE2: 2616 case SPDIFIN_USERCODE3: 2617 case SPDIFIN_USERCODE4: 2618 case SPDIFIN_USERCODE5: 2619 case SPDIFIN_USERCODE6: 2620 case SPDIFIN_USERCODE7: 2621 case SPDIFIN_USERCODE8: 2622 case SPDIFIN_USERCODE9: 2623 case SPDIFIN_USERCODE10: 2624 case SPDIFIN_USERCODE11: 2625 case SPDIFIN_USERCODE12: 2626 case AFE_SPDIFIN_APLL_TUNER_CFG: 2627 case AFE_LINEIN_APLL_TUNER_MON: 2628 case AFE_EARC_APLL_TUNER_MON: 2629 case AFE_CM0_MON: 2630 case AFE_CM1_MON: 2631 case AFE_CM2_MON: 2632 case AFE_MPHONE_MULTI_DET_MON0: 2633 case AFE_MPHONE_MULTI_DET_MON1: 2634 case AFE_MPHONE_MULTI_DET_MON2: 2635 case AFE_MPHONE_MULTI2_DET_MON0: 2636 case AFE_MPHONE_MULTI2_DET_MON1: 2637 case AFE_MPHONE_MULTI2_DET_MON2: 2638 case AFE_ADDA_MTKAIF_MON0: 2639 case AFE_ADDA_MTKAIF_MON1: 2640 case AFE_AUD_PAD_TOP: 2641 case AFE_ADDA6_MTKAIF_MON0: 2642 case AFE_ADDA6_MTKAIF_MON1: 2643 case AFE_ADDA6_SRC_DEBUG_MON0: 2644 case AFE_ADDA6_UL_SRC_MON0: 2645 case AFE_ADDA6_UL_SRC_MON1: 2646 case AFE_ASRC11_NEW_CON8: 2647 case AFE_ASRC11_NEW_CON9: 2648 case AFE_ASRC12_NEW_CON8: 2649 case AFE_ASRC12_NEW_CON9: 2650 case AFE_LRCK_CNT: 2651 case AFE_DAC_MON0: 2652 case AFE_DL2_CUR: 2653 case AFE_DL3_CUR: 2654 case AFE_DL6_CUR: 2655 case AFE_DL7_CUR: 2656 case AFE_DL8_CUR: 2657 case AFE_DL10_CUR: 2658 case AFE_DL11_CUR: 2659 case AFE_UL1_CUR: 2660 case AFE_UL2_CUR: 2661 case AFE_UL3_CUR: 2662 case AFE_UL4_CUR: 2663 case AFE_UL5_CUR: 2664 case AFE_UL6_CUR: 2665 case AFE_UL8_CUR: 2666 case AFE_UL9_CUR: 2667 case AFE_UL10_CUR: 2668 case AFE_DL8_CHK_SUM1: 2669 case AFE_DL8_CHK_SUM2: 2670 case AFE_DL8_CHK_SUM3: 2671 case AFE_DL8_CHK_SUM4: 2672 case AFE_DL8_CHK_SUM5: 2673 case AFE_DL8_CHK_SUM6: 2674 case AFE_DL10_CHK_SUM1: 2675 case AFE_DL10_CHK_SUM2: 2676 case AFE_DL10_CHK_SUM3: 2677 case AFE_DL10_CHK_SUM4: 2678 case AFE_DL10_CHK_SUM5: 2679 case AFE_DL10_CHK_SUM6: 2680 case AFE_DL11_CHK_SUM1: 2681 case AFE_DL11_CHK_SUM2: 2682 case AFE_DL11_CHK_SUM3: 2683 case AFE_DL11_CHK_SUM4: 2684 case AFE_DL11_CHK_SUM5: 2685 case AFE_DL11_CHK_SUM6: 2686 case AFE_UL1_CHK_SUM1: 2687 case AFE_UL1_CHK_SUM2: 2688 case AFE_UL2_CHK_SUM1: 2689 case AFE_UL2_CHK_SUM2: 2690 case AFE_UL3_CHK_SUM1: 2691 case AFE_UL3_CHK_SUM2: 2692 case AFE_UL4_CHK_SUM1: 2693 case AFE_UL4_CHK_SUM2: 2694 case AFE_UL5_CHK_SUM1: 2695 case AFE_UL5_CHK_SUM2: 2696 case AFE_UL6_CHK_SUM1: 2697 case AFE_UL6_CHK_SUM2: 2698 case AFE_UL8_CHK_SUM1: 2699 case AFE_UL8_CHK_SUM2: 2700 case AFE_DL2_CHK_SUM1: 2701 case AFE_DL2_CHK_SUM2: 2702 case AFE_DL3_CHK_SUM1: 2703 case AFE_DL3_CHK_SUM2: 2704 case AFE_DL6_CHK_SUM1: 2705 case AFE_DL6_CHK_SUM2: 2706 case AFE_DL7_CHK_SUM1: 2707 case AFE_DL7_CHK_SUM2: 2708 case AFE_UL9_CHK_SUM1: 2709 case AFE_UL9_CHK_SUM2: 2710 case AFE_BUS_MON1: 2711 case UL1_MOD2AGT_CNT_LAT: 2712 case UL2_MOD2AGT_CNT_LAT: 2713 case UL3_MOD2AGT_CNT_LAT: 2714 case UL4_MOD2AGT_CNT_LAT: 2715 case UL5_MOD2AGT_CNT_LAT: 2716 case UL6_MOD2AGT_CNT_LAT: 2717 case UL8_MOD2AGT_CNT_LAT: 2718 case UL9_MOD2AGT_CNT_LAT: 2719 case UL10_MOD2AGT_CNT_LAT: 2720 case AFE_MEMIF_BUF_FULL_MON: 2721 case AFE_MEMIF_BUF_MON1: 2722 case AFE_MEMIF_BUF_MON3: 2723 case AFE_MEMIF_BUF_MON4: 2724 case AFE_MEMIF_BUF_MON5: 2725 case AFE_MEMIF_BUF_MON6: 2726 case AFE_MEMIF_BUF_MON7: 2727 case AFE_MEMIF_BUF_MON8: 2728 case AFE_MEMIF_BUF_MON9: 2729 case AFE_MEMIF_BUF_MON10: 2730 case DL2_AGENT2MODULE_CNT: 2731 case DL3_AGENT2MODULE_CNT: 2732 case DL6_AGENT2MODULE_CNT: 2733 case DL7_AGENT2MODULE_CNT: 2734 case DL8_AGENT2MODULE_CNT: 2735 case DL10_AGENT2MODULE_CNT: 2736 case DL11_AGENT2MODULE_CNT: 2737 case UL1_MODULE2AGENT_CNT: 2738 case UL2_MODULE2AGENT_CNT: 2739 case UL3_MODULE2AGENT_CNT: 2740 case UL4_MODULE2AGENT_CNT: 2741 case UL5_MODULE2AGENT_CNT: 2742 case UL6_MODULE2AGENT_CNT: 2743 case UL8_MODULE2AGENT_CNT: 2744 case UL9_MODULE2AGENT_CNT: 2745 case UL10_MODULE2AGENT_CNT: 2746 case AFE_DMIC0_SRC_DEBUG_MON0: 2747 case AFE_DMIC0_UL_SRC_MON0: 2748 case AFE_DMIC0_UL_SRC_MON1: 2749 case AFE_DMIC1_SRC_DEBUG_MON0: 2750 case AFE_DMIC1_UL_SRC_MON0: 2751 case AFE_DMIC1_UL_SRC_MON1: 2752 case AFE_DMIC2_SRC_DEBUG_MON0: 2753 case AFE_DMIC2_UL_SRC_MON0: 2754 case AFE_DMIC2_UL_SRC_MON1: 2755 case AFE_DMIC3_SRC_DEBUG_MON0: 2756 case AFE_DMIC3_UL_SRC_MON0: 2757 case AFE_DMIC3_UL_SRC_MON1: 2758 case DMIC_GAIN1_CUR: 2759 case DMIC_GAIN2_CUR: 2760 case DMIC_GAIN3_CUR: 2761 case DMIC_GAIN4_CUR: 2762 case ETDM_IN1_MONITOR: 2763 case ETDM_IN2_MONITOR: 2764 case ETDM_OUT1_MONITOR: 2765 case ETDM_OUT2_MONITOR: 2766 case ETDM_OUT3_MONITOR: 2767 case AFE_ADDA_SRC_DEBUG_MON0: 2768 case AFE_ADDA_SRC_DEBUG_MON1: 2769 case AFE_ADDA_DL_SDM_FIFO_MON: 2770 case AFE_ADDA_DL_SRC_LCH_MON: 2771 case AFE_ADDA_DL_SRC_RCH_MON: 2772 case AFE_ADDA_DL_SDM_OUT_MON: 2773 case AFE_GASRC0_NEW_CON8: 2774 case AFE_GASRC0_NEW_CON9: 2775 case AFE_GASRC0_NEW_CON12: 2776 case AFE_GASRC1_NEW_CON8: 2777 case AFE_GASRC1_NEW_CON9: 2778 case AFE_GASRC1_NEW_CON12: 2779 case AFE_GASRC2_NEW_CON8: 2780 case AFE_GASRC2_NEW_CON9: 2781 case AFE_GASRC2_NEW_CON12: 2782 case AFE_GASRC3_NEW_CON8: 2783 case AFE_GASRC3_NEW_CON9: 2784 case AFE_GASRC3_NEW_CON12: 2785 case AFE_GASRC4_NEW_CON8: 2786 case AFE_GASRC4_NEW_CON9: 2787 case AFE_GASRC4_NEW_CON12: 2788 case AFE_GASRC5_NEW_CON8: 2789 case AFE_GASRC5_NEW_CON9: 2790 case AFE_GASRC5_NEW_CON12: 2791 case AFE_GASRC6_NEW_CON8: 2792 case AFE_GASRC6_NEW_CON9: 2793 case AFE_GASRC6_NEW_CON12: 2794 case AFE_GASRC7_NEW_CON8: 2795 case AFE_GASRC7_NEW_CON9: 2796 case AFE_GASRC7_NEW_CON12: 2797 case AFE_GASRC8_NEW_CON8: 2798 case AFE_GASRC8_NEW_CON9: 2799 case AFE_GASRC8_NEW_CON12: 2800 case AFE_GASRC9_NEW_CON8: 2801 case AFE_GASRC9_NEW_CON9: 2802 case AFE_GASRC9_NEW_CON12: 2803 case AFE_GASRC10_NEW_CON8: 2804 case AFE_GASRC10_NEW_CON9: 2805 case AFE_GASRC10_NEW_CON12: 2806 case AFE_GASRC11_NEW_CON8: 2807 case AFE_GASRC11_NEW_CON9: 2808 case AFE_GASRC11_NEW_CON12: 2809 case AFE_GASRC12_NEW_CON8: 2810 case AFE_GASRC12_NEW_CON9: 2811 case AFE_GASRC12_NEW_CON12: 2812 case AFE_GASRC13_NEW_CON8: 2813 case AFE_GASRC13_NEW_CON9: 2814 case AFE_GASRC13_NEW_CON12: 2815 case AFE_GASRC14_NEW_CON8: 2816 case AFE_GASRC14_NEW_CON9: 2817 case AFE_GASRC14_NEW_CON12: 2818 case AFE_GASRC15_NEW_CON8: 2819 case AFE_GASRC15_NEW_CON9: 2820 case AFE_GASRC15_NEW_CON12: 2821 case AFE_GASRC16_NEW_CON8: 2822 case AFE_GASRC16_NEW_CON9: 2823 case AFE_GASRC16_NEW_CON12: 2824 case AFE_GASRC17_NEW_CON8: 2825 case AFE_GASRC17_NEW_CON9: 2826 case AFE_GASRC17_NEW_CON12: 2827 case AFE_GASRC18_NEW_CON8: 2828 case AFE_GASRC18_NEW_CON9: 2829 case AFE_GASRC18_NEW_CON12: 2830 case AFE_GASRC19_NEW_CON8: 2831 case AFE_GASRC19_NEW_CON9: 2832 case AFE_GASRC19_NEW_CON12: 2833 return true; 2834 default: 2835 return false; 2836 }; 2837 } 2838 2839 static const struct regmap_config mt8195_afe_regmap_config = { 2840 .reg_bits = 32, 2841 .reg_stride = 4, 2842 .val_bits = 32, 2843 .volatile_reg = mt8195_is_volatile_reg, 2844 .max_register = AFE_MAX_REGISTER, 2845 .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1), 2846 .cache_type = REGCACHE_FLAT, 2847 }; 2848 2849 #define AFE_IRQ_CLR_BITS (0x387) 2850 #define ASYS_IRQ_CLR_BITS (0xffff) 2851 2852 static irqreturn_t mt8195_afe_irq_handler(int irq_id, void *dev_id) 2853 { 2854 struct mtk_base_afe *afe = dev_id; 2855 unsigned int val = 0; 2856 unsigned int asys_irq_clr_bits = 0; 2857 unsigned int afe_irq_clr_bits = 0; 2858 unsigned int irq_status_bits = 0; 2859 unsigned int irq_clr_bits = 0; 2860 unsigned int mcu_irq_mask = 0; 2861 int i = 0; 2862 int ret = 0; 2863 2864 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val); 2865 if (ret) { 2866 dev_info(afe->dev, "%s irq status err\n", __func__); 2867 afe_irq_clr_bits = AFE_IRQ_CLR_BITS; 2868 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS; 2869 goto err_irq; 2870 } 2871 2872 ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask); 2873 if (ret) { 2874 dev_info(afe->dev, "%s read irq mask err\n", __func__); 2875 afe_irq_clr_bits = AFE_IRQ_CLR_BITS; 2876 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS; 2877 goto err_irq; 2878 } 2879 2880 /* only clr cpu irq */ 2881 val &= mcu_irq_mask; 2882 2883 for (i = 0; i < MT8195_AFE_MEMIF_NUM; i++) { 2884 struct mtk_base_afe_memif *memif = &afe->memif[i]; 2885 struct mtk_base_irq_data const *irq_data; 2886 2887 if (memif->irq_usage < 0) 2888 continue; 2889 2890 irq_data = afe->irqs[memif->irq_usage].irq_data; 2891 2892 irq_status_bits = BIT(irq_data->irq_status_shift); 2893 irq_clr_bits = BIT(irq_data->irq_clr_shift); 2894 2895 if (!(val & irq_status_bits)) 2896 continue; 2897 2898 if (irq_data->irq_clr_reg == ASYS_IRQ_CLR) 2899 asys_irq_clr_bits |= irq_clr_bits; 2900 else 2901 afe_irq_clr_bits |= irq_clr_bits; 2902 2903 snd_pcm_period_elapsed(memif->substream); 2904 } 2905 2906 err_irq: 2907 /* clear irq */ 2908 if (asys_irq_clr_bits) 2909 regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits); 2910 if (afe_irq_clr_bits) 2911 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits); 2912 2913 return IRQ_HANDLED; 2914 } 2915 2916 static int mt8195_afe_runtime_suspend(struct device *dev) 2917 { 2918 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2919 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2920 2921 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2922 goto skip_regmap; 2923 2924 mt8195_afe_disable_main_clock(afe); 2925 2926 regcache_cache_only(afe->regmap, true); 2927 regcache_mark_dirty(afe->regmap); 2928 2929 skip_regmap: 2930 mt8195_afe_disable_reg_rw_clk(afe); 2931 2932 return 0; 2933 } 2934 2935 static int mt8195_afe_runtime_resume(struct device *dev) 2936 { 2937 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2938 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2939 2940 mt8195_afe_enable_reg_rw_clk(afe); 2941 2942 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2943 goto skip_regmap; 2944 2945 regcache_cache_only(afe->regmap, false); 2946 regcache_sync(afe->regmap); 2947 2948 mt8195_afe_enable_main_clock(afe); 2949 skip_regmap: 2950 return 0; 2951 } 2952 2953 static int mt8195_afe_component_probe(struct snd_soc_component *component) 2954 { 2955 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 2956 int ret = 0; 2957 2958 snd_soc_component_init_regmap(component, afe->regmap); 2959 2960 ret = mtk_afe_add_sub_dai_control(component); 2961 2962 return ret; 2963 } 2964 2965 static const struct snd_soc_component_driver mt8195_afe_component = { 2966 .name = AFE_PCM_NAME, 2967 .pointer = mtk_afe_pcm_pointer, 2968 .pcm_construct = mtk_afe_pcm_new, 2969 .probe = mt8195_afe_component_probe, 2970 }; 2971 2972 static int init_memif_priv_data(struct mtk_base_afe *afe) 2973 { 2974 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2975 struct mtk_dai_memif_priv *memif_priv; 2976 int i; 2977 2978 for (i = MT8195_AFE_MEMIF_START; i < MT8195_AFE_MEMIF_END; i++) { 2979 memif_priv = devm_kzalloc(afe->dev, 2980 sizeof(struct mtk_dai_memif_priv), 2981 GFP_KERNEL); 2982 if (!memif_priv) 2983 return -ENOMEM; 2984 2985 afe_priv->dai_priv[i] = memif_priv; 2986 } 2987 2988 return 0; 2989 } 2990 2991 static int mt8195_dai_memif_register(struct mtk_base_afe *afe) 2992 { 2993 struct mtk_base_afe_dai *dai; 2994 2995 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2996 if (!dai) 2997 return -ENOMEM; 2998 2999 list_add(&dai->list, &afe->sub_dais); 3000 3001 dai->dai_drivers = mt8195_memif_dai_driver; 3002 dai->num_dai_drivers = ARRAY_SIZE(mt8195_memif_dai_driver); 3003 3004 dai->dapm_widgets = mt8195_memif_widgets; 3005 dai->num_dapm_widgets = ARRAY_SIZE(mt8195_memif_widgets); 3006 dai->dapm_routes = mt8195_memif_routes; 3007 dai->num_dapm_routes = ARRAY_SIZE(mt8195_memif_routes); 3008 dai->controls = mt8195_memif_controls; 3009 dai->num_controls = ARRAY_SIZE(mt8195_memif_controls); 3010 3011 return init_memif_priv_data(afe); 3012 } 3013 3014 typedef int (*dai_register_cb)(struct mtk_base_afe *); 3015 static const dai_register_cb dai_register_cbs[] = { 3016 mt8195_dai_adda_register, 3017 mt8195_dai_etdm_register, 3018 mt8195_dai_pcm_register, 3019 mt8195_dai_memif_register, 3020 }; 3021 3022 static const struct reg_sequence mt8195_afe_reg_defaults[] = { 3023 { AFE_IRQ_MASK, 0x387ffff }, 3024 { AFE_IRQ3_CON, BIT(30) }, 3025 { AFE_IRQ9_CON, BIT(30) }, 3026 { ETDM_IN1_CON4, 0x12000100 }, 3027 { ETDM_IN2_CON4, 0x12000100 }, 3028 }; 3029 3030 static const struct reg_sequence mt8195_cg_patch[] = { 3031 { AUDIO_TOP_CON0, 0xfffffffb }, 3032 { AUDIO_TOP_CON1, 0xfffffff8 }, 3033 }; 3034 3035 static int mt8195_afe_init_registers(struct mtk_base_afe *afe) 3036 { 3037 return regmap_multi_reg_write(afe->regmap, 3038 mt8195_afe_reg_defaults, 3039 ARRAY_SIZE(mt8195_afe_reg_defaults)); 3040 } 3041 3042 static void mt8195_afe_parse_of(struct mtk_base_afe *afe, 3043 struct device_node *np) 3044 { 3045 #if IS_ENABLED(CONFIG_SND_SOC_MT6359) 3046 struct mt8195_afe_private *afe_priv = afe->platform_priv; 3047 3048 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(afe->dev->of_node, 3049 "mediatek,topckgen"); 3050 if (IS_ERR(afe_priv->topckgen)) { 3051 dev_info(afe->dev, "%s() Cannot find topckgen controller: %ld\n", 3052 __func__, PTR_ERR(afe_priv->topckgen)); 3053 } 3054 #endif 3055 } 3056 3057 static int mt8195_afe_pcm_dev_probe(struct platform_device *pdev) 3058 { 3059 struct mtk_base_afe *afe; 3060 struct mt8195_afe_private *afe_priv; 3061 struct device *dev = &pdev->dev; 3062 int i, irq_id, ret; 3063 struct snd_soc_component *component; 3064 3065 ret = of_reserved_mem_device_init(dev); 3066 if (ret) { 3067 dev_err(dev, "failed to assign memory region: %d\n", ret); 3068 return ret; 3069 } 3070 3071 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(33)); 3072 if (ret) 3073 return ret; 3074 3075 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 3076 if (!afe) 3077 return -ENOMEM; 3078 3079 afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), 3080 GFP_KERNEL); 3081 if (!afe->platform_priv) 3082 return -ENOMEM; 3083 3084 afe_priv = afe->platform_priv; 3085 afe->dev = &pdev->dev; 3086 3087 afe->base_addr = devm_platform_ioremap_resource(pdev, 0); 3088 if (IS_ERR(afe->base_addr)) 3089 return PTR_ERR(afe->base_addr); 3090 3091 /* initial audio related clock */ 3092 ret = mt8195_afe_init_clock(afe); 3093 if (ret) { 3094 dev_err(dev, "init clock error\n"); 3095 return ret; 3096 } 3097 3098 spin_lock_init(&afe_priv->afe_ctrl_lock); 3099 3100 mutex_init(&afe->irq_alloc_lock); 3101 3102 /* irq initialize */ 3103 afe->irqs_size = MT8195_AFE_IRQ_NUM; 3104 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 3105 GFP_KERNEL); 3106 if (!afe->irqs) 3107 return -ENOMEM; 3108 3109 for (i = 0; i < afe->irqs_size; i++) 3110 afe->irqs[i].irq_data = &irq_data_array[i]; 3111 3112 /* init memif */ 3113 afe->memif_size = MT8195_AFE_MEMIF_NUM; 3114 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 3115 GFP_KERNEL); 3116 if (!afe->memif) 3117 return -ENOMEM; 3118 3119 for (i = 0; i < afe->memif_size; i++) { 3120 afe->memif[i].data = &memif_data[i]; 3121 afe->memif[i].irq_usage = mt8195_afe_memif_const_irqs[i]; 3122 afe->memif[i].const_irq = 1; 3123 afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true; 3124 } 3125 3126 /* request irq */ 3127 irq_id = platform_get_irq(pdev, 0); 3128 if (irq_id < 0) { 3129 dev_err(dev, "%s no irq found\n", dev->of_node->name); 3130 return -ENXIO; 3131 } 3132 3133 ret = devm_request_irq(dev, irq_id, mt8195_afe_irq_handler, 3134 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); 3135 if (ret) { 3136 dev_err(dev, "could not request_irq for asys-isr\n"); 3137 return ret; 3138 } 3139 3140 /* init sub_dais */ 3141 INIT_LIST_HEAD(&afe->sub_dais); 3142 3143 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 3144 ret = dai_register_cbs[i](afe); 3145 if (ret) { 3146 dev_warn(dev, "dai register i %d fail, ret %d\n", 3147 i, ret); 3148 return ret; 3149 } 3150 } 3151 3152 /* init dai_driver and component_driver */ 3153 ret = mtk_afe_combine_sub_dai(afe); 3154 if (ret) { 3155 dev_warn(dev, "mtk_afe_combine_sub_dai fail, ret %d\n", 3156 ret); 3157 return ret; 3158 } 3159 3160 afe->mtk_afe_hardware = &mt8195_afe_hardware; 3161 afe->memif_fs = mt8195_memif_fs; 3162 afe->irq_fs = mt8195_irq_fs; 3163 3164 afe->runtime_resume = mt8195_afe_runtime_resume; 3165 afe->runtime_suspend = mt8195_afe_runtime_suspend; 3166 3167 platform_set_drvdata(pdev, afe); 3168 3169 mt8195_afe_parse_of(afe, pdev->dev.of_node); 3170 3171 pm_runtime_enable(dev); 3172 if (!pm_runtime_enabled(dev)) { 3173 ret = mt8195_afe_runtime_resume(dev); 3174 if (ret) 3175 return ret; 3176 } 3177 3178 /* enable clock for regcache get default value from hw */ 3179 afe_priv->pm_runtime_bypass_reg_ctl = true; 3180 pm_runtime_get_sync(dev); 3181 3182 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, 3183 &mt8195_afe_regmap_config); 3184 if (IS_ERR(afe->regmap)) { 3185 ret = PTR_ERR(afe->regmap); 3186 goto err_pm_put; 3187 } 3188 3189 ret = regmap_register_patch(afe->regmap, mt8195_cg_patch, 3190 ARRAY_SIZE(mt8195_cg_patch)); 3191 if (ret < 0) { 3192 dev_err(dev, "Failed to apply cg patch\n"); 3193 goto err_pm_put; 3194 } 3195 3196 /* register component */ 3197 ret = devm_snd_soc_register_component(dev, &mt8195_afe_component, 3198 NULL, 0); 3199 if (ret) { 3200 dev_warn(dev, "err_platform\n"); 3201 goto err_pm_put; 3202 } 3203 3204 component = devm_kzalloc(dev, sizeof(*component), GFP_KERNEL); 3205 if (!component) { 3206 ret = -ENOMEM; 3207 goto err_pm_put; 3208 } 3209 3210 ret = snd_soc_component_initialize(component, 3211 &mt8195_afe_pcm_dai_component, 3212 dev); 3213 if (ret) 3214 goto err_pm_put; 3215 3216 #ifdef CONFIG_DEBUG_FS 3217 component->debugfs_prefix = "pcm"; 3218 #endif 3219 3220 ret = snd_soc_add_component(component, 3221 afe->dai_drivers, 3222 afe->num_dai_drivers); 3223 if (ret) { 3224 dev_warn(dev, "err_dai_component\n"); 3225 goto err_pm_put; 3226 } 3227 3228 mt8195_afe_init_registers(afe); 3229 3230 pm_runtime_put_sync(dev); 3231 afe_priv->pm_runtime_bypass_reg_ctl = false; 3232 3233 regcache_cache_only(afe->regmap, true); 3234 regcache_mark_dirty(afe->regmap); 3235 3236 return 0; 3237 3238 err_pm_put: 3239 pm_runtime_put_sync(dev); 3240 pm_runtime_disable(dev); 3241 3242 return ret; 3243 } 3244 3245 static int mt8195_afe_pcm_dev_remove(struct platform_device *pdev) 3246 { 3247 struct mtk_base_afe *afe = platform_get_drvdata(pdev); 3248 3249 snd_soc_unregister_component(&pdev->dev); 3250 3251 pm_runtime_disable(&pdev->dev); 3252 if (!pm_runtime_status_suspended(&pdev->dev)) 3253 mt8195_afe_runtime_suspend(&pdev->dev); 3254 3255 mt8195_afe_deinit_clock(afe); 3256 return 0; 3257 } 3258 3259 static const struct of_device_id mt8195_afe_pcm_dt_match[] = { 3260 {.compatible = "mediatek,mt8195-audio", }, 3261 {}, 3262 }; 3263 MODULE_DEVICE_TABLE(of, mt8195_afe_pcm_dt_match); 3264 3265 static const struct dev_pm_ops mt8195_afe_pm_ops = { 3266 SET_RUNTIME_PM_OPS(mt8195_afe_runtime_suspend, 3267 mt8195_afe_runtime_resume, NULL) 3268 }; 3269 3270 static struct platform_driver mt8195_afe_pcm_driver = { 3271 .driver = { 3272 .name = "mt8195-audio", 3273 .of_match_table = mt8195_afe_pcm_dt_match, 3274 .pm = &mt8195_afe_pm_ops, 3275 }, 3276 .probe = mt8195_afe_pcm_dev_probe, 3277 .remove = mt8195_afe_pcm_dev_remove, 3278 }; 3279 3280 module_platform_driver(mt8195_afe_pcm_driver); 3281 3282 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8195"); 3283 MODULE_AUTHOR("Bicycle Tsai <bicycle.tsai@mediatek.com>"); 3284 MODULE_LICENSE("GPL v2"); 3285