1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mediatek ALSA SoC AFE platform driver for 8195 4 * 5 * Copyright (c) 2021 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_platform.h> 17 #include <linux/pm_runtime.h> 18 #include "mt8195-afe-common.h" 19 #include "mt8195-afe-clk.h" 20 #include "mt8195-reg.h" 21 #include "../common/mtk-afe-platform-driver.h" 22 #include "../common/mtk-afe-fe-dai.h" 23 24 #define MT8195_MEMIF_BUFFER_BYTES_ALIGN (0x40) 25 #define MT8195_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff) 26 27 struct mtk_dai_memif_priv { 28 unsigned int asys_timing_sel; 29 }; 30 31 static const struct snd_pcm_hardware mt8195_afe_hardware = { 32 .info = SNDRV_PCM_INFO_MMAP | 33 SNDRV_PCM_INFO_INTERLEAVED | 34 SNDRV_PCM_INFO_MMAP_VALID, 35 .formats = SNDRV_PCM_FMTBIT_S16_LE | 36 SNDRV_PCM_FMTBIT_S24_LE | 37 SNDRV_PCM_FMTBIT_S32_LE, 38 .period_bytes_min = 64, 39 .period_bytes_max = 256 * 1024, 40 .periods_min = 2, 41 .periods_max = 256, 42 .buffer_bytes_max = 256 * 2 * 1024, 43 }; 44 45 struct mt8195_afe_rate { 46 unsigned int rate; 47 unsigned int reg_value; 48 }; 49 50 static const struct mt8195_afe_rate mt8195_afe_rates[] = { 51 { .rate = 8000, .reg_value = 0, }, 52 { .rate = 12000, .reg_value = 1, }, 53 { .rate = 16000, .reg_value = 2, }, 54 { .rate = 24000, .reg_value = 3, }, 55 { .rate = 32000, .reg_value = 4, }, 56 { .rate = 48000, .reg_value = 5, }, 57 { .rate = 96000, .reg_value = 6, }, 58 { .rate = 192000, .reg_value = 7, }, 59 { .rate = 384000, .reg_value = 8, }, 60 { .rate = 7350, .reg_value = 16, }, 61 { .rate = 11025, .reg_value = 17, }, 62 { .rate = 14700, .reg_value = 18, }, 63 { .rate = 22050, .reg_value = 19, }, 64 { .rate = 29400, .reg_value = 20, }, 65 { .rate = 44100, .reg_value = 21, }, 66 { .rate = 88200, .reg_value = 22, }, 67 { .rate = 176400, .reg_value = 23, }, 68 { .rate = 352800, .reg_value = 24, }, 69 }; 70 71 int mt8195_afe_fs_timing(unsigned int rate) 72 { 73 int i; 74 75 for (i = 0; i < ARRAY_SIZE(mt8195_afe_rates); i++) 76 if (mt8195_afe_rates[i].rate == rate) 77 return mt8195_afe_rates[i].reg_value; 78 79 return -EINVAL; 80 } 81 82 static int mt8195_memif_fs(struct snd_pcm_substream *substream, 83 unsigned int rate) 84 { 85 struct snd_soc_pcm_runtime *rtd = substream->private_data; 86 struct snd_soc_component *component = 87 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 88 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 89 int id = asoc_rtd_to_cpu(rtd, 0)->id; 90 struct mtk_base_afe_memif *memif = &afe->memif[id]; 91 int fs = mt8195_afe_fs_timing(rate); 92 93 switch (memif->data->id) { 94 case MT8195_AFE_MEMIF_DL10: 95 fs = MT8195_ETDM_OUT3_1X_EN; 96 break; 97 case MT8195_AFE_MEMIF_UL8: 98 fs = MT8195_ETDM_IN1_NX_EN; 99 break; 100 case MT8195_AFE_MEMIF_UL3: 101 fs = MT8195_ETDM_IN2_NX_EN; 102 break; 103 default: 104 break; 105 } 106 107 return fs; 108 } 109 110 static int mt8195_irq_fs(struct snd_pcm_substream *substream, 111 unsigned int rate) 112 { 113 int fs = mt8195_memif_fs(substream, rate); 114 115 switch (fs) { 116 case MT8195_ETDM_IN1_NX_EN: 117 fs = MT8195_ETDM_IN1_1X_EN; 118 break; 119 case MT8195_ETDM_IN2_NX_EN: 120 fs = MT8195_ETDM_IN2_1X_EN; 121 break; 122 default: 123 break; 124 } 125 126 return fs; 127 } 128 129 enum { 130 MT8195_AFE_CM0, 131 MT8195_AFE_CM1, 132 MT8195_AFE_CM2, 133 MT8195_AFE_CM_NUM, 134 }; 135 136 struct mt8195_afe_channel_merge { 137 int id; 138 int reg; 139 unsigned int sel_shift; 140 unsigned int sel_maskbit; 141 unsigned int sel_default; 142 unsigned int ch_num_shift; 143 unsigned int ch_num_maskbit; 144 unsigned int en_shift; 145 unsigned int en_maskbit; 146 unsigned int update_cnt_shift; 147 unsigned int update_cnt_maskbit; 148 unsigned int update_cnt_default; 149 }; 150 151 static const struct mt8195_afe_channel_merge 152 mt8195_afe_cm[MT8195_AFE_CM_NUM] = { 153 [MT8195_AFE_CM0] = { 154 .id = MT8195_AFE_CM0, 155 .reg = AFE_CM0_CON, 156 .sel_shift = 30, 157 .sel_maskbit = 0x1, 158 .sel_default = 1, 159 .ch_num_shift = 2, 160 .ch_num_maskbit = 0x3f, 161 .en_shift = 0, 162 .en_maskbit = 0x1, 163 .update_cnt_shift = 16, 164 .update_cnt_maskbit = 0x1fff, 165 .update_cnt_default = 0x3, 166 }, 167 [MT8195_AFE_CM1] = { 168 .id = MT8195_AFE_CM1, 169 .reg = AFE_CM1_CON, 170 .sel_shift = 30, 171 .sel_maskbit = 0x1, 172 .sel_default = 1, 173 .ch_num_shift = 2, 174 .ch_num_maskbit = 0x1f, 175 .en_shift = 0, 176 .en_maskbit = 0x1, 177 .update_cnt_shift = 16, 178 .update_cnt_maskbit = 0x1fff, 179 .update_cnt_default = 0x3, 180 }, 181 [MT8195_AFE_CM2] = { 182 .id = MT8195_AFE_CM2, 183 .reg = AFE_CM2_CON, 184 .sel_shift = 30, 185 .sel_maskbit = 0x1, 186 .sel_default = 1, 187 .ch_num_shift = 2, 188 .ch_num_maskbit = 0x1f, 189 .en_shift = 0, 190 .en_maskbit = 0x1, 191 .update_cnt_shift = 16, 192 .update_cnt_maskbit = 0x1fff, 193 .update_cnt_default = 0x3, 194 }, 195 }; 196 197 static int mt8195_afe_memif_is_ul(int id) 198 { 199 if (id >= MT8195_AFE_MEMIF_UL_START && id < MT8195_AFE_MEMIF_END) 200 return 1; 201 else 202 return 0; 203 } 204 205 static const struct mt8195_afe_channel_merge* 206 mt8195_afe_found_cm(struct snd_soc_dai *dai) 207 { 208 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 209 int id = -EINVAL; 210 211 if (mt8195_afe_memif_is_ul(dai->id) == 0) 212 return NULL; 213 214 switch (dai->id) { 215 case MT8195_AFE_MEMIF_UL9: 216 id = MT8195_AFE_CM0; 217 break; 218 case MT8195_AFE_MEMIF_UL2: 219 id = MT8195_AFE_CM1; 220 break; 221 case MT8195_AFE_MEMIF_UL10: 222 id = MT8195_AFE_CM2; 223 break; 224 default: 225 break; 226 } 227 228 if (id < 0) { 229 dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n", 230 __func__, dai->id); 231 return NULL; 232 } 233 234 return &mt8195_afe_cm[id]; 235 } 236 237 static int mt8195_afe_config_cm(struct mtk_base_afe *afe, 238 const struct mt8195_afe_channel_merge *cm, 239 unsigned int channels) 240 { 241 if (!cm) 242 return -EINVAL; 243 244 regmap_update_bits(afe->regmap, 245 cm->reg, 246 cm->sel_maskbit << cm->sel_shift, 247 cm->sel_default << cm->sel_shift); 248 249 regmap_update_bits(afe->regmap, 250 cm->reg, 251 cm->ch_num_maskbit << cm->ch_num_shift, 252 (channels - 1) << cm->ch_num_shift); 253 254 regmap_update_bits(afe->regmap, 255 cm->reg, 256 cm->update_cnt_maskbit << cm->update_cnt_shift, 257 cm->update_cnt_default << cm->update_cnt_shift); 258 259 return 0; 260 } 261 262 static int mt8195_afe_enable_cm(struct mtk_base_afe *afe, 263 const struct mt8195_afe_channel_merge *cm, 264 bool enable) 265 { 266 if (!cm) 267 return -EINVAL; 268 269 regmap_update_bits(afe->regmap, 270 cm->reg, 271 cm->en_maskbit << cm->en_shift, 272 enable << cm->en_shift); 273 274 return 0; 275 } 276 277 static int 278 mt8195_afe_paired_memif_clk_prepare(struct snd_pcm_substream *substream, 279 struct snd_soc_dai *dai, 280 int enable) 281 { 282 struct snd_soc_pcm_runtime *rtd = substream->private_data; 283 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 284 struct mt8195_afe_private *afe_priv = afe->platform_priv; 285 int id = asoc_rtd_to_cpu(rtd, 0)->id; 286 int clk_id; 287 288 if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10) 289 return 0; 290 291 if (enable) { 292 clk_id = MT8195_CLK_AUD_MEMIF_DL10; 293 mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]); 294 clk_id = MT8195_CLK_AUD_MEMIF_DL8; 295 mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]); 296 } else { 297 clk_id = MT8195_CLK_AUD_MEMIF_DL8; 298 mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]); 299 clk_id = MT8195_CLK_AUD_MEMIF_DL10; 300 mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]); 301 } 302 303 return 0; 304 } 305 306 static int 307 mt8195_afe_paired_memif_clk_enable(struct snd_pcm_substream *substream, 308 struct snd_soc_dai *dai, 309 int enable) 310 { 311 struct snd_soc_pcm_runtime *rtd = substream->private_data; 312 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 313 struct mt8195_afe_private *afe_priv = afe->platform_priv; 314 int id = asoc_rtd_to_cpu(rtd, 0)->id; 315 int clk_id; 316 317 if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10) 318 return 0; 319 320 if (enable) { 321 /* DL8_DL10_MEM */ 322 clk_id = MT8195_CLK_AUD_MEMIF_DL10; 323 mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]); 324 udelay(1); 325 /* DL8_DL10_AGENT */ 326 clk_id = MT8195_CLK_AUD_MEMIF_DL8; 327 mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]); 328 } else { 329 /* DL8_DL10_AGENT */ 330 clk_id = MT8195_CLK_AUD_MEMIF_DL8; 331 mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]); 332 /* DL8_DL10_MEM */ 333 clk_id = MT8195_CLK_AUD_MEMIF_DL10; 334 mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]); 335 } 336 337 return 0; 338 } 339 340 static int mt8195_afe_fe_startup(struct snd_pcm_substream *substream, 341 struct snd_soc_dai *dai) 342 { 343 struct snd_soc_pcm_runtime *rtd = substream->private_data; 344 struct snd_pcm_runtime *runtime = substream->runtime; 345 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 346 int id = asoc_rtd_to_cpu(rtd, 0)->id; 347 int ret = 0; 348 349 mt8195_afe_paired_memif_clk_prepare(substream, dai, 1); 350 351 ret = mtk_afe_fe_startup(substream, dai); 352 353 snd_pcm_hw_constraint_step(runtime, 0, 354 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 355 MT8195_MEMIF_BUFFER_BYTES_ALIGN); 356 357 if (id != MT8195_AFE_MEMIF_DL7) 358 goto out; 359 360 ret = snd_pcm_hw_constraint_minmax(runtime, 361 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 362 1, 363 MT8195_MEMIF_DL7_MAX_PERIOD_SIZE); 364 if (ret < 0) 365 dev_dbg(afe->dev, "hw_constraint_minmax failed\n"); 366 out: 367 return ret; 368 } 369 370 static void mt8195_afe_fe_shutdown(struct snd_pcm_substream *substream, 371 struct snd_soc_dai *dai) 372 { 373 mtk_afe_fe_shutdown(substream, dai); 374 mt8195_afe_paired_memif_clk_prepare(substream, dai, 0); 375 } 376 377 static int mt8195_afe_fe_hw_params(struct snd_pcm_substream *substream, 378 struct snd_pcm_hw_params *params, 379 struct snd_soc_dai *dai) 380 { 381 struct snd_soc_pcm_runtime *rtd = substream->private_data; 382 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 383 int id = asoc_rtd_to_cpu(rtd, 0)->id; 384 struct mtk_base_afe_memif *memif = &afe->memif[id]; 385 const struct mtk_base_memif_data *data = memif->data; 386 const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai); 387 unsigned int ch_num = params_channels(params); 388 389 mt8195_afe_config_cm(afe, cm, params_channels(params)); 390 391 if (data->ch_num_reg >= 0) { 392 regmap_update_bits(afe->regmap, data->ch_num_reg, 393 data->ch_num_maskbit << data->ch_num_shift, 394 ch_num << data->ch_num_shift); 395 } 396 397 return mtk_afe_fe_hw_params(substream, params, dai); 398 } 399 400 static int mt8195_afe_fe_hw_free(struct snd_pcm_substream *substream, 401 struct snd_soc_dai *dai) 402 { 403 return mtk_afe_fe_hw_free(substream, dai); 404 } 405 406 static int mt8195_afe_fe_prepare(struct snd_pcm_substream *substream, 407 struct snd_soc_dai *dai) 408 { 409 return mtk_afe_fe_prepare(substream, dai); 410 } 411 412 static int mt8195_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd, 413 struct snd_soc_dai *dai) 414 { 415 int ret = 0; 416 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 417 const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai); 418 419 switch (cmd) { 420 case SNDRV_PCM_TRIGGER_START: 421 case SNDRV_PCM_TRIGGER_RESUME: 422 mt8195_afe_enable_cm(afe, cm, true); 423 break; 424 case SNDRV_PCM_TRIGGER_STOP: 425 case SNDRV_PCM_TRIGGER_SUSPEND: 426 mt8195_afe_enable_cm(afe, cm, false); 427 break; 428 default: 429 break; 430 } 431 432 ret = mtk_afe_fe_trigger(substream, cmd, dai); 433 434 switch (cmd) { 435 case SNDRV_PCM_TRIGGER_START: 436 case SNDRV_PCM_TRIGGER_RESUME: 437 mt8195_afe_paired_memif_clk_enable(substream, dai, 1); 438 break; 439 case SNDRV_PCM_TRIGGER_STOP: 440 case SNDRV_PCM_TRIGGER_SUSPEND: 441 mt8195_afe_paired_memif_clk_enable(substream, dai, 0); 442 break; 443 default: 444 break; 445 } 446 447 return ret; 448 } 449 450 static int mt8195_afe_fe_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 451 { 452 return 0; 453 } 454 455 static const struct snd_soc_dai_ops mt8195_afe_fe_dai_ops = { 456 .startup = mt8195_afe_fe_startup, 457 .shutdown = mt8195_afe_fe_shutdown, 458 .hw_params = mt8195_afe_fe_hw_params, 459 .hw_free = mt8195_afe_fe_hw_free, 460 .prepare = mt8195_afe_fe_prepare, 461 .trigger = mt8195_afe_fe_trigger, 462 .set_fmt = mt8195_afe_fe_set_fmt, 463 }; 464 465 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 466 SNDRV_PCM_RATE_88200 |\ 467 SNDRV_PCM_RATE_96000 |\ 468 SNDRV_PCM_RATE_176400 |\ 469 SNDRV_PCM_RATE_192000 |\ 470 SNDRV_PCM_RATE_352800 |\ 471 SNDRV_PCM_RATE_384000) 472 473 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 474 SNDRV_PCM_FMTBIT_S24_LE |\ 475 SNDRV_PCM_FMTBIT_S32_LE) 476 477 static struct snd_soc_dai_driver mt8195_memif_dai_driver[] = { 478 /* FE DAIs: memory intefaces to CPU */ 479 { 480 .name = "DL2", 481 .id = MT8195_AFE_MEMIF_DL2, 482 .playback = { 483 .stream_name = "DL2", 484 .channels_min = 1, 485 .channels_max = 2, 486 .rates = MTK_PCM_RATES, 487 .formats = MTK_PCM_FORMATS, 488 }, 489 .ops = &mt8195_afe_fe_dai_ops, 490 }, 491 { 492 .name = "DL3", 493 .id = MT8195_AFE_MEMIF_DL3, 494 .playback = { 495 .stream_name = "DL3", 496 .channels_min = 1, 497 .channels_max = 2, 498 .rates = MTK_PCM_RATES, 499 .formats = MTK_PCM_FORMATS, 500 }, 501 .ops = &mt8195_afe_fe_dai_ops, 502 }, 503 { 504 .name = "DL6", 505 .id = MT8195_AFE_MEMIF_DL6, 506 .playback = { 507 .stream_name = "DL6", 508 .channels_min = 1, 509 .channels_max = 2, 510 .rates = MTK_PCM_RATES, 511 .formats = MTK_PCM_FORMATS, 512 }, 513 .ops = &mt8195_afe_fe_dai_ops, 514 }, 515 { 516 .name = "DL7", 517 .id = MT8195_AFE_MEMIF_DL7, 518 .playback = { 519 .stream_name = "DL7", 520 .channels_min = 1, 521 .channels_max = 2, 522 .rates = MTK_PCM_RATES, 523 .formats = MTK_PCM_FORMATS, 524 }, 525 .ops = &mt8195_afe_fe_dai_ops, 526 }, 527 { 528 .name = "DL8", 529 .id = MT8195_AFE_MEMIF_DL8, 530 .playback = { 531 .stream_name = "DL8", 532 .channels_min = 1, 533 .channels_max = 24, 534 .rates = MTK_PCM_RATES, 535 .formats = MTK_PCM_FORMATS, 536 }, 537 .ops = &mt8195_afe_fe_dai_ops, 538 }, 539 { 540 .name = "DL10", 541 .id = MT8195_AFE_MEMIF_DL10, 542 .playback = { 543 .stream_name = "DL10", 544 .channels_min = 1, 545 .channels_max = 8, 546 .rates = MTK_PCM_RATES, 547 .formats = MTK_PCM_FORMATS, 548 }, 549 .ops = &mt8195_afe_fe_dai_ops, 550 }, 551 { 552 .name = "DL11", 553 .id = MT8195_AFE_MEMIF_DL11, 554 .playback = { 555 .stream_name = "DL11", 556 .channels_min = 1, 557 .channels_max = 48, 558 .rates = MTK_PCM_RATES, 559 .formats = MTK_PCM_FORMATS, 560 }, 561 .ops = &mt8195_afe_fe_dai_ops, 562 }, 563 { 564 .name = "UL1", 565 .id = MT8195_AFE_MEMIF_UL1, 566 .capture = { 567 .stream_name = "UL1", 568 .channels_min = 1, 569 .channels_max = 8, 570 .rates = MTK_PCM_RATES, 571 .formats = MTK_PCM_FORMATS, 572 }, 573 .ops = &mt8195_afe_fe_dai_ops, 574 }, 575 { 576 .name = "UL2", 577 .id = MT8195_AFE_MEMIF_UL2, 578 .capture = { 579 .stream_name = "UL2", 580 .channels_min = 1, 581 .channels_max = 8, 582 .rates = MTK_PCM_RATES, 583 .formats = MTK_PCM_FORMATS, 584 }, 585 .ops = &mt8195_afe_fe_dai_ops, 586 }, 587 { 588 .name = "UL3", 589 .id = MT8195_AFE_MEMIF_UL3, 590 .capture = { 591 .stream_name = "UL3", 592 .channels_min = 1, 593 .channels_max = 16, 594 .rates = MTK_PCM_RATES, 595 .formats = MTK_PCM_FORMATS, 596 }, 597 .ops = &mt8195_afe_fe_dai_ops, 598 }, 599 { 600 .name = "UL4", 601 .id = MT8195_AFE_MEMIF_UL4, 602 .capture = { 603 .stream_name = "UL4", 604 .channels_min = 1, 605 .channels_max = 2, 606 .rates = MTK_PCM_RATES, 607 .formats = MTK_PCM_FORMATS, 608 }, 609 .ops = &mt8195_afe_fe_dai_ops, 610 }, 611 { 612 .name = "UL5", 613 .id = MT8195_AFE_MEMIF_UL5, 614 .capture = { 615 .stream_name = "UL5", 616 .channels_min = 1, 617 .channels_max = 2, 618 .rates = MTK_PCM_RATES, 619 .formats = MTK_PCM_FORMATS, 620 }, 621 .ops = &mt8195_afe_fe_dai_ops, 622 }, 623 { 624 .name = "UL6", 625 .id = MT8195_AFE_MEMIF_UL6, 626 .capture = { 627 .stream_name = "UL6", 628 .channels_min = 1, 629 .channels_max = 8, 630 .rates = MTK_PCM_RATES, 631 .formats = MTK_PCM_FORMATS, 632 }, 633 .ops = &mt8195_afe_fe_dai_ops, 634 }, 635 { 636 .name = "UL8", 637 .id = MT8195_AFE_MEMIF_UL8, 638 .capture = { 639 .stream_name = "UL8", 640 .channels_min = 1, 641 .channels_max = 24, 642 .rates = MTK_PCM_RATES, 643 .formats = MTK_PCM_FORMATS, 644 }, 645 .ops = &mt8195_afe_fe_dai_ops, 646 }, 647 { 648 .name = "UL9", 649 .id = MT8195_AFE_MEMIF_UL9, 650 .capture = { 651 .stream_name = "UL9", 652 .channels_min = 1, 653 .channels_max = 32, 654 .rates = MTK_PCM_RATES, 655 .formats = MTK_PCM_FORMATS, 656 }, 657 .ops = &mt8195_afe_fe_dai_ops, 658 }, 659 { 660 .name = "UL10", 661 .id = MT8195_AFE_MEMIF_UL10, 662 .capture = { 663 .stream_name = "UL10", 664 .channels_min = 1, 665 .channels_max = 4, 666 .rates = MTK_PCM_RATES, 667 .formats = MTK_PCM_FORMATS, 668 }, 669 .ops = &mt8195_afe_fe_dai_ops, 670 }, 671 }; 672 673 static const struct snd_kcontrol_new o002_mix[] = { 674 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0), 675 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0), 676 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0), 677 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0), 678 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0), 679 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0), 680 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0), 681 }; 682 683 static const struct snd_kcontrol_new o003_mix[] = { 684 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0), 685 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0), 686 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0), 687 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0), 688 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0), 689 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0), 690 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0), 691 }; 692 693 static const struct snd_kcontrol_new o004_mix[] = { 694 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0), 695 SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0), 696 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0), 697 SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0), 698 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN4_5, 10, 1, 0), 699 }; 700 701 static const struct snd_kcontrol_new o005_mix[] = { 702 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0), 703 SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0), 704 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0), 705 SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0), 706 SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN5_5, 11, 1, 0), 707 }; 708 709 static const struct snd_kcontrol_new o006_mix[] = { 710 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0), 711 SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0), 712 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0), 713 SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0), 714 }; 715 716 static const struct snd_kcontrol_new o007_mix[] = { 717 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0), 718 SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0), 719 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0), 720 SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0), 721 }; 722 723 static const struct snd_kcontrol_new o008_mix[] = { 724 SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0), 725 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0), 726 SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0), 727 }; 728 729 static const struct snd_kcontrol_new o009_mix[] = { 730 SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0), 731 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0), 732 SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0), 733 }; 734 735 static const struct snd_kcontrol_new o010_mix[] = { 736 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0), 737 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0), 738 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0), 739 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0), 740 }; 741 742 static const struct snd_kcontrol_new o011_mix[] = { 743 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0), 744 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0), 745 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0), 746 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0), 747 }; 748 749 static const struct snd_kcontrol_new o012_mix[] = { 750 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0), 751 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0), 752 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0), 753 SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0), 754 }; 755 756 static const struct snd_kcontrol_new o013_mix[] = { 757 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0), 758 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0), 759 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0), 760 SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0), 761 }; 762 763 static const struct snd_kcontrol_new o014_mix[] = { 764 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0), 765 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0), 766 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0), 767 SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0), 768 }; 769 770 static const struct snd_kcontrol_new o015_mix[] = { 771 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0), 772 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0), 773 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0), 774 SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0), 775 }; 776 777 static const struct snd_kcontrol_new o016_mix[] = { 778 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0), 779 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0), 780 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0), 781 SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0), 782 }; 783 784 static const struct snd_kcontrol_new o017_mix[] = { 785 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0), 786 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0), 787 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0), 788 SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0), 789 }; 790 791 static const struct snd_kcontrol_new o018_mix[] = { 792 SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN18_1, 6, 1, 0), 793 SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0), 794 }; 795 796 static const struct snd_kcontrol_new o019_mix[] = { 797 SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN19_1, 7, 1, 0), 798 SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0), 799 }; 800 801 static const struct snd_kcontrol_new o020_mix[] = { 802 SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN20_1, 8, 1, 0), 803 SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0), 804 }; 805 806 static const struct snd_kcontrol_new o021_mix[] = { 807 SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN21_1, 9, 1, 0), 808 SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0), 809 }; 810 811 static const struct snd_kcontrol_new o022_mix[] = { 812 SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN22_1, 10, 1, 0), 813 SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0), 814 }; 815 816 static const struct snd_kcontrol_new o023_mix[] = { 817 SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN23_1, 11, 1, 0), 818 SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0), 819 }; 820 821 static const struct snd_kcontrol_new o024_mix[] = { 822 SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN24_1, 12, 1, 0), 823 SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0), 824 }; 825 826 static const struct snd_kcontrol_new o025_mix[] = { 827 SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN25_1, 13, 1, 0), 828 SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0), 829 }; 830 831 static const struct snd_kcontrol_new o026_mix[] = { 832 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0), 833 SOC_DAPM_SINGLE_AUTODISABLE("I088 Switch", AFE_CONN26_2, 24, 1, 0), 834 }; 835 836 static const struct snd_kcontrol_new o027_mix[] = { 837 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0), 838 SOC_DAPM_SINGLE_AUTODISABLE("I089 Switch", AFE_CONN27_2, 25, 1, 0), 839 }; 840 841 static const struct snd_kcontrol_new o028_mix[] = { 842 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0), 843 SOC_DAPM_SINGLE_AUTODISABLE("I090 Switch", AFE_CONN28_2, 26, 1, 0), 844 }; 845 846 static const struct snd_kcontrol_new o029_mix[] = { 847 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0), 848 SOC_DAPM_SINGLE_AUTODISABLE("I091 Switch", AFE_CONN29_2, 27, 1, 0), 849 }; 850 851 static const struct snd_kcontrol_new o030_mix[] = { 852 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0), 853 SOC_DAPM_SINGLE_AUTODISABLE("I092 Switch", AFE_CONN30_2, 28, 1, 0), 854 }; 855 856 static const struct snd_kcontrol_new o031_mix[] = { 857 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0), 858 SOC_DAPM_SINGLE_AUTODISABLE("I093 Switch", AFE_CONN31_2, 29, 1, 0), 859 }; 860 861 static const struct snd_kcontrol_new o032_mix[] = { 862 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0), 863 SOC_DAPM_SINGLE_AUTODISABLE("I094 Switch", AFE_CONN32_2, 30, 1, 0), 864 }; 865 866 static const struct snd_kcontrol_new o033_mix[] = { 867 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0), 868 SOC_DAPM_SINGLE_AUTODISABLE("I095 Switch", AFE_CONN33_2, 31, 1, 0), 869 }; 870 871 static const struct snd_kcontrol_new o034_mix[] = { 872 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0), 873 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0), 874 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0), 875 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0), 876 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0), 877 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0), 878 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0), 879 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN34_5, 10, 1, 0), 880 }; 881 882 static const struct snd_kcontrol_new o035_mix[] = { 883 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0), 884 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0), 885 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0), 886 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0), 887 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0), 888 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0), 889 SOC_DAPM_SINGLE_AUTODISABLE("I137 Switch", AFE_CONN35_4, 9, 1, 0), 890 SOC_DAPM_SINGLE_AUTODISABLE("I139 Switch", AFE_CONN35_4, 11, 1, 0), 891 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0), 892 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0), 893 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN35_5, 10, 1, 0), 894 SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN35_5, 11, 1, 0), 895 }; 896 897 static const struct snd_kcontrol_new o036_mix[] = { 898 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0), 899 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0), 900 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0), 901 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0), 902 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0), 903 }; 904 905 static const struct snd_kcontrol_new o037_mix[] = { 906 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0), 907 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0), 908 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0), 909 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0), 910 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0), 911 }; 912 913 static const struct snd_kcontrol_new o038_mix[] = { 914 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0), 915 }; 916 917 static const struct snd_kcontrol_new o039_mix[] = { 918 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0), 919 }; 920 921 static const struct snd_kcontrol_new o040_mix[] = { 922 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0), 923 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0), 924 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0), 925 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0), 926 }; 927 928 static const struct snd_kcontrol_new o041_mix[] = { 929 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0), 930 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0), 931 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0), 932 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0), 933 }; 934 935 static const struct snd_kcontrol_new o042_mix[] = { 936 SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0), 937 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0), 938 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN42_5, 10, 1, 0), 939 }; 940 941 static const struct snd_kcontrol_new o043_mix[] = { 942 SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0), 943 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0), 944 SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN43_5, 11, 1, 0), 945 }; 946 947 static const struct snd_kcontrol_new o044_mix[] = { 948 SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0), 949 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0), 950 }; 951 952 static const struct snd_kcontrol_new o045_mix[] = { 953 SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0), 954 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0), 955 }; 956 957 static const struct snd_kcontrol_new o046_mix[] = { 958 SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0), 959 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0), 960 }; 961 962 static const struct snd_kcontrol_new o047_mix[] = { 963 SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0), 964 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0), 965 }; 966 967 static const struct snd_kcontrol_new o182_mix[] = { 968 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0), 969 }; 970 971 static const struct snd_kcontrol_new o183_mix[] = { 972 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0), 973 }; 974 975 static const char * const dl8_dl11_data_sel_mux_text[] = { 976 "dl8", "dl11", 977 }; 978 979 static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum, 980 AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text); 981 982 static const struct snd_kcontrol_new dl8_dl11_data_sel_mux = 983 SOC_DAPM_ENUM("DL8_DL11 Sink", dl8_dl11_data_sel_mux_enum); 984 985 static const struct snd_soc_dapm_widget mt8195_memif_widgets[] = { 986 /* DL6 */ 987 SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0), 988 SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0), 989 990 /* DL3 */ 991 SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0), 992 SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0), 993 994 /* DL11 */ 995 SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0), 996 SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0), 997 SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0), 998 SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0), 999 SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0), 1000 SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0), 1001 SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0), 1002 SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0), 1003 SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0), 1004 SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0), 1005 SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0), 1006 SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0), 1007 SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0), 1008 SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0), 1009 SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0), 1010 SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0), 1011 SND_SOC_DAPM_MIXER("I038", SND_SOC_NOPM, 0, 0, NULL, 0), 1012 SND_SOC_DAPM_MIXER("I039", SND_SOC_NOPM, 0, 0, NULL, 0), 1013 SND_SOC_DAPM_MIXER("I040", SND_SOC_NOPM, 0, 0, NULL, 0), 1014 SND_SOC_DAPM_MIXER("I041", SND_SOC_NOPM, 0, 0, NULL, 0), 1015 SND_SOC_DAPM_MIXER("I042", SND_SOC_NOPM, 0, 0, NULL, 0), 1016 SND_SOC_DAPM_MIXER("I043", SND_SOC_NOPM, 0, 0, NULL, 0), 1017 SND_SOC_DAPM_MIXER("I044", SND_SOC_NOPM, 0, 0, NULL, 0), 1018 SND_SOC_DAPM_MIXER("I045", SND_SOC_NOPM, 0, 0, NULL, 0), 1019 1020 /* DL11/DL8 */ 1021 SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0), 1022 SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0), 1023 SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0), 1024 SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0), 1025 SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0), 1026 SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0), 1027 SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0), 1028 SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0), 1029 SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0), 1030 SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0), 1031 SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0), 1032 SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0), 1033 SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0), 1034 SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0), 1035 SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0), 1036 SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0), 1037 SND_SOC_DAPM_MIXER("I062", SND_SOC_NOPM, 0, 0, NULL, 0), 1038 SND_SOC_DAPM_MIXER("I063", SND_SOC_NOPM, 0, 0, NULL, 0), 1039 SND_SOC_DAPM_MIXER("I064", SND_SOC_NOPM, 0, 0, NULL, 0), 1040 SND_SOC_DAPM_MIXER("I065", SND_SOC_NOPM, 0, 0, NULL, 0), 1041 SND_SOC_DAPM_MIXER("I066", SND_SOC_NOPM, 0, 0, NULL, 0), 1042 SND_SOC_DAPM_MIXER("I067", SND_SOC_NOPM, 0, 0, NULL, 0), 1043 SND_SOC_DAPM_MIXER("I068", SND_SOC_NOPM, 0, 0, NULL, 0), 1044 SND_SOC_DAPM_MIXER("I069", SND_SOC_NOPM, 0, 0, NULL, 0), 1045 1046 /* DL2 */ 1047 SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0), 1048 SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0), 1049 1050 SND_SOC_DAPM_MUX("DL8_DL11 Mux", 1051 SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux), 1052 1053 /* UL9 */ 1054 SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0, 1055 o002_mix, ARRAY_SIZE(o002_mix)), 1056 SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0, 1057 o003_mix, ARRAY_SIZE(o003_mix)), 1058 SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0, 1059 o004_mix, ARRAY_SIZE(o004_mix)), 1060 SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0, 1061 o005_mix, ARRAY_SIZE(o005_mix)), 1062 SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0, 1063 o006_mix, ARRAY_SIZE(o006_mix)), 1064 SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0, 1065 o007_mix, ARRAY_SIZE(o007_mix)), 1066 SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0, 1067 o008_mix, ARRAY_SIZE(o008_mix)), 1068 SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0, 1069 o009_mix, ARRAY_SIZE(o009_mix)), 1070 SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0, 1071 o010_mix, ARRAY_SIZE(o010_mix)), 1072 SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0, 1073 o011_mix, ARRAY_SIZE(o011_mix)), 1074 SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0, 1075 o012_mix, ARRAY_SIZE(o012_mix)), 1076 SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0, 1077 o013_mix, ARRAY_SIZE(o013_mix)), 1078 SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0, 1079 o014_mix, ARRAY_SIZE(o014_mix)), 1080 SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0, 1081 o015_mix, ARRAY_SIZE(o015_mix)), 1082 SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0, 1083 o016_mix, ARRAY_SIZE(o016_mix)), 1084 SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0, 1085 o017_mix, ARRAY_SIZE(o017_mix)), 1086 SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0, 1087 o018_mix, ARRAY_SIZE(o018_mix)), 1088 SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0, 1089 o019_mix, ARRAY_SIZE(o019_mix)), 1090 SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0, 1091 o020_mix, ARRAY_SIZE(o020_mix)), 1092 SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0, 1093 o021_mix, ARRAY_SIZE(o021_mix)), 1094 SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0, 1095 o022_mix, ARRAY_SIZE(o022_mix)), 1096 SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0, 1097 o023_mix, ARRAY_SIZE(o023_mix)), 1098 SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0, 1099 o024_mix, ARRAY_SIZE(o024_mix)), 1100 SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0, 1101 o025_mix, ARRAY_SIZE(o025_mix)), 1102 SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0, 1103 o026_mix, ARRAY_SIZE(o026_mix)), 1104 SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0, 1105 o027_mix, ARRAY_SIZE(o027_mix)), 1106 SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0, 1107 o028_mix, ARRAY_SIZE(o028_mix)), 1108 SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0, 1109 o029_mix, ARRAY_SIZE(o029_mix)), 1110 SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0, 1111 o030_mix, ARRAY_SIZE(o030_mix)), 1112 SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0, 1113 o031_mix, ARRAY_SIZE(o031_mix)), 1114 SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0, 1115 o032_mix, ARRAY_SIZE(o032_mix)), 1116 SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0, 1117 o033_mix, ARRAY_SIZE(o033_mix)), 1118 1119 /* UL4 */ 1120 SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0, 1121 o034_mix, ARRAY_SIZE(o034_mix)), 1122 SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0, 1123 o035_mix, ARRAY_SIZE(o035_mix)), 1124 1125 /* UL5 */ 1126 SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0, 1127 o036_mix, ARRAY_SIZE(o036_mix)), 1128 SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0, 1129 o037_mix, ARRAY_SIZE(o037_mix)), 1130 1131 /* UL10 */ 1132 SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0, 1133 o038_mix, ARRAY_SIZE(o038_mix)), 1134 SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0, 1135 o039_mix, ARRAY_SIZE(o039_mix)), 1136 SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0, 1137 o182_mix, ARRAY_SIZE(o182_mix)), 1138 SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0, 1139 o183_mix, ARRAY_SIZE(o183_mix)), 1140 1141 /* UL2 */ 1142 SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0, 1143 o040_mix, ARRAY_SIZE(o040_mix)), 1144 SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0, 1145 o041_mix, ARRAY_SIZE(o041_mix)), 1146 SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0, 1147 o042_mix, ARRAY_SIZE(o042_mix)), 1148 SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0, 1149 o043_mix, ARRAY_SIZE(o043_mix)), 1150 SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0, 1151 o044_mix, ARRAY_SIZE(o044_mix)), 1152 SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0, 1153 o045_mix, ARRAY_SIZE(o045_mix)), 1154 SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0, 1155 o046_mix, ARRAY_SIZE(o046_mix)), 1156 SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0, 1157 o047_mix, ARRAY_SIZE(o047_mix)), 1158 }; 1159 1160 static const struct snd_soc_dapm_route mt8195_memif_routes[] = { 1161 {"I000", NULL, "DL6"}, 1162 {"I001", NULL, "DL6"}, 1163 1164 {"I020", NULL, "DL3"}, 1165 {"I021", NULL, "DL3"}, 1166 1167 {"I022", NULL, "DL11"}, 1168 {"I023", NULL, "DL11"}, 1169 {"I024", NULL, "DL11"}, 1170 {"I025", NULL, "DL11"}, 1171 {"I026", NULL, "DL11"}, 1172 {"I027", NULL, "DL11"}, 1173 {"I028", NULL, "DL11"}, 1174 {"I029", NULL, "DL11"}, 1175 {"I030", NULL, "DL11"}, 1176 {"I031", NULL, "DL11"}, 1177 {"I032", NULL, "DL11"}, 1178 {"I033", NULL, "DL11"}, 1179 {"I034", NULL, "DL11"}, 1180 {"I035", NULL, "DL11"}, 1181 {"I036", NULL, "DL11"}, 1182 {"I037", NULL, "DL11"}, 1183 {"I038", NULL, "DL11"}, 1184 {"I039", NULL, "DL11"}, 1185 {"I040", NULL, "DL11"}, 1186 {"I041", NULL, "DL11"}, 1187 {"I042", NULL, "DL11"}, 1188 {"I043", NULL, "DL11"}, 1189 {"I044", NULL, "DL11"}, 1190 {"I045", NULL, "DL11"}, 1191 1192 {"DL8_DL11 Mux", "dl8", "DL8"}, 1193 {"DL8_DL11 Mux", "dl11", "DL11"}, 1194 1195 {"I046", NULL, "DL8_DL11 Mux"}, 1196 {"I047", NULL, "DL8_DL11 Mux"}, 1197 {"I048", NULL, "DL8_DL11 Mux"}, 1198 {"I049", NULL, "DL8_DL11 Mux"}, 1199 {"I050", NULL, "DL8_DL11 Mux"}, 1200 {"I051", NULL, "DL8_DL11 Mux"}, 1201 {"I052", NULL, "DL8_DL11 Mux"}, 1202 {"I053", NULL, "DL8_DL11 Mux"}, 1203 {"I054", NULL, "DL8_DL11 Mux"}, 1204 {"I055", NULL, "DL8_DL11 Mux"}, 1205 {"I056", NULL, "DL8_DL11 Mux"}, 1206 {"I057", NULL, "DL8_DL11 Mux"}, 1207 {"I058", NULL, "DL8_DL11 Mux"}, 1208 {"I059", NULL, "DL8_DL11 Mux"}, 1209 {"I060", NULL, "DL8_DL11 Mux"}, 1210 {"I061", NULL, "DL8_DL11 Mux"}, 1211 {"I062", NULL, "DL8_DL11 Mux"}, 1212 {"I063", NULL, "DL8_DL11 Mux"}, 1213 {"I064", NULL, "DL8_DL11 Mux"}, 1214 {"I065", NULL, "DL8_DL11 Mux"}, 1215 {"I066", NULL, "DL8_DL11 Mux"}, 1216 {"I067", NULL, "DL8_DL11 Mux"}, 1217 {"I068", NULL, "DL8_DL11 Mux"}, 1218 {"I069", NULL, "DL8_DL11 Mux"}, 1219 1220 {"I070", NULL, "DL2"}, 1221 {"I071", NULL, "DL2"}, 1222 1223 {"UL9", NULL, "O002"}, 1224 {"UL9", NULL, "O003"}, 1225 {"UL9", NULL, "O004"}, 1226 {"UL9", NULL, "O005"}, 1227 {"UL9", NULL, "O006"}, 1228 {"UL9", NULL, "O007"}, 1229 {"UL9", NULL, "O008"}, 1230 {"UL9", NULL, "O009"}, 1231 {"UL9", NULL, "O010"}, 1232 {"UL9", NULL, "O011"}, 1233 {"UL9", NULL, "O012"}, 1234 {"UL9", NULL, "O013"}, 1235 {"UL9", NULL, "O014"}, 1236 {"UL9", NULL, "O015"}, 1237 {"UL9", NULL, "O016"}, 1238 {"UL9", NULL, "O017"}, 1239 {"UL9", NULL, "O018"}, 1240 {"UL9", NULL, "O019"}, 1241 {"UL9", NULL, "O020"}, 1242 {"UL9", NULL, "O021"}, 1243 {"UL9", NULL, "O022"}, 1244 {"UL9", NULL, "O023"}, 1245 {"UL9", NULL, "O024"}, 1246 {"UL9", NULL, "O025"}, 1247 {"UL9", NULL, "O026"}, 1248 {"UL9", NULL, "O027"}, 1249 {"UL9", NULL, "O028"}, 1250 {"UL9", NULL, "O029"}, 1251 {"UL9", NULL, "O030"}, 1252 {"UL9", NULL, "O031"}, 1253 {"UL9", NULL, "O032"}, 1254 {"UL9", NULL, "O033"}, 1255 1256 {"UL4", NULL, "O034"}, 1257 {"UL4", NULL, "O035"}, 1258 1259 {"UL5", NULL, "O036"}, 1260 {"UL5", NULL, "O037"}, 1261 1262 {"UL10", NULL, "O038"}, 1263 {"UL10", NULL, "O039"}, 1264 {"UL10", NULL, "O182"}, 1265 {"UL10", NULL, "O183"}, 1266 1267 {"UL2", NULL, "O040"}, 1268 {"UL2", NULL, "O041"}, 1269 {"UL2", NULL, "O042"}, 1270 {"UL2", NULL, "O043"}, 1271 {"UL2", NULL, "O044"}, 1272 {"UL2", NULL, "O045"}, 1273 {"UL2", NULL, "O046"}, 1274 {"UL2", NULL, "O047"}, 1275 1276 {"O004", "I000 Switch", "I000"}, 1277 {"O005", "I001 Switch", "I001"}, 1278 1279 {"O006", "I000 Switch", "I000"}, 1280 {"O007", "I001 Switch", "I001"}, 1281 1282 {"O010", "I022 Switch", "I022"}, 1283 {"O011", "I023 Switch", "I023"}, 1284 {"O012", "I024 Switch", "I024"}, 1285 {"O013", "I025 Switch", "I025"}, 1286 {"O014", "I026 Switch", "I026"}, 1287 {"O015", "I027 Switch", "I027"}, 1288 {"O016", "I028 Switch", "I028"}, 1289 {"O017", "I029 Switch", "I029"}, 1290 1291 {"O010", "I046 Switch", "I046"}, 1292 {"O011", "I047 Switch", "I047"}, 1293 {"O012", "I048 Switch", "I048"}, 1294 {"O013", "I049 Switch", "I049"}, 1295 {"O014", "I050 Switch", "I050"}, 1296 {"O015", "I051 Switch", "I051"}, 1297 {"O016", "I052 Switch", "I052"}, 1298 {"O017", "I053 Switch", "I053"}, 1299 {"O002", "I022 Switch", "I022"}, 1300 {"O003", "I023 Switch", "I023"}, 1301 {"O004", "I024 Switch", "I024"}, 1302 {"O005", "I025 Switch", "I025"}, 1303 {"O006", "I026 Switch", "I026"}, 1304 {"O007", "I027 Switch", "I027"}, 1305 {"O008", "I028 Switch", "I028"}, 1306 {"O009", "I029 Switch", "I029"}, 1307 {"O010", "I030 Switch", "I030"}, 1308 {"O011", "I031 Switch", "I031"}, 1309 {"O012", "I032 Switch", "I032"}, 1310 {"O013", "I033 Switch", "I033"}, 1311 {"O014", "I034 Switch", "I034"}, 1312 {"O015", "I035 Switch", "I035"}, 1313 {"O016", "I036 Switch", "I036"}, 1314 {"O017", "I037 Switch", "I037"}, 1315 {"O018", "I038 Switch", "I038"}, 1316 {"O019", "I039 Switch", "I039"}, 1317 {"O020", "I040 Switch", "I040"}, 1318 {"O021", "I041 Switch", "I041"}, 1319 {"O022", "I042 Switch", "I042"}, 1320 {"O023", "I043 Switch", "I043"}, 1321 {"O024", "I044 Switch", "I044"}, 1322 {"O025", "I045 Switch", "I045"}, 1323 {"O026", "I046 Switch", "I046"}, 1324 {"O027", "I047 Switch", "I047"}, 1325 {"O028", "I048 Switch", "I048"}, 1326 {"O029", "I049 Switch", "I049"}, 1327 {"O030", "I050 Switch", "I050"}, 1328 {"O031", "I051 Switch", "I051"}, 1329 {"O032", "I052 Switch", "I052"}, 1330 {"O033", "I053 Switch", "I053"}, 1331 1332 {"O002", "I000 Switch", "I000"}, 1333 {"O003", "I001 Switch", "I001"}, 1334 {"O002", "I020 Switch", "I020"}, 1335 {"O003", "I021 Switch", "I021"}, 1336 {"O002", "I070 Switch", "I070"}, 1337 {"O003", "I071 Switch", "I071"}, 1338 1339 {"O034", "I000 Switch", "I000"}, 1340 {"O035", "I001 Switch", "I001"}, 1341 {"O034", "I002 Switch", "I002"}, 1342 {"O035", "I003 Switch", "I003"}, 1343 {"O034", "I012 Switch", "I012"}, 1344 {"O035", "I013 Switch", "I013"}, 1345 {"O034", "I020 Switch", "I020"}, 1346 {"O035", "I021 Switch", "I021"}, 1347 {"O034", "I070 Switch", "I070"}, 1348 {"O035", "I071 Switch", "I071"}, 1349 {"O034", "I072 Switch", "I072"}, 1350 {"O035", "I073 Switch", "I073"}, 1351 1352 {"O036", "I000 Switch", "I000"}, 1353 {"O037", "I001 Switch", "I001"}, 1354 {"O036", "I012 Switch", "I012"}, 1355 {"O037", "I013 Switch", "I013"}, 1356 {"O036", "I020 Switch", "I020"}, 1357 {"O037", "I021 Switch", "I021"}, 1358 {"O036", "I070 Switch", "I070"}, 1359 {"O037", "I071 Switch", "I071"}, 1360 {"O036", "I168 Switch", "I168"}, 1361 {"O037", "I169 Switch", "I169"}, 1362 1363 {"O038", "I022 Switch", "I022"}, 1364 {"O039", "I023 Switch", "I023"}, 1365 {"O182", "I024 Switch", "I024"}, 1366 {"O183", "I025 Switch", "I025"}, 1367 1368 {"O040", "I022 Switch", "I022"}, 1369 {"O041", "I023 Switch", "I023"}, 1370 {"O042", "I024 Switch", "I024"}, 1371 {"O043", "I025 Switch", "I025"}, 1372 {"O044", "I026 Switch", "I026"}, 1373 {"O045", "I027 Switch", "I027"}, 1374 {"O046", "I028 Switch", "I028"}, 1375 {"O047", "I029 Switch", "I029"}, 1376 1377 {"O040", "I002 Switch", "I002"}, 1378 {"O041", "I003 Switch", "I003"}, 1379 {"O002", "I012 Switch", "I012"}, 1380 {"O003", "I013 Switch", "I013"}, 1381 {"O004", "I014 Switch", "I014"}, 1382 {"O005", "I015 Switch", "I015"}, 1383 {"O006", "I016 Switch", "I016"}, 1384 {"O007", "I017 Switch", "I017"}, 1385 {"O008", "I018 Switch", "I018"}, 1386 {"O009", "I019 Switch", "I019"}, 1387 1388 {"O040", "I012 Switch", "I012"}, 1389 {"O041", "I013 Switch", "I013"}, 1390 {"O042", "I014 Switch", "I014"}, 1391 {"O043", "I015 Switch", "I015"}, 1392 {"O044", "I016 Switch", "I016"}, 1393 {"O045", "I017 Switch", "I017"}, 1394 {"O046", "I018 Switch", "I018"}, 1395 {"O047", "I019 Switch", "I019"}, 1396 1397 {"O002", "I072 Switch", "I072"}, 1398 {"O003", "I073 Switch", "I073"}, 1399 {"O004", "I074 Switch", "I074"}, 1400 {"O005", "I075 Switch", "I075"}, 1401 {"O006", "I076 Switch", "I076"}, 1402 {"O007", "I077 Switch", "I077"}, 1403 {"O008", "I078 Switch", "I078"}, 1404 {"O009", "I079 Switch", "I079"}, 1405 1406 {"O010", "I072 Switch", "I072"}, 1407 {"O011", "I073 Switch", "I073"}, 1408 {"O012", "I074 Switch", "I074"}, 1409 {"O013", "I075 Switch", "I075"}, 1410 {"O014", "I076 Switch", "I076"}, 1411 {"O015", "I077 Switch", "I077"}, 1412 {"O016", "I078 Switch", "I078"}, 1413 {"O017", "I079 Switch", "I079"}, 1414 {"O018", "I080 Switch", "I080"}, 1415 {"O019", "I081 Switch", "I081"}, 1416 {"O020", "I082 Switch", "I082"}, 1417 {"O021", "I083 Switch", "I083"}, 1418 {"O022", "I084 Switch", "I084"}, 1419 {"O023", "I085 Switch", "I085"}, 1420 {"O024", "I086 Switch", "I086"}, 1421 {"O025", "I087 Switch", "I087"}, 1422 {"O026", "I088 Switch", "I088"}, 1423 {"O027", "I089 Switch", "I089"}, 1424 {"O028", "I090 Switch", "I090"}, 1425 {"O029", "I091 Switch", "I091"}, 1426 {"O030", "I092 Switch", "I092"}, 1427 {"O031", "I093 Switch", "I093"}, 1428 {"O032", "I094 Switch", "I094"}, 1429 {"O033", "I095 Switch", "I095"}, 1430 1431 {"O002", "I168 Switch", "I168"}, 1432 {"O003", "I169 Switch", "I169"}, 1433 {"O004", "I170 Switch", "I170"}, 1434 {"O005", "I171 Switch", "I171"}, 1435 1436 {"O034", "I168 Switch", "I168"}, 1437 {"O035", "I168 Switch", "I168"}, 1438 {"O035", "I169 Switch", "I169"}, 1439 1440 {"O034", "I170 Switch", "I170"}, 1441 {"O035", "I170 Switch", "I170"}, 1442 {"O035", "I171 Switch", "I171"}, 1443 1444 {"O040", "I168 Switch", "I168"}, 1445 {"O041", "I169 Switch", "I169"}, 1446 {"O042", "I170 Switch", "I170"}, 1447 {"O043", "I171 Switch", "I171"}, 1448 }; 1449 1450 static const char * const mt8195_afe_1x_en_sel_text[] = { 1451 "a1sys_a2sys", "a3sys", "a4sys", 1452 }; 1453 1454 static const unsigned int mt8195_afe_1x_en_sel_values[] = { 1455 0, 1, 2, 1456 }; 1457 1458 static int mt8195_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol, 1459 struct snd_ctl_elem_value *ucontrol) 1460 { 1461 struct snd_soc_component *component = 1462 snd_soc_kcontrol_component(kcontrol); 1463 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1464 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1465 struct mtk_dai_memif_priv *memif_priv; 1466 unsigned int dai_id = kcontrol->id.device; 1467 long val = ucontrol->value.integer.value[0]; 1468 int ret = 0; 1469 1470 memif_priv = afe_priv->dai_priv[dai_id]; 1471 1472 if (val == memif_priv->asys_timing_sel) 1473 return 0; 1474 1475 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1476 1477 memif_priv->asys_timing_sel = val; 1478 1479 return ret; 1480 } 1481 1482 static int mt8195_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol, 1483 struct snd_ctl_elem_value *ucontrol) 1484 { 1485 struct snd_soc_component *component = 1486 snd_soc_kcontrol_component(kcontrol); 1487 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1488 struct mt8195_afe_private *afe_priv = afe->platform_priv; 1489 unsigned int id = kcontrol->id.device; 1490 long val = ucontrol->value.integer.value[0]; 1491 int ret = 0; 1492 1493 if (val == afe_priv->irq_priv[id].asys_timing_sel) 1494 return 0; 1495 1496 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1497 1498 afe_priv->irq_priv[id].asys_timing_sel = val; 1499 1500 return ret; 1501 } 1502 1503 static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum, 1504 A3_A4_TIMING_SEL1, 18, 0x3, 1505 mt8195_afe_1x_en_sel_text, 1506 mt8195_afe_1x_en_sel_values); 1507 static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum, 1508 A3_A4_TIMING_SEL1, 20, 0x3, 1509 mt8195_afe_1x_en_sel_text, 1510 mt8195_afe_1x_en_sel_values); 1511 static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum, 1512 A3_A4_TIMING_SEL1, 22, 0x3, 1513 mt8195_afe_1x_en_sel_text, 1514 mt8195_afe_1x_en_sel_values); 1515 static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum, 1516 A3_A4_TIMING_SEL1, 24, 0x3, 1517 mt8195_afe_1x_en_sel_text, 1518 mt8195_afe_1x_en_sel_values); 1519 static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum, 1520 A3_A4_TIMING_SEL1, 26, 0x3, 1521 mt8195_afe_1x_en_sel_text, 1522 mt8195_afe_1x_en_sel_values); 1523 static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum, 1524 A3_A4_TIMING_SEL1, 28, 0x3, 1525 mt8195_afe_1x_en_sel_text, 1526 mt8195_afe_1x_en_sel_values); 1527 static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum, 1528 A3_A4_TIMING_SEL1, 30, 0x3, 1529 mt8195_afe_1x_en_sel_text, 1530 mt8195_afe_1x_en_sel_values); 1531 static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum, 1532 A3_A4_TIMING_SEL1, 0, 0x3, 1533 mt8195_afe_1x_en_sel_text, 1534 mt8195_afe_1x_en_sel_values); 1535 static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum, 1536 A3_A4_TIMING_SEL1, 2, 0x3, 1537 mt8195_afe_1x_en_sel_text, 1538 mt8195_afe_1x_en_sel_values); 1539 static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum, 1540 A3_A4_TIMING_SEL1, 4, 0x3, 1541 mt8195_afe_1x_en_sel_text, 1542 mt8195_afe_1x_en_sel_values); 1543 static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum, 1544 A3_A4_TIMING_SEL1, 6, 0x3, 1545 mt8195_afe_1x_en_sel_text, 1546 mt8195_afe_1x_en_sel_values); 1547 static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum, 1548 A3_A4_TIMING_SEL1, 8, 0x3, 1549 mt8195_afe_1x_en_sel_text, 1550 mt8195_afe_1x_en_sel_values); 1551 static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum, 1552 A3_A4_TIMING_SEL1, 10, 0x3, 1553 mt8195_afe_1x_en_sel_text, 1554 mt8195_afe_1x_en_sel_values); 1555 static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum, 1556 A3_A4_TIMING_SEL1, 12, 0x3, 1557 mt8195_afe_1x_en_sel_text, 1558 mt8195_afe_1x_en_sel_values); 1559 static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum, 1560 A3_A4_TIMING_SEL1, 14, 0x3, 1561 mt8195_afe_1x_en_sel_text, 1562 mt8195_afe_1x_en_sel_values); 1563 static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum, 1564 A3_A4_TIMING_SEL1, 16, 0x3, 1565 mt8195_afe_1x_en_sel_text, 1566 mt8195_afe_1x_en_sel_values); 1567 1568 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum, 1569 A3_A4_TIMING_SEL6, 0, 0x3, 1570 mt8195_afe_1x_en_sel_text, 1571 mt8195_afe_1x_en_sel_values); 1572 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum, 1573 A3_A4_TIMING_SEL6, 2, 0x3, 1574 mt8195_afe_1x_en_sel_text, 1575 mt8195_afe_1x_en_sel_values); 1576 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum, 1577 A3_A4_TIMING_SEL6, 4, 0x3, 1578 mt8195_afe_1x_en_sel_text, 1579 mt8195_afe_1x_en_sel_values); 1580 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum, 1581 A3_A4_TIMING_SEL6, 6, 0x3, 1582 mt8195_afe_1x_en_sel_text, 1583 mt8195_afe_1x_en_sel_values); 1584 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum, 1585 A3_A4_TIMING_SEL6, 8, 0x3, 1586 mt8195_afe_1x_en_sel_text, 1587 mt8195_afe_1x_en_sel_values); 1588 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum, 1589 A3_A4_TIMING_SEL6, 10, 0x3, 1590 mt8195_afe_1x_en_sel_text, 1591 mt8195_afe_1x_en_sel_values); 1592 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum, 1593 A3_A4_TIMING_SEL6, 12, 0x3, 1594 mt8195_afe_1x_en_sel_text, 1595 mt8195_afe_1x_en_sel_values); 1596 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum, 1597 A3_A4_TIMING_SEL6, 14, 0x3, 1598 mt8195_afe_1x_en_sel_text, 1599 mt8195_afe_1x_en_sel_values); 1600 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum, 1601 A3_A4_TIMING_SEL6, 16, 0x3, 1602 mt8195_afe_1x_en_sel_text, 1603 mt8195_afe_1x_en_sel_values); 1604 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum, 1605 A3_A4_TIMING_SEL6, 18, 0x3, 1606 mt8195_afe_1x_en_sel_text, 1607 mt8195_afe_1x_en_sel_values); 1608 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum, 1609 A3_A4_TIMING_SEL6, 20, 0x3, 1610 mt8195_afe_1x_en_sel_text, 1611 mt8195_afe_1x_en_sel_values); 1612 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum, 1613 A3_A4_TIMING_SEL6, 22, 0x3, 1614 mt8195_afe_1x_en_sel_text, 1615 mt8195_afe_1x_en_sel_values); 1616 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum, 1617 A3_A4_TIMING_SEL6, 24, 0x3, 1618 mt8195_afe_1x_en_sel_text, 1619 mt8195_afe_1x_en_sel_values); 1620 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum, 1621 A3_A4_TIMING_SEL6, 26, 0x3, 1622 mt8195_afe_1x_en_sel_text, 1623 mt8195_afe_1x_en_sel_values); 1624 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum, 1625 A3_A4_TIMING_SEL6, 28, 0x3, 1626 mt8195_afe_1x_en_sel_text, 1627 mt8195_afe_1x_en_sel_values); 1628 static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum, 1629 A3_A4_TIMING_SEL6, 30, 0x3, 1630 mt8195_afe_1x_en_sel_text, 1631 mt8195_afe_1x_en_sel_values); 1632 1633 static const struct snd_kcontrol_new mt8195_memif_controls[] = { 1634 MT8195_SOC_ENUM_EXT("dl2_1x_en_sel", 1635 dl2_1x_en_sel_enum, 1636 snd_soc_get_enum_double, 1637 mt8195_memif_1x_en_sel_put, 1638 MT8195_AFE_MEMIF_DL2), 1639 MT8195_SOC_ENUM_EXT("dl3_1x_en_sel", 1640 dl3_1x_en_sel_enum, 1641 snd_soc_get_enum_double, 1642 mt8195_memif_1x_en_sel_put, 1643 MT8195_AFE_MEMIF_DL3), 1644 MT8195_SOC_ENUM_EXT("dl6_1x_en_sel", 1645 dl6_1x_en_sel_enum, 1646 snd_soc_get_enum_double, 1647 mt8195_memif_1x_en_sel_put, 1648 MT8195_AFE_MEMIF_DL6), 1649 MT8195_SOC_ENUM_EXT("dl7_1x_en_sel", 1650 dl7_1x_en_sel_enum, 1651 snd_soc_get_enum_double, 1652 mt8195_memif_1x_en_sel_put, 1653 MT8195_AFE_MEMIF_DL7), 1654 MT8195_SOC_ENUM_EXT("dl8_1x_en_sel", 1655 dl8_1x_en_sel_enum, 1656 snd_soc_get_enum_double, 1657 mt8195_memif_1x_en_sel_put, 1658 MT8195_AFE_MEMIF_DL8), 1659 MT8195_SOC_ENUM_EXT("dl10_1x_en_sel", 1660 dl10_1x_en_sel_enum, 1661 snd_soc_get_enum_double, 1662 mt8195_memif_1x_en_sel_put, 1663 MT8195_AFE_MEMIF_DL10), 1664 MT8195_SOC_ENUM_EXT("dl11_1x_en_sel", 1665 dl11_1x_en_sel_enum, 1666 snd_soc_get_enum_double, 1667 mt8195_memif_1x_en_sel_put, 1668 MT8195_AFE_MEMIF_DL11), 1669 MT8195_SOC_ENUM_EXT("ul1_1x_en_sel", 1670 ul1_1x_en_sel_enum, 1671 snd_soc_get_enum_double, 1672 mt8195_memif_1x_en_sel_put, 1673 MT8195_AFE_MEMIF_UL1), 1674 MT8195_SOC_ENUM_EXT("ul2_1x_en_sel", 1675 ul2_1x_en_sel_enum, 1676 snd_soc_get_enum_double, 1677 mt8195_memif_1x_en_sel_put, 1678 MT8195_AFE_MEMIF_UL2), 1679 MT8195_SOC_ENUM_EXT("ul3_1x_en_sel", 1680 ul3_1x_en_sel_enum, 1681 snd_soc_get_enum_double, 1682 mt8195_memif_1x_en_sel_put, 1683 MT8195_AFE_MEMIF_UL3), 1684 MT8195_SOC_ENUM_EXT("ul4_1x_en_sel", 1685 ul4_1x_en_sel_enum, 1686 snd_soc_get_enum_double, 1687 mt8195_memif_1x_en_sel_put, 1688 MT8195_AFE_MEMIF_UL4), 1689 MT8195_SOC_ENUM_EXT("ul5_1x_en_sel", 1690 ul5_1x_en_sel_enum, 1691 snd_soc_get_enum_double, 1692 mt8195_memif_1x_en_sel_put, 1693 MT8195_AFE_MEMIF_UL5), 1694 MT8195_SOC_ENUM_EXT("ul6_1x_en_sel", 1695 ul6_1x_en_sel_enum, 1696 snd_soc_get_enum_double, 1697 mt8195_memif_1x_en_sel_put, 1698 MT8195_AFE_MEMIF_UL6), 1699 MT8195_SOC_ENUM_EXT("ul8_1x_en_sel", 1700 ul8_1x_en_sel_enum, 1701 snd_soc_get_enum_double, 1702 mt8195_memif_1x_en_sel_put, 1703 MT8195_AFE_MEMIF_UL8), 1704 MT8195_SOC_ENUM_EXT("ul9_1x_en_sel", 1705 ul9_1x_en_sel_enum, 1706 snd_soc_get_enum_double, 1707 mt8195_memif_1x_en_sel_put, 1708 MT8195_AFE_MEMIF_UL9), 1709 MT8195_SOC_ENUM_EXT("ul10_1x_en_sel", 1710 ul10_1x_en_sel_enum, 1711 snd_soc_get_enum_double, 1712 mt8195_memif_1x_en_sel_put, 1713 MT8195_AFE_MEMIF_UL10), 1714 MT8195_SOC_ENUM_EXT("asys_irq1_1x_en_sel", 1715 asys_irq1_1x_en_sel_enum, 1716 snd_soc_get_enum_double, 1717 mt8195_asys_irq_1x_en_sel_put, 1718 MT8195_AFE_IRQ_13), 1719 MT8195_SOC_ENUM_EXT("asys_irq2_1x_en_sel", 1720 asys_irq2_1x_en_sel_enum, 1721 snd_soc_get_enum_double, 1722 mt8195_asys_irq_1x_en_sel_put, 1723 MT8195_AFE_IRQ_14), 1724 MT8195_SOC_ENUM_EXT("asys_irq3_1x_en_sel", 1725 asys_irq3_1x_en_sel_enum, 1726 snd_soc_get_enum_double, 1727 mt8195_asys_irq_1x_en_sel_put, 1728 MT8195_AFE_IRQ_15), 1729 MT8195_SOC_ENUM_EXT("asys_irq4_1x_en_sel", 1730 asys_irq4_1x_en_sel_enum, 1731 snd_soc_get_enum_double, 1732 mt8195_asys_irq_1x_en_sel_put, 1733 MT8195_AFE_IRQ_16), 1734 MT8195_SOC_ENUM_EXT("asys_irq5_1x_en_sel", 1735 asys_irq5_1x_en_sel_enum, 1736 snd_soc_get_enum_double, 1737 mt8195_asys_irq_1x_en_sel_put, 1738 MT8195_AFE_IRQ_17), 1739 MT8195_SOC_ENUM_EXT("asys_irq6_1x_en_sel", 1740 asys_irq6_1x_en_sel_enum, 1741 snd_soc_get_enum_double, 1742 mt8195_asys_irq_1x_en_sel_put, 1743 MT8195_AFE_IRQ_18), 1744 MT8195_SOC_ENUM_EXT("asys_irq7_1x_en_sel", 1745 asys_irq7_1x_en_sel_enum, 1746 snd_soc_get_enum_double, 1747 mt8195_asys_irq_1x_en_sel_put, 1748 MT8195_AFE_IRQ_19), 1749 MT8195_SOC_ENUM_EXT("asys_irq8_1x_en_sel", 1750 asys_irq8_1x_en_sel_enum, 1751 snd_soc_get_enum_double, 1752 mt8195_asys_irq_1x_en_sel_put, 1753 MT8195_AFE_IRQ_20), 1754 MT8195_SOC_ENUM_EXT("asys_irq9_1x_en_sel", 1755 asys_irq9_1x_en_sel_enum, 1756 snd_soc_get_enum_double, 1757 mt8195_asys_irq_1x_en_sel_put, 1758 MT8195_AFE_IRQ_21), 1759 MT8195_SOC_ENUM_EXT("asys_irq10_1x_en_sel", 1760 asys_irq10_1x_en_sel_enum, 1761 snd_soc_get_enum_double, 1762 mt8195_asys_irq_1x_en_sel_put, 1763 MT8195_AFE_IRQ_22), 1764 MT8195_SOC_ENUM_EXT("asys_irq11_1x_en_sel", 1765 asys_irq11_1x_en_sel_enum, 1766 snd_soc_get_enum_double, 1767 mt8195_asys_irq_1x_en_sel_put, 1768 MT8195_AFE_IRQ_23), 1769 MT8195_SOC_ENUM_EXT("asys_irq12_1x_en_sel", 1770 asys_irq12_1x_en_sel_enum, 1771 snd_soc_get_enum_double, 1772 mt8195_asys_irq_1x_en_sel_put, 1773 MT8195_AFE_IRQ_24), 1774 MT8195_SOC_ENUM_EXT("asys_irq13_1x_en_sel", 1775 asys_irq13_1x_en_sel_enum, 1776 snd_soc_get_enum_double, 1777 mt8195_asys_irq_1x_en_sel_put, 1778 MT8195_AFE_IRQ_25), 1779 MT8195_SOC_ENUM_EXT("asys_irq14_1x_en_sel", 1780 asys_irq14_1x_en_sel_enum, 1781 snd_soc_get_enum_double, 1782 mt8195_asys_irq_1x_en_sel_put, 1783 MT8195_AFE_IRQ_26), 1784 MT8195_SOC_ENUM_EXT("asys_irq15_1x_en_sel", 1785 asys_irq15_1x_en_sel_enum, 1786 snd_soc_get_enum_double, 1787 mt8195_asys_irq_1x_en_sel_put, 1788 MT8195_AFE_IRQ_27), 1789 MT8195_SOC_ENUM_EXT("asys_irq16_1x_en_sel", 1790 asys_irq16_1x_en_sel_enum, 1791 snd_soc_get_enum_double, 1792 mt8195_asys_irq_1x_en_sel_put, 1793 MT8195_AFE_IRQ_28), 1794 }; 1795 1796 static const struct snd_soc_component_driver mt8195_afe_pcm_dai_component = { 1797 .name = "mt8195-afe-pcm-dai", 1798 }; 1799 1800 static const struct mtk_base_memif_data memif_data[MT8195_AFE_MEMIF_NUM] = { 1801 [MT8195_AFE_MEMIF_DL2] = { 1802 .name = "DL2", 1803 .id = MT8195_AFE_MEMIF_DL2, 1804 .reg_ofs_base = AFE_DL2_BASE, 1805 .reg_ofs_cur = AFE_DL2_CUR, 1806 .reg_ofs_end = AFE_DL2_END, 1807 .fs_reg = AFE_MEMIF_AGENT_FS_CON0, 1808 .fs_shift = 10, 1809 .fs_maskbit = 0x1f, 1810 .mono_reg = -1, 1811 .mono_shift = 0, 1812 .int_odd_flag_reg = -1, 1813 .int_odd_flag_shift = 0, 1814 .enable_reg = AFE_DAC_CON0, 1815 .enable_shift = 18, 1816 .hd_reg = AFE_DL2_CON0, 1817 .hd_shift = 5, 1818 .agent_disable_reg = AUDIO_TOP_CON5, 1819 .agent_disable_shift = 18, 1820 .ch_num_reg = AFE_DL2_CON0, 1821 .ch_num_shift = 0, 1822 .ch_num_maskbit = 0x1f, 1823 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1824 .msb_shift = 18, 1825 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1826 .msb_end_shift = 18, 1827 }, 1828 [MT8195_AFE_MEMIF_DL3] = { 1829 .name = "DL3", 1830 .id = MT8195_AFE_MEMIF_DL3, 1831 .reg_ofs_base = AFE_DL3_BASE, 1832 .reg_ofs_cur = AFE_DL3_CUR, 1833 .reg_ofs_end = AFE_DL3_END, 1834 .fs_reg = AFE_MEMIF_AGENT_FS_CON0, 1835 .fs_shift = 15, 1836 .fs_maskbit = 0x1f, 1837 .mono_reg = -1, 1838 .mono_shift = 0, 1839 .int_odd_flag_reg = -1, 1840 .int_odd_flag_shift = 0, 1841 .enable_reg = AFE_DAC_CON0, 1842 .enable_shift = 19, 1843 .hd_reg = AFE_DL3_CON0, 1844 .hd_shift = 5, 1845 .agent_disable_reg = AUDIO_TOP_CON5, 1846 .agent_disable_shift = 19, 1847 .ch_num_reg = AFE_DL3_CON0, 1848 .ch_num_shift = 0, 1849 .ch_num_maskbit = 0x1f, 1850 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1851 .msb_shift = 19, 1852 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1853 .msb_end_shift = 19, 1854 }, 1855 [MT8195_AFE_MEMIF_DL6] = { 1856 .name = "DL6", 1857 .id = MT8195_AFE_MEMIF_DL6, 1858 .reg_ofs_base = AFE_DL6_BASE, 1859 .reg_ofs_cur = AFE_DL6_CUR, 1860 .reg_ofs_end = AFE_DL6_END, 1861 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1862 .fs_shift = 0, 1863 .fs_maskbit = 0x1f, 1864 .mono_reg = -1, 1865 .mono_shift = 0, 1866 .int_odd_flag_reg = -1, 1867 .int_odd_flag_shift = 0, 1868 .enable_reg = AFE_DAC_CON0, 1869 .enable_shift = 22, 1870 .hd_reg = AFE_DL6_CON0, 1871 .hd_shift = 5, 1872 .agent_disable_reg = AUDIO_TOP_CON5, 1873 .agent_disable_shift = 22, 1874 .ch_num_reg = AFE_DL6_CON0, 1875 .ch_num_shift = 0, 1876 .ch_num_maskbit = 0x1f, 1877 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1878 .msb_shift = 22, 1879 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1880 .msb_end_shift = 22, 1881 }, 1882 [MT8195_AFE_MEMIF_DL7] = { 1883 .name = "DL7", 1884 .id = MT8195_AFE_MEMIF_DL7, 1885 .reg_ofs_base = AFE_DL7_BASE, 1886 .reg_ofs_cur = AFE_DL7_CUR, 1887 .reg_ofs_end = AFE_DL7_END, 1888 .fs_reg = -1, 1889 .fs_shift = 0, 1890 .fs_maskbit = 0, 1891 .mono_reg = -1, 1892 .mono_shift = 0, 1893 .int_odd_flag_reg = -1, 1894 .int_odd_flag_shift = 0, 1895 .enable_reg = AFE_DAC_CON0, 1896 .enable_shift = 23, 1897 .hd_reg = AFE_DL7_CON0, 1898 .hd_shift = 5, 1899 .agent_disable_reg = AUDIO_TOP_CON5, 1900 .agent_disable_shift = 23, 1901 .ch_num_reg = AFE_DL7_CON0, 1902 .ch_num_shift = 0, 1903 .ch_num_maskbit = 0x1f, 1904 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1905 .msb_shift = 23, 1906 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1907 .msb_end_shift = 23, 1908 }, 1909 [MT8195_AFE_MEMIF_DL8] = { 1910 .name = "DL8", 1911 .id = MT8195_AFE_MEMIF_DL8, 1912 .reg_ofs_base = AFE_DL8_BASE, 1913 .reg_ofs_cur = AFE_DL8_CUR, 1914 .reg_ofs_end = AFE_DL8_END, 1915 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1916 .fs_shift = 10, 1917 .fs_maskbit = 0x1f, 1918 .mono_reg = -1, 1919 .mono_shift = 0, 1920 .int_odd_flag_reg = -1, 1921 .int_odd_flag_shift = 0, 1922 .enable_reg = AFE_DAC_CON0, 1923 .enable_shift = 24, 1924 .hd_reg = AFE_DL8_CON0, 1925 .hd_shift = 6, 1926 .agent_disable_reg = -1, 1927 .agent_disable_shift = 0, 1928 .ch_num_reg = AFE_DL8_CON0, 1929 .ch_num_shift = 0, 1930 .ch_num_maskbit = 0x3f, 1931 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1932 .msb_shift = 24, 1933 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1934 .msb_end_shift = 24, 1935 }, 1936 [MT8195_AFE_MEMIF_DL10] = { 1937 .name = "DL10", 1938 .id = MT8195_AFE_MEMIF_DL10, 1939 .reg_ofs_base = AFE_DL10_BASE, 1940 .reg_ofs_cur = AFE_DL10_CUR, 1941 .reg_ofs_end = AFE_DL10_END, 1942 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1943 .fs_shift = 20, 1944 .fs_maskbit = 0x1f, 1945 .mono_reg = -1, 1946 .mono_shift = 0, 1947 .int_odd_flag_reg = -1, 1948 .int_odd_flag_shift = 0, 1949 .enable_reg = AFE_DAC_CON0, 1950 .enable_shift = 26, 1951 .hd_reg = AFE_DL10_CON0, 1952 .hd_shift = 5, 1953 .agent_disable_reg = -1, 1954 .agent_disable_shift = 0, 1955 .ch_num_reg = AFE_DL10_CON0, 1956 .ch_num_shift = 0, 1957 .ch_num_maskbit = 0x1f, 1958 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1959 .msb_shift = 26, 1960 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1961 .msb_end_shift = 26, 1962 }, 1963 [MT8195_AFE_MEMIF_DL11] = { 1964 .name = "DL11", 1965 .id = MT8195_AFE_MEMIF_DL11, 1966 .reg_ofs_base = AFE_DL11_BASE, 1967 .reg_ofs_cur = AFE_DL11_CUR, 1968 .reg_ofs_end = AFE_DL11_END, 1969 .fs_reg = AFE_MEMIF_AGENT_FS_CON1, 1970 .fs_shift = 25, 1971 .fs_maskbit = 0x1f, 1972 .mono_reg = -1, 1973 .mono_shift = 0, 1974 .int_odd_flag_reg = -1, 1975 .int_odd_flag_shift = 0, 1976 .enable_reg = AFE_DAC_CON0, 1977 .enable_shift = 27, 1978 .hd_reg = AFE_DL11_CON0, 1979 .hd_shift = 7, 1980 .agent_disable_reg = AUDIO_TOP_CON5, 1981 .agent_disable_shift = 27, 1982 .ch_num_reg = AFE_DL11_CON0, 1983 .ch_num_shift = 0, 1984 .ch_num_maskbit = 0x7f, 1985 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 1986 .msb_shift = 27, 1987 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 1988 .msb_end_shift = 27, 1989 }, 1990 [MT8195_AFE_MEMIF_UL1] = { 1991 .name = "UL1", 1992 .id = MT8195_AFE_MEMIF_UL1, 1993 .reg_ofs_base = AFE_UL1_BASE, 1994 .reg_ofs_cur = AFE_UL1_CUR, 1995 .reg_ofs_end = AFE_UL1_END, 1996 .fs_reg = -1, 1997 .fs_shift = 0, 1998 .fs_maskbit = 0, 1999 .mono_reg = AFE_UL1_CON0, 2000 .mono_shift = 1, 2001 .int_odd_flag_reg = AFE_UL1_CON0, 2002 .int_odd_flag_shift = 0, 2003 .enable_reg = AFE_DAC_CON0, 2004 .enable_shift = 1, 2005 .hd_reg = AFE_UL1_CON0, 2006 .hd_shift = 5, 2007 .agent_disable_reg = AUDIO_TOP_CON5, 2008 .agent_disable_shift = 0, 2009 .ch_num_reg = -1, 2010 .ch_num_shift = 0, 2011 .ch_num_maskbit = 0, 2012 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2013 .msb_shift = 0, 2014 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2015 .msb_end_shift = 0, 2016 }, 2017 [MT8195_AFE_MEMIF_UL2] = { 2018 .name = "UL2", 2019 .id = MT8195_AFE_MEMIF_UL2, 2020 .reg_ofs_base = AFE_UL2_BASE, 2021 .reg_ofs_cur = AFE_UL2_CUR, 2022 .reg_ofs_end = AFE_UL2_END, 2023 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2024 .fs_shift = 5, 2025 .fs_maskbit = 0x1f, 2026 .mono_reg = AFE_UL2_CON0, 2027 .mono_shift = 1, 2028 .int_odd_flag_reg = AFE_UL2_CON0, 2029 .int_odd_flag_shift = 0, 2030 .enable_reg = AFE_DAC_CON0, 2031 .enable_shift = 2, 2032 .hd_reg = AFE_UL2_CON0, 2033 .hd_shift = 5, 2034 .agent_disable_reg = AUDIO_TOP_CON5, 2035 .agent_disable_shift = 1, 2036 .ch_num_reg = -1, 2037 .ch_num_shift = 0, 2038 .ch_num_maskbit = 0, 2039 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2040 .msb_shift = 1, 2041 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2042 .msb_end_shift = 1, 2043 }, 2044 [MT8195_AFE_MEMIF_UL3] = { 2045 .name = "UL3", 2046 .id = MT8195_AFE_MEMIF_UL3, 2047 .reg_ofs_base = AFE_UL3_BASE, 2048 .reg_ofs_cur = AFE_UL3_CUR, 2049 .reg_ofs_end = AFE_UL3_END, 2050 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2051 .fs_shift = 10, 2052 .fs_maskbit = 0x1f, 2053 .mono_reg = AFE_UL3_CON0, 2054 .mono_shift = 1, 2055 .int_odd_flag_reg = AFE_UL3_CON0, 2056 .int_odd_flag_shift = 0, 2057 .enable_reg = AFE_DAC_CON0, 2058 .enable_shift = 3, 2059 .hd_reg = AFE_UL3_CON0, 2060 .hd_shift = 5, 2061 .agent_disable_reg = AUDIO_TOP_CON5, 2062 .agent_disable_shift = 2, 2063 .ch_num_reg = -1, 2064 .ch_num_shift = 0, 2065 .ch_num_maskbit = 0, 2066 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2067 .msb_shift = 2, 2068 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2069 .msb_end_shift = 2, 2070 }, 2071 [MT8195_AFE_MEMIF_UL4] = { 2072 .name = "UL4", 2073 .id = MT8195_AFE_MEMIF_UL4, 2074 .reg_ofs_base = AFE_UL4_BASE, 2075 .reg_ofs_cur = AFE_UL4_CUR, 2076 .reg_ofs_end = AFE_UL4_END, 2077 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2078 .fs_shift = 15, 2079 .fs_maskbit = 0x1f, 2080 .mono_reg = AFE_UL4_CON0, 2081 .mono_shift = 1, 2082 .int_odd_flag_reg = AFE_UL4_CON0, 2083 .int_odd_flag_shift = 0, 2084 .enable_reg = AFE_DAC_CON0, 2085 .enable_shift = 4, 2086 .hd_reg = AFE_UL4_CON0, 2087 .hd_shift = 5, 2088 .agent_disable_reg = AUDIO_TOP_CON5, 2089 .agent_disable_shift = 3, 2090 .ch_num_reg = -1, 2091 .ch_num_shift = 0, 2092 .ch_num_maskbit = 0, 2093 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2094 .msb_shift = 3, 2095 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2096 .msb_end_shift = 3, 2097 }, 2098 [MT8195_AFE_MEMIF_UL5] = { 2099 .name = "UL5", 2100 .id = MT8195_AFE_MEMIF_UL5, 2101 .reg_ofs_base = AFE_UL5_BASE, 2102 .reg_ofs_cur = AFE_UL5_CUR, 2103 .reg_ofs_end = AFE_UL5_END, 2104 .fs_reg = AFE_MEMIF_AGENT_FS_CON2, 2105 .fs_shift = 20, 2106 .fs_maskbit = 0x1f, 2107 .mono_reg = AFE_UL5_CON0, 2108 .mono_shift = 1, 2109 .int_odd_flag_reg = AFE_UL5_CON0, 2110 .int_odd_flag_shift = 0, 2111 .enable_reg = AFE_DAC_CON0, 2112 .enable_shift = 5, 2113 .hd_reg = AFE_UL5_CON0, 2114 .hd_shift = 5, 2115 .agent_disable_reg = AUDIO_TOP_CON5, 2116 .agent_disable_shift = 4, 2117 .ch_num_reg = -1, 2118 .ch_num_shift = 0, 2119 .ch_num_maskbit = 0, 2120 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2121 .msb_shift = 4, 2122 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2123 .msb_end_shift = 4, 2124 }, 2125 [MT8195_AFE_MEMIF_UL6] = { 2126 .name = "UL6", 2127 .id = MT8195_AFE_MEMIF_UL6, 2128 .reg_ofs_base = AFE_UL6_BASE, 2129 .reg_ofs_cur = AFE_UL6_CUR, 2130 .reg_ofs_end = AFE_UL6_END, 2131 .fs_reg = -1, 2132 .fs_shift = 0, 2133 .fs_maskbit = 0, 2134 .mono_reg = AFE_UL6_CON0, 2135 .mono_shift = 1, 2136 .int_odd_flag_reg = AFE_UL6_CON0, 2137 .int_odd_flag_shift = 0, 2138 .enable_reg = AFE_DAC_CON0, 2139 .enable_shift = 6, 2140 .hd_reg = AFE_UL6_CON0, 2141 .hd_shift = 5, 2142 .agent_disable_reg = AUDIO_TOP_CON5, 2143 .agent_disable_shift = 5, 2144 .ch_num_reg = -1, 2145 .ch_num_shift = 0, 2146 .ch_num_maskbit = 0, 2147 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2148 .msb_shift = 5, 2149 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2150 .msb_end_shift = 5, 2151 }, 2152 [MT8195_AFE_MEMIF_UL8] = { 2153 .name = "UL8", 2154 .id = MT8195_AFE_MEMIF_UL8, 2155 .reg_ofs_base = AFE_UL8_BASE, 2156 .reg_ofs_cur = AFE_UL8_CUR, 2157 .reg_ofs_end = AFE_UL8_END, 2158 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2159 .fs_shift = 5, 2160 .fs_maskbit = 0x1f, 2161 .mono_reg = AFE_UL8_CON0, 2162 .mono_shift = 1, 2163 .int_odd_flag_reg = AFE_UL8_CON0, 2164 .int_odd_flag_shift = 0, 2165 .enable_reg = AFE_DAC_CON0, 2166 .enable_shift = 8, 2167 .hd_reg = AFE_UL8_CON0, 2168 .hd_shift = 5, 2169 .agent_disable_reg = AUDIO_TOP_CON5, 2170 .agent_disable_shift = 7, 2171 .ch_num_reg = -1, 2172 .ch_num_shift = 0, 2173 .ch_num_maskbit = 0, 2174 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2175 .msb_shift = 7, 2176 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2177 .msb_end_shift = 7, 2178 }, 2179 [MT8195_AFE_MEMIF_UL9] = { 2180 .name = "UL9", 2181 .id = MT8195_AFE_MEMIF_UL9, 2182 .reg_ofs_base = AFE_UL9_BASE, 2183 .reg_ofs_cur = AFE_UL9_CUR, 2184 .reg_ofs_end = AFE_UL9_END, 2185 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2186 .fs_shift = 10, 2187 .fs_maskbit = 0x1f, 2188 .mono_reg = AFE_UL9_CON0, 2189 .mono_shift = 1, 2190 .int_odd_flag_reg = AFE_UL9_CON0, 2191 .int_odd_flag_shift = 0, 2192 .enable_reg = AFE_DAC_CON0, 2193 .enable_shift = 9, 2194 .hd_reg = AFE_UL9_CON0, 2195 .hd_shift = 5, 2196 .agent_disable_reg = AUDIO_TOP_CON5, 2197 .agent_disable_shift = 8, 2198 .ch_num_reg = -1, 2199 .ch_num_shift = 0, 2200 .ch_num_maskbit = 0, 2201 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2202 .msb_shift = 8, 2203 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2204 .msb_end_shift = 8, 2205 }, 2206 [MT8195_AFE_MEMIF_UL10] = { 2207 .name = "UL10", 2208 .id = MT8195_AFE_MEMIF_UL10, 2209 .reg_ofs_base = AFE_UL10_BASE, 2210 .reg_ofs_cur = AFE_UL10_CUR, 2211 .reg_ofs_end = AFE_UL10_END, 2212 .fs_reg = AFE_MEMIF_AGENT_FS_CON3, 2213 .fs_shift = 15, 2214 .fs_maskbit = 0x1f, 2215 .mono_reg = AFE_UL10_CON0, 2216 .mono_shift = 1, 2217 .int_odd_flag_reg = AFE_UL10_CON0, 2218 .int_odd_flag_shift = 0, 2219 .enable_reg = AFE_DAC_CON0, 2220 .enable_shift = 10, 2221 .hd_reg = AFE_UL10_CON0, 2222 .hd_shift = 5, 2223 .agent_disable_reg = AUDIO_TOP_CON5, 2224 .agent_disable_shift = 9, 2225 .ch_num_reg = -1, 2226 .ch_num_shift = 0, 2227 .ch_num_maskbit = 0, 2228 .msb_reg = AFE_NORMAL_BASE_ADR_MSB, 2229 .msb_shift = 9, 2230 .msb_end_reg = AFE_NORMAL_END_ADR_MSB, 2231 .msb_end_shift = 9, 2232 }, 2233 }; 2234 2235 static const struct mtk_base_irq_data irq_data_array[MT8195_AFE_IRQ_NUM] = { 2236 [MT8195_AFE_IRQ_1] = { 2237 .id = MT8195_AFE_IRQ_1, 2238 .irq_cnt_reg = -1, 2239 .irq_cnt_shift = 0, 2240 .irq_cnt_maskbit = 0, 2241 .irq_fs_reg = -1, 2242 .irq_fs_shift = 0, 2243 .irq_fs_maskbit = 0, 2244 .irq_en_reg = AFE_IRQ1_CON, 2245 .irq_en_shift = 31, 2246 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2247 .irq_clr_shift = 0, 2248 .irq_status_shift = 16, 2249 }, 2250 [MT8195_AFE_IRQ_2] = { 2251 .id = MT8195_AFE_IRQ_2, 2252 .irq_cnt_reg = -1, 2253 .irq_cnt_shift = 0, 2254 .irq_cnt_maskbit = 0, 2255 .irq_fs_reg = -1, 2256 .irq_fs_shift = 0, 2257 .irq_fs_maskbit = 0, 2258 .irq_en_reg = AFE_IRQ2_CON, 2259 .irq_en_shift = 31, 2260 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2261 .irq_clr_shift = 1, 2262 .irq_status_shift = 17, 2263 }, 2264 [MT8195_AFE_IRQ_3] = { 2265 .id = MT8195_AFE_IRQ_3, 2266 .irq_cnt_reg = AFE_IRQ3_CON, 2267 .irq_cnt_shift = 0, 2268 .irq_cnt_maskbit = 0xffffff, 2269 .irq_fs_reg = -1, 2270 .irq_fs_shift = 0, 2271 .irq_fs_maskbit = 0, 2272 .irq_en_reg = AFE_IRQ3_CON, 2273 .irq_en_shift = 31, 2274 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2275 .irq_clr_shift = 2, 2276 .irq_status_shift = 18, 2277 }, 2278 [MT8195_AFE_IRQ_8] = { 2279 .id = MT8195_AFE_IRQ_8, 2280 .irq_cnt_reg = -1, 2281 .irq_cnt_shift = 0, 2282 .irq_cnt_maskbit = 0, 2283 .irq_fs_reg = -1, 2284 .irq_fs_shift = 0, 2285 .irq_fs_maskbit = 0, 2286 .irq_en_reg = AFE_IRQ8_CON, 2287 .irq_en_shift = 31, 2288 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2289 .irq_clr_shift = 7, 2290 .irq_status_shift = 23, 2291 }, 2292 [MT8195_AFE_IRQ_9] = { 2293 .id = MT8195_AFE_IRQ_9, 2294 .irq_cnt_reg = AFE_IRQ9_CON, 2295 .irq_cnt_shift = 0, 2296 .irq_cnt_maskbit = 0xffffff, 2297 .irq_fs_reg = -1, 2298 .irq_fs_shift = 0, 2299 .irq_fs_maskbit = 0, 2300 .irq_en_reg = AFE_IRQ9_CON, 2301 .irq_en_shift = 31, 2302 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2303 .irq_clr_shift = 8, 2304 .irq_status_shift = 24, 2305 }, 2306 [MT8195_AFE_IRQ_10] = { 2307 .id = MT8195_AFE_IRQ_10, 2308 .irq_cnt_reg = -1, 2309 .irq_cnt_shift = 0, 2310 .irq_cnt_maskbit = 0, 2311 .irq_fs_reg = -1, 2312 .irq_fs_shift = 0, 2313 .irq_fs_maskbit = 0, 2314 .irq_en_reg = AFE_IRQ10_CON, 2315 .irq_en_shift = 31, 2316 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2317 .irq_clr_shift = 9, 2318 .irq_status_shift = 25, 2319 }, 2320 [MT8195_AFE_IRQ_13] = { 2321 .id = MT8195_AFE_IRQ_13, 2322 .irq_cnt_reg = ASYS_IRQ1_CON, 2323 .irq_cnt_shift = 0, 2324 .irq_cnt_maskbit = 0xffffff, 2325 .irq_fs_reg = ASYS_IRQ1_CON, 2326 .irq_fs_shift = 24, 2327 .irq_fs_maskbit = 0x1ffff, 2328 .irq_en_reg = ASYS_IRQ1_CON, 2329 .irq_en_shift = 31, 2330 .irq_clr_reg = ASYS_IRQ_CLR, 2331 .irq_clr_shift = 0, 2332 .irq_status_shift = 0, 2333 }, 2334 [MT8195_AFE_IRQ_14] = { 2335 .id = MT8195_AFE_IRQ_14, 2336 .irq_cnt_reg = ASYS_IRQ2_CON, 2337 .irq_cnt_shift = 0, 2338 .irq_cnt_maskbit = 0xffffff, 2339 .irq_fs_reg = ASYS_IRQ2_CON, 2340 .irq_fs_shift = 24, 2341 .irq_fs_maskbit = 0x1ffff, 2342 .irq_en_reg = ASYS_IRQ2_CON, 2343 .irq_en_shift = 31, 2344 .irq_clr_reg = ASYS_IRQ_CLR, 2345 .irq_clr_shift = 1, 2346 .irq_status_shift = 1, 2347 }, 2348 [MT8195_AFE_IRQ_15] = { 2349 .id = MT8195_AFE_IRQ_15, 2350 .irq_cnt_reg = ASYS_IRQ3_CON, 2351 .irq_cnt_shift = 0, 2352 .irq_cnt_maskbit = 0xffffff, 2353 .irq_fs_reg = ASYS_IRQ3_CON, 2354 .irq_fs_shift = 24, 2355 .irq_fs_maskbit = 0x1ffff, 2356 .irq_en_reg = ASYS_IRQ3_CON, 2357 .irq_en_shift = 31, 2358 .irq_clr_reg = ASYS_IRQ_CLR, 2359 .irq_clr_shift = 2, 2360 .irq_status_shift = 2, 2361 }, 2362 [MT8195_AFE_IRQ_16] = { 2363 .id = MT8195_AFE_IRQ_16, 2364 .irq_cnt_reg = ASYS_IRQ4_CON, 2365 .irq_cnt_shift = 0, 2366 .irq_cnt_maskbit = 0xffffff, 2367 .irq_fs_reg = ASYS_IRQ4_CON, 2368 .irq_fs_shift = 24, 2369 .irq_fs_maskbit = 0x1ffff, 2370 .irq_en_reg = ASYS_IRQ4_CON, 2371 .irq_en_shift = 31, 2372 .irq_clr_reg = ASYS_IRQ_CLR, 2373 .irq_clr_shift = 3, 2374 .irq_status_shift = 3, 2375 }, 2376 [MT8195_AFE_IRQ_17] = { 2377 .id = MT8195_AFE_IRQ_17, 2378 .irq_cnt_reg = ASYS_IRQ5_CON, 2379 .irq_cnt_shift = 0, 2380 .irq_cnt_maskbit = 0xffffff, 2381 .irq_fs_reg = ASYS_IRQ5_CON, 2382 .irq_fs_shift = 24, 2383 .irq_fs_maskbit = 0x1ffff, 2384 .irq_en_reg = ASYS_IRQ5_CON, 2385 .irq_en_shift = 31, 2386 .irq_clr_reg = ASYS_IRQ_CLR, 2387 .irq_clr_shift = 4, 2388 .irq_status_shift = 4, 2389 }, 2390 [MT8195_AFE_IRQ_18] = { 2391 .id = MT8195_AFE_IRQ_18, 2392 .irq_cnt_reg = ASYS_IRQ6_CON, 2393 .irq_cnt_shift = 0, 2394 .irq_cnt_maskbit = 0xffffff, 2395 .irq_fs_reg = ASYS_IRQ6_CON, 2396 .irq_fs_shift = 24, 2397 .irq_fs_maskbit = 0x1ffff, 2398 .irq_en_reg = ASYS_IRQ6_CON, 2399 .irq_en_shift = 31, 2400 .irq_clr_reg = ASYS_IRQ_CLR, 2401 .irq_clr_shift = 5, 2402 .irq_status_shift = 5, 2403 }, 2404 [MT8195_AFE_IRQ_19] = { 2405 .id = MT8195_AFE_IRQ_19, 2406 .irq_cnt_reg = ASYS_IRQ7_CON, 2407 .irq_cnt_shift = 0, 2408 .irq_cnt_maskbit = 0xffffff, 2409 .irq_fs_reg = ASYS_IRQ7_CON, 2410 .irq_fs_shift = 24, 2411 .irq_fs_maskbit = 0x1ffff, 2412 .irq_en_reg = ASYS_IRQ7_CON, 2413 .irq_en_shift = 31, 2414 .irq_clr_reg = ASYS_IRQ_CLR, 2415 .irq_clr_shift = 6, 2416 .irq_status_shift = 6, 2417 }, 2418 [MT8195_AFE_IRQ_20] = { 2419 .id = MT8195_AFE_IRQ_20, 2420 .irq_cnt_reg = ASYS_IRQ8_CON, 2421 .irq_cnt_shift = 0, 2422 .irq_cnt_maskbit = 0xffffff, 2423 .irq_fs_reg = ASYS_IRQ8_CON, 2424 .irq_fs_shift = 24, 2425 .irq_fs_maskbit = 0x1ffff, 2426 .irq_en_reg = ASYS_IRQ8_CON, 2427 .irq_en_shift = 31, 2428 .irq_clr_reg = ASYS_IRQ_CLR, 2429 .irq_clr_shift = 7, 2430 .irq_status_shift = 7, 2431 }, 2432 [MT8195_AFE_IRQ_21] = { 2433 .id = MT8195_AFE_IRQ_21, 2434 .irq_cnt_reg = ASYS_IRQ9_CON, 2435 .irq_cnt_shift = 0, 2436 .irq_cnt_maskbit = 0xffffff, 2437 .irq_fs_reg = ASYS_IRQ9_CON, 2438 .irq_fs_shift = 24, 2439 .irq_fs_maskbit = 0x1ffff, 2440 .irq_en_reg = ASYS_IRQ9_CON, 2441 .irq_en_shift = 31, 2442 .irq_clr_reg = ASYS_IRQ_CLR, 2443 .irq_clr_shift = 8, 2444 .irq_status_shift = 8, 2445 }, 2446 [MT8195_AFE_IRQ_22] = { 2447 .id = MT8195_AFE_IRQ_22, 2448 .irq_cnt_reg = ASYS_IRQ10_CON, 2449 .irq_cnt_shift = 0, 2450 .irq_cnt_maskbit = 0xffffff, 2451 .irq_fs_reg = ASYS_IRQ10_CON, 2452 .irq_fs_shift = 24, 2453 .irq_fs_maskbit = 0x1ffff, 2454 .irq_en_reg = ASYS_IRQ10_CON, 2455 .irq_en_shift = 31, 2456 .irq_clr_reg = ASYS_IRQ_CLR, 2457 .irq_clr_shift = 9, 2458 .irq_status_shift = 9, 2459 }, 2460 [MT8195_AFE_IRQ_23] = { 2461 .id = MT8195_AFE_IRQ_23, 2462 .irq_cnt_reg = ASYS_IRQ11_CON, 2463 .irq_cnt_shift = 0, 2464 .irq_cnt_maskbit = 0xffffff, 2465 .irq_fs_reg = ASYS_IRQ11_CON, 2466 .irq_fs_shift = 24, 2467 .irq_fs_maskbit = 0x1ffff, 2468 .irq_en_reg = ASYS_IRQ11_CON, 2469 .irq_en_shift = 31, 2470 .irq_clr_reg = ASYS_IRQ_CLR, 2471 .irq_clr_shift = 10, 2472 .irq_status_shift = 10, 2473 }, 2474 [MT8195_AFE_IRQ_24] = { 2475 .id = MT8195_AFE_IRQ_24, 2476 .irq_cnt_reg = ASYS_IRQ12_CON, 2477 .irq_cnt_shift = 0, 2478 .irq_cnt_maskbit = 0xffffff, 2479 .irq_fs_reg = ASYS_IRQ12_CON, 2480 .irq_fs_shift = 24, 2481 .irq_fs_maskbit = 0x1ffff, 2482 .irq_en_reg = ASYS_IRQ12_CON, 2483 .irq_en_shift = 31, 2484 .irq_clr_reg = ASYS_IRQ_CLR, 2485 .irq_clr_shift = 11, 2486 .irq_status_shift = 11, 2487 }, 2488 [MT8195_AFE_IRQ_25] = { 2489 .id = MT8195_AFE_IRQ_25, 2490 .irq_cnt_reg = ASYS_IRQ13_CON, 2491 .irq_cnt_shift = 0, 2492 .irq_cnt_maskbit = 0xffffff, 2493 .irq_fs_reg = ASYS_IRQ13_CON, 2494 .irq_fs_shift = 24, 2495 .irq_fs_maskbit = 0x1ffff, 2496 .irq_en_reg = ASYS_IRQ13_CON, 2497 .irq_en_shift = 31, 2498 .irq_clr_reg = ASYS_IRQ_CLR, 2499 .irq_clr_shift = 12, 2500 .irq_status_shift = 12, 2501 }, 2502 [MT8195_AFE_IRQ_26] = { 2503 .id = MT8195_AFE_IRQ_26, 2504 .irq_cnt_reg = ASYS_IRQ14_CON, 2505 .irq_cnt_shift = 0, 2506 .irq_cnt_maskbit = 0xffffff, 2507 .irq_fs_reg = ASYS_IRQ14_CON, 2508 .irq_fs_shift = 24, 2509 .irq_fs_maskbit = 0x1ffff, 2510 .irq_en_reg = ASYS_IRQ14_CON, 2511 .irq_en_shift = 31, 2512 .irq_clr_reg = ASYS_IRQ_CLR, 2513 .irq_clr_shift = 13, 2514 .irq_status_shift = 13, 2515 }, 2516 [MT8195_AFE_IRQ_27] = { 2517 .id = MT8195_AFE_IRQ_27, 2518 .irq_cnt_reg = ASYS_IRQ15_CON, 2519 .irq_cnt_shift = 0, 2520 .irq_cnt_maskbit = 0xffffff, 2521 .irq_fs_reg = ASYS_IRQ15_CON, 2522 .irq_fs_shift = 24, 2523 .irq_fs_maskbit = 0x1ffff, 2524 .irq_en_reg = ASYS_IRQ15_CON, 2525 .irq_en_shift = 31, 2526 .irq_clr_reg = ASYS_IRQ_CLR, 2527 .irq_clr_shift = 14, 2528 .irq_status_shift = 14, 2529 }, 2530 [MT8195_AFE_IRQ_28] = { 2531 .id = MT8195_AFE_IRQ_28, 2532 .irq_cnt_reg = ASYS_IRQ16_CON, 2533 .irq_cnt_shift = 0, 2534 .irq_cnt_maskbit = 0xffffff, 2535 .irq_fs_reg = ASYS_IRQ16_CON, 2536 .irq_fs_shift = 24, 2537 .irq_fs_maskbit = 0x1ffff, 2538 .irq_en_reg = ASYS_IRQ16_CON, 2539 .irq_en_shift = 31, 2540 .irq_clr_reg = ASYS_IRQ_CLR, 2541 .irq_clr_shift = 15, 2542 .irq_status_shift = 15, 2543 }, 2544 }; 2545 2546 static const int mt8195_afe_memif_const_irqs[MT8195_AFE_MEMIF_NUM] = { 2547 [MT8195_AFE_MEMIF_DL2] = MT8195_AFE_IRQ_13, 2548 [MT8195_AFE_MEMIF_DL3] = MT8195_AFE_IRQ_14, 2549 [MT8195_AFE_MEMIF_DL6] = MT8195_AFE_IRQ_15, 2550 [MT8195_AFE_MEMIF_DL7] = MT8195_AFE_IRQ_1, 2551 [MT8195_AFE_MEMIF_DL8] = MT8195_AFE_IRQ_16, 2552 [MT8195_AFE_MEMIF_DL10] = MT8195_AFE_IRQ_17, 2553 [MT8195_AFE_MEMIF_DL11] = MT8195_AFE_IRQ_18, 2554 [MT8195_AFE_MEMIF_UL1] = MT8195_AFE_IRQ_3, 2555 [MT8195_AFE_MEMIF_UL2] = MT8195_AFE_IRQ_19, 2556 [MT8195_AFE_MEMIF_UL3] = MT8195_AFE_IRQ_20, 2557 [MT8195_AFE_MEMIF_UL4] = MT8195_AFE_IRQ_21, 2558 [MT8195_AFE_MEMIF_UL5] = MT8195_AFE_IRQ_22, 2559 [MT8195_AFE_MEMIF_UL6] = MT8195_AFE_IRQ_9, 2560 [MT8195_AFE_MEMIF_UL8] = MT8195_AFE_IRQ_23, 2561 [MT8195_AFE_MEMIF_UL9] = MT8195_AFE_IRQ_24, 2562 [MT8195_AFE_MEMIF_UL10] = MT8195_AFE_IRQ_25, 2563 }; 2564 2565 static bool mt8195_is_volatile_reg(struct device *dev, unsigned int reg) 2566 { 2567 /* these auto-gen reg has read-only bit, so put it as volatile */ 2568 /* volatile reg cannot be cached, so cannot be set when power off */ 2569 switch (reg) { 2570 case AUDIO_TOP_CON0: 2571 case AUDIO_TOP_CON1: 2572 case AUDIO_TOP_CON3: 2573 case AUDIO_TOP_CON4: 2574 case AUDIO_TOP_CON5: 2575 case AUDIO_TOP_CON6: 2576 case ASYS_IRQ_CLR: 2577 case ASYS_IRQ_STATUS: 2578 case ASYS_IRQ_MON1: 2579 case ASYS_IRQ_MON2: 2580 case AFE_IRQ_MCU_CLR: 2581 case AFE_IRQ_STATUS: 2582 case AFE_IRQ3_CON_MON: 2583 case AFE_IRQ_MCU_MON2: 2584 case ADSP_IRQ_STATUS: 2585 case AFE_APLL_TUNER_CFG: 2586 case AFE_APLL_TUNER_CFG1: 2587 case AUDIO_TOP_STA0: 2588 case AUDIO_TOP_STA1: 2589 case AFE_GAIN1_CUR: 2590 case AFE_GAIN2_CUR: 2591 case AFE_IEC_BURST_INFO: 2592 case AFE_IEC_CHL_STAT0: 2593 case AFE_IEC_CHL_STAT1: 2594 case AFE_IEC_CHR_STAT0: 2595 case AFE_IEC_CHR_STAT1: 2596 case AFE_SPDIFIN_CHSTS1: 2597 case AFE_SPDIFIN_CHSTS2: 2598 case AFE_SPDIFIN_CHSTS3: 2599 case AFE_SPDIFIN_CHSTS4: 2600 case AFE_SPDIFIN_CHSTS5: 2601 case AFE_SPDIFIN_CHSTS6: 2602 case AFE_SPDIFIN_DEBUG1: 2603 case AFE_SPDIFIN_DEBUG2: 2604 case AFE_SPDIFIN_DEBUG3: 2605 case AFE_SPDIFIN_DEBUG4: 2606 case AFE_SPDIFIN_EC: 2607 case AFE_SPDIFIN_CKLOCK_CFG: 2608 case AFE_SPDIFIN_BR_DBG1: 2609 case AFE_SPDIFIN_CKFBDIV: 2610 case AFE_SPDIFIN_INT_EXT: 2611 case AFE_SPDIFIN_INT_EXT2: 2612 case SPDIFIN_FREQ_STATUS: 2613 case SPDIFIN_USERCODE1: 2614 case SPDIFIN_USERCODE2: 2615 case SPDIFIN_USERCODE3: 2616 case SPDIFIN_USERCODE4: 2617 case SPDIFIN_USERCODE5: 2618 case SPDIFIN_USERCODE6: 2619 case SPDIFIN_USERCODE7: 2620 case SPDIFIN_USERCODE8: 2621 case SPDIFIN_USERCODE9: 2622 case SPDIFIN_USERCODE10: 2623 case SPDIFIN_USERCODE11: 2624 case SPDIFIN_USERCODE12: 2625 case AFE_SPDIFIN_APLL_TUNER_CFG: 2626 case AFE_LINEIN_APLL_TUNER_MON: 2627 case AFE_EARC_APLL_TUNER_MON: 2628 case AFE_CM0_MON: 2629 case AFE_CM1_MON: 2630 case AFE_CM2_MON: 2631 case AFE_MPHONE_MULTI_DET_MON0: 2632 case AFE_MPHONE_MULTI_DET_MON1: 2633 case AFE_MPHONE_MULTI_DET_MON2: 2634 case AFE_MPHONE_MULTI2_DET_MON0: 2635 case AFE_MPHONE_MULTI2_DET_MON1: 2636 case AFE_MPHONE_MULTI2_DET_MON2: 2637 case AFE_ADDA_MTKAIF_MON0: 2638 case AFE_ADDA_MTKAIF_MON1: 2639 case AFE_AUD_PAD_TOP: 2640 case AFE_ADDA6_MTKAIF_MON0: 2641 case AFE_ADDA6_MTKAIF_MON1: 2642 case AFE_ADDA6_SRC_DEBUG_MON0: 2643 case AFE_ADDA6_UL_SRC_MON0: 2644 case AFE_ADDA6_UL_SRC_MON1: 2645 case AFE_ASRC11_NEW_CON8: 2646 case AFE_ASRC11_NEW_CON9: 2647 case AFE_ASRC12_NEW_CON8: 2648 case AFE_ASRC12_NEW_CON9: 2649 case AFE_LRCK_CNT: 2650 case AFE_DAC_MON0: 2651 case AFE_DL2_CUR: 2652 case AFE_DL3_CUR: 2653 case AFE_DL6_CUR: 2654 case AFE_DL7_CUR: 2655 case AFE_DL8_CUR: 2656 case AFE_DL10_CUR: 2657 case AFE_DL11_CUR: 2658 case AFE_UL1_CUR: 2659 case AFE_UL2_CUR: 2660 case AFE_UL3_CUR: 2661 case AFE_UL4_CUR: 2662 case AFE_UL5_CUR: 2663 case AFE_UL6_CUR: 2664 case AFE_UL8_CUR: 2665 case AFE_UL9_CUR: 2666 case AFE_UL10_CUR: 2667 case AFE_DL8_CHK_SUM1: 2668 case AFE_DL8_CHK_SUM2: 2669 case AFE_DL8_CHK_SUM3: 2670 case AFE_DL8_CHK_SUM4: 2671 case AFE_DL8_CHK_SUM5: 2672 case AFE_DL8_CHK_SUM6: 2673 case AFE_DL10_CHK_SUM1: 2674 case AFE_DL10_CHK_SUM2: 2675 case AFE_DL10_CHK_SUM3: 2676 case AFE_DL10_CHK_SUM4: 2677 case AFE_DL10_CHK_SUM5: 2678 case AFE_DL10_CHK_SUM6: 2679 case AFE_DL11_CHK_SUM1: 2680 case AFE_DL11_CHK_SUM2: 2681 case AFE_DL11_CHK_SUM3: 2682 case AFE_DL11_CHK_SUM4: 2683 case AFE_DL11_CHK_SUM5: 2684 case AFE_DL11_CHK_SUM6: 2685 case AFE_UL1_CHK_SUM1: 2686 case AFE_UL1_CHK_SUM2: 2687 case AFE_UL2_CHK_SUM1: 2688 case AFE_UL2_CHK_SUM2: 2689 case AFE_UL3_CHK_SUM1: 2690 case AFE_UL3_CHK_SUM2: 2691 case AFE_UL4_CHK_SUM1: 2692 case AFE_UL4_CHK_SUM2: 2693 case AFE_UL5_CHK_SUM1: 2694 case AFE_UL5_CHK_SUM2: 2695 case AFE_UL6_CHK_SUM1: 2696 case AFE_UL6_CHK_SUM2: 2697 case AFE_UL8_CHK_SUM1: 2698 case AFE_UL8_CHK_SUM2: 2699 case AFE_DL2_CHK_SUM1: 2700 case AFE_DL2_CHK_SUM2: 2701 case AFE_DL3_CHK_SUM1: 2702 case AFE_DL3_CHK_SUM2: 2703 case AFE_DL6_CHK_SUM1: 2704 case AFE_DL6_CHK_SUM2: 2705 case AFE_DL7_CHK_SUM1: 2706 case AFE_DL7_CHK_SUM2: 2707 case AFE_UL9_CHK_SUM1: 2708 case AFE_UL9_CHK_SUM2: 2709 case AFE_BUS_MON1: 2710 case UL1_MOD2AGT_CNT_LAT: 2711 case UL2_MOD2AGT_CNT_LAT: 2712 case UL3_MOD2AGT_CNT_LAT: 2713 case UL4_MOD2AGT_CNT_LAT: 2714 case UL5_MOD2AGT_CNT_LAT: 2715 case UL6_MOD2AGT_CNT_LAT: 2716 case UL8_MOD2AGT_CNT_LAT: 2717 case UL9_MOD2AGT_CNT_LAT: 2718 case UL10_MOD2AGT_CNT_LAT: 2719 case AFE_MEMIF_BUF_FULL_MON: 2720 case AFE_MEMIF_BUF_MON1: 2721 case AFE_MEMIF_BUF_MON3: 2722 case AFE_MEMIF_BUF_MON4: 2723 case AFE_MEMIF_BUF_MON5: 2724 case AFE_MEMIF_BUF_MON6: 2725 case AFE_MEMIF_BUF_MON7: 2726 case AFE_MEMIF_BUF_MON8: 2727 case AFE_MEMIF_BUF_MON9: 2728 case AFE_MEMIF_BUF_MON10: 2729 case DL2_AGENT2MODULE_CNT: 2730 case DL3_AGENT2MODULE_CNT: 2731 case DL6_AGENT2MODULE_CNT: 2732 case DL7_AGENT2MODULE_CNT: 2733 case DL8_AGENT2MODULE_CNT: 2734 case DL10_AGENT2MODULE_CNT: 2735 case DL11_AGENT2MODULE_CNT: 2736 case UL1_MODULE2AGENT_CNT: 2737 case UL2_MODULE2AGENT_CNT: 2738 case UL3_MODULE2AGENT_CNT: 2739 case UL4_MODULE2AGENT_CNT: 2740 case UL5_MODULE2AGENT_CNT: 2741 case UL6_MODULE2AGENT_CNT: 2742 case UL8_MODULE2AGENT_CNT: 2743 case UL9_MODULE2AGENT_CNT: 2744 case UL10_MODULE2AGENT_CNT: 2745 case AFE_DMIC0_SRC_DEBUG_MON0: 2746 case AFE_DMIC0_UL_SRC_MON0: 2747 case AFE_DMIC0_UL_SRC_MON1: 2748 case AFE_DMIC1_SRC_DEBUG_MON0: 2749 case AFE_DMIC1_UL_SRC_MON0: 2750 case AFE_DMIC1_UL_SRC_MON1: 2751 case AFE_DMIC2_SRC_DEBUG_MON0: 2752 case AFE_DMIC2_UL_SRC_MON0: 2753 case AFE_DMIC2_UL_SRC_MON1: 2754 case AFE_DMIC3_SRC_DEBUG_MON0: 2755 case AFE_DMIC3_UL_SRC_MON0: 2756 case AFE_DMIC3_UL_SRC_MON1: 2757 case DMIC_GAIN1_CUR: 2758 case DMIC_GAIN2_CUR: 2759 case DMIC_GAIN3_CUR: 2760 case DMIC_GAIN4_CUR: 2761 case ETDM_IN1_MONITOR: 2762 case ETDM_IN2_MONITOR: 2763 case ETDM_OUT1_MONITOR: 2764 case ETDM_OUT2_MONITOR: 2765 case ETDM_OUT3_MONITOR: 2766 case AFE_ADDA_SRC_DEBUG_MON0: 2767 case AFE_ADDA_SRC_DEBUG_MON1: 2768 case AFE_ADDA_DL_SDM_FIFO_MON: 2769 case AFE_ADDA_DL_SRC_LCH_MON: 2770 case AFE_ADDA_DL_SRC_RCH_MON: 2771 case AFE_ADDA_DL_SDM_OUT_MON: 2772 case AFE_GASRC0_NEW_CON8: 2773 case AFE_GASRC0_NEW_CON9: 2774 case AFE_GASRC0_NEW_CON12: 2775 case AFE_GASRC1_NEW_CON8: 2776 case AFE_GASRC1_NEW_CON9: 2777 case AFE_GASRC1_NEW_CON12: 2778 case AFE_GASRC2_NEW_CON8: 2779 case AFE_GASRC2_NEW_CON9: 2780 case AFE_GASRC2_NEW_CON12: 2781 case AFE_GASRC3_NEW_CON8: 2782 case AFE_GASRC3_NEW_CON9: 2783 case AFE_GASRC3_NEW_CON12: 2784 case AFE_GASRC4_NEW_CON8: 2785 case AFE_GASRC4_NEW_CON9: 2786 case AFE_GASRC4_NEW_CON12: 2787 case AFE_GASRC5_NEW_CON8: 2788 case AFE_GASRC5_NEW_CON9: 2789 case AFE_GASRC5_NEW_CON12: 2790 case AFE_GASRC6_NEW_CON8: 2791 case AFE_GASRC6_NEW_CON9: 2792 case AFE_GASRC6_NEW_CON12: 2793 case AFE_GASRC7_NEW_CON8: 2794 case AFE_GASRC7_NEW_CON9: 2795 case AFE_GASRC7_NEW_CON12: 2796 case AFE_GASRC8_NEW_CON8: 2797 case AFE_GASRC8_NEW_CON9: 2798 case AFE_GASRC8_NEW_CON12: 2799 case AFE_GASRC9_NEW_CON8: 2800 case AFE_GASRC9_NEW_CON9: 2801 case AFE_GASRC9_NEW_CON12: 2802 case AFE_GASRC10_NEW_CON8: 2803 case AFE_GASRC10_NEW_CON9: 2804 case AFE_GASRC10_NEW_CON12: 2805 case AFE_GASRC11_NEW_CON8: 2806 case AFE_GASRC11_NEW_CON9: 2807 case AFE_GASRC11_NEW_CON12: 2808 case AFE_GASRC12_NEW_CON8: 2809 case AFE_GASRC12_NEW_CON9: 2810 case AFE_GASRC12_NEW_CON12: 2811 case AFE_GASRC13_NEW_CON8: 2812 case AFE_GASRC13_NEW_CON9: 2813 case AFE_GASRC13_NEW_CON12: 2814 case AFE_GASRC14_NEW_CON8: 2815 case AFE_GASRC14_NEW_CON9: 2816 case AFE_GASRC14_NEW_CON12: 2817 case AFE_GASRC15_NEW_CON8: 2818 case AFE_GASRC15_NEW_CON9: 2819 case AFE_GASRC15_NEW_CON12: 2820 case AFE_GASRC16_NEW_CON8: 2821 case AFE_GASRC16_NEW_CON9: 2822 case AFE_GASRC16_NEW_CON12: 2823 case AFE_GASRC17_NEW_CON8: 2824 case AFE_GASRC17_NEW_CON9: 2825 case AFE_GASRC17_NEW_CON12: 2826 case AFE_GASRC18_NEW_CON8: 2827 case AFE_GASRC18_NEW_CON9: 2828 case AFE_GASRC18_NEW_CON12: 2829 case AFE_GASRC19_NEW_CON8: 2830 case AFE_GASRC19_NEW_CON9: 2831 case AFE_GASRC19_NEW_CON12: 2832 return true; 2833 default: 2834 return false; 2835 }; 2836 } 2837 2838 static const struct regmap_config mt8195_afe_regmap_config = { 2839 .reg_bits = 32, 2840 .reg_stride = 4, 2841 .val_bits = 32, 2842 .volatile_reg = mt8195_is_volatile_reg, 2843 .max_register = AFE_MAX_REGISTER, 2844 .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1), 2845 .cache_type = REGCACHE_FLAT, 2846 }; 2847 2848 #define AFE_IRQ_CLR_BITS (0x387) 2849 #define ASYS_IRQ_CLR_BITS (0xffff) 2850 2851 static irqreturn_t mt8195_afe_irq_handler(int irq_id, void *dev_id) 2852 { 2853 struct mtk_base_afe *afe = dev_id; 2854 unsigned int val = 0; 2855 unsigned int asys_irq_clr_bits = 0; 2856 unsigned int afe_irq_clr_bits = 0; 2857 unsigned int irq_status_bits = 0; 2858 unsigned int irq_clr_bits = 0; 2859 unsigned int mcu_irq_mask = 0; 2860 int i = 0; 2861 int ret = 0; 2862 2863 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val); 2864 if (ret) { 2865 dev_info(afe->dev, "%s irq status err\n", __func__); 2866 afe_irq_clr_bits = AFE_IRQ_CLR_BITS; 2867 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS; 2868 goto err_irq; 2869 } 2870 2871 ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask); 2872 if (ret) { 2873 dev_info(afe->dev, "%s read irq mask err\n", __func__); 2874 afe_irq_clr_bits = AFE_IRQ_CLR_BITS; 2875 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS; 2876 goto err_irq; 2877 } 2878 2879 /* only clr cpu irq */ 2880 val &= mcu_irq_mask; 2881 2882 for (i = 0; i < MT8195_AFE_MEMIF_NUM; i++) { 2883 struct mtk_base_afe_memif *memif = &afe->memif[i]; 2884 struct mtk_base_irq_data const *irq_data; 2885 2886 if (memif->irq_usage < 0) 2887 continue; 2888 2889 irq_data = afe->irqs[memif->irq_usage].irq_data; 2890 2891 irq_status_bits = BIT(irq_data->irq_status_shift); 2892 irq_clr_bits = BIT(irq_data->irq_clr_shift); 2893 2894 if (!(val & irq_status_bits)) 2895 continue; 2896 2897 if (irq_data->irq_clr_reg == ASYS_IRQ_CLR) 2898 asys_irq_clr_bits |= irq_clr_bits; 2899 else 2900 afe_irq_clr_bits |= irq_clr_bits; 2901 2902 snd_pcm_period_elapsed(memif->substream); 2903 } 2904 2905 err_irq: 2906 /* clear irq */ 2907 if (asys_irq_clr_bits) 2908 regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits); 2909 if (afe_irq_clr_bits) 2910 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits); 2911 2912 return IRQ_HANDLED; 2913 } 2914 2915 static int mt8195_afe_runtime_suspend(struct device *dev) 2916 { 2917 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2918 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2919 2920 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2921 goto skip_regmap; 2922 2923 mt8195_afe_disable_main_clock(afe); 2924 2925 regcache_cache_only(afe->regmap, true); 2926 regcache_mark_dirty(afe->regmap); 2927 2928 skip_regmap: 2929 mt8195_afe_disable_reg_rw_clk(afe); 2930 2931 return 0; 2932 } 2933 2934 static int mt8195_afe_runtime_resume(struct device *dev) 2935 { 2936 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2937 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2938 2939 mt8195_afe_enable_reg_rw_clk(afe); 2940 2941 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2942 goto skip_regmap; 2943 2944 regcache_cache_only(afe->regmap, false); 2945 regcache_sync(afe->regmap); 2946 2947 mt8195_afe_enable_main_clock(afe); 2948 skip_regmap: 2949 return 0; 2950 } 2951 2952 static int mt8195_afe_component_probe(struct snd_soc_component *component) 2953 { 2954 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 2955 int ret = 0; 2956 2957 snd_soc_component_init_regmap(component, afe->regmap); 2958 2959 ret = mtk_afe_add_sub_dai_control(component); 2960 2961 return ret; 2962 } 2963 2964 static const struct snd_soc_component_driver mt8195_afe_component = { 2965 .name = AFE_PCM_NAME, 2966 .pointer = mtk_afe_pcm_pointer, 2967 .pcm_construct = mtk_afe_pcm_new, 2968 .probe = mt8195_afe_component_probe, 2969 }; 2970 2971 static int init_memif_priv_data(struct mtk_base_afe *afe) 2972 { 2973 struct mt8195_afe_private *afe_priv = afe->platform_priv; 2974 struct mtk_dai_memif_priv *memif_priv; 2975 int i; 2976 2977 for (i = MT8195_AFE_MEMIF_START; i < MT8195_AFE_MEMIF_END; i++) { 2978 memif_priv = devm_kzalloc(afe->dev, 2979 sizeof(struct mtk_dai_memif_priv), 2980 GFP_KERNEL); 2981 if (!memif_priv) 2982 return -ENOMEM; 2983 2984 afe_priv->dai_priv[i] = memif_priv; 2985 } 2986 2987 return 0; 2988 } 2989 2990 static int mt8195_dai_memif_register(struct mtk_base_afe *afe) 2991 { 2992 struct mtk_base_afe_dai *dai; 2993 2994 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2995 if (!dai) 2996 return -ENOMEM; 2997 2998 list_add(&dai->list, &afe->sub_dais); 2999 3000 dai->dai_drivers = mt8195_memif_dai_driver; 3001 dai->num_dai_drivers = ARRAY_SIZE(mt8195_memif_dai_driver); 3002 3003 dai->dapm_widgets = mt8195_memif_widgets; 3004 dai->num_dapm_widgets = ARRAY_SIZE(mt8195_memif_widgets); 3005 dai->dapm_routes = mt8195_memif_routes; 3006 dai->num_dapm_routes = ARRAY_SIZE(mt8195_memif_routes); 3007 dai->controls = mt8195_memif_controls; 3008 dai->num_controls = ARRAY_SIZE(mt8195_memif_controls); 3009 3010 return init_memif_priv_data(afe); 3011 } 3012 3013 typedef int (*dai_register_cb)(struct mtk_base_afe *); 3014 static const dai_register_cb dai_register_cbs[] = { 3015 mt8195_dai_adda_register, 3016 mt8195_dai_etdm_register, 3017 mt8195_dai_pcm_register, 3018 mt8195_dai_memif_register, 3019 }; 3020 3021 static const struct reg_sequence mt8195_afe_reg_defaults[] = { 3022 { AFE_IRQ_MASK, 0x387ffff }, 3023 { AFE_IRQ3_CON, BIT(30) }, 3024 { AFE_IRQ9_CON, BIT(30) }, 3025 { ETDM_IN1_CON4, 0x12000100 }, 3026 { ETDM_IN2_CON4, 0x12000100 }, 3027 }; 3028 3029 static const struct reg_sequence mt8195_cg_patch[] = { 3030 { AUDIO_TOP_CON0, 0xfffffffb }, 3031 { AUDIO_TOP_CON1, 0xfffffffa }, 3032 }; 3033 3034 static int mt8195_afe_init_registers(struct mtk_base_afe *afe) 3035 { 3036 return regmap_multi_reg_write(afe->regmap, 3037 mt8195_afe_reg_defaults, 3038 ARRAY_SIZE(mt8195_afe_reg_defaults)); 3039 } 3040 3041 static void mt8195_afe_parse_of(struct mtk_base_afe *afe, 3042 struct device_node *np) 3043 { 3044 #if IS_ENABLED(CONFIG_SND_SOC_MT6359) 3045 struct mt8195_afe_private *afe_priv = afe->platform_priv; 3046 3047 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(afe->dev->of_node, 3048 "mediatek,topckgen"); 3049 if (IS_ERR(afe_priv->topckgen)) { 3050 dev_info(afe->dev, "%s() Cannot find topckgen controller: %ld\n", 3051 __func__, PTR_ERR(afe_priv->topckgen)); 3052 } 3053 #endif 3054 } 3055 3056 static int mt8195_afe_pcm_dev_probe(struct platform_device *pdev) 3057 { 3058 struct mtk_base_afe *afe; 3059 struct mt8195_afe_private *afe_priv; 3060 struct device *dev = &pdev->dev; 3061 int i, irq_id, ret; 3062 struct snd_soc_component *component; 3063 3064 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(33)); 3065 if (ret) 3066 return ret; 3067 3068 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 3069 if (!afe) 3070 return -ENOMEM; 3071 3072 afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), 3073 GFP_KERNEL); 3074 if (!afe->platform_priv) 3075 return -ENOMEM; 3076 3077 afe_priv = afe->platform_priv; 3078 afe->dev = &pdev->dev; 3079 3080 afe->base_addr = devm_platform_ioremap_resource(pdev, 0); 3081 if (IS_ERR(afe->base_addr)) 3082 return PTR_ERR(afe->base_addr); 3083 3084 /* initial audio related clock */ 3085 ret = mt8195_afe_init_clock(afe); 3086 if (ret) { 3087 dev_err(dev, "init clock error\n"); 3088 return ret; 3089 } 3090 3091 spin_lock_init(&afe_priv->afe_ctrl_lock); 3092 3093 mutex_init(&afe->irq_alloc_lock); 3094 3095 /* irq initialize */ 3096 afe->irqs_size = MT8195_AFE_IRQ_NUM; 3097 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 3098 GFP_KERNEL); 3099 if (!afe->irqs) 3100 return -ENOMEM; 3101 3102 for (i = 0; i < afe->irqs_size; i++) 3103 afe->irqs[i].irq_data = &irq_data_array[i]; 3104 3105 /* init memif */ 3106 afe->memif_size = MT8195_AFE_MEMIF_NUM; 3107 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 3108 GFP_KERNEL); 3109 if (!afe->memif) 3110 return -ENOMEM; 3111 3112 for (i = 0; i < afe->memif_size; i++) { 3113 afe->memif[i].data = &memif_data[i]; 3114 afe->memif[i].irq_usage = mt8195_afe_memif_const_irqs[i]; 3115 afe->memif[i].const_irq = 1; 3116 afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true; 3117 } 3118 3119 /* request irq */ 3120 irq_id = platform_get_irq(pdev, 0); 3121 if (irq_id < 0) { 3122 dev_err(dev, "%s no irq found\n", dev->of_node->name); 3123 return -ENXIO; 3124 } 3125 3126 ret = devm_request_irq(dev, irq_id, mt8195_afe_irq_handler, 3127 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); 3128 if (ret) { 3129 dev_err(dev, "could not request_irq for asys-isr\n"); 3130 return ret; 3131 } 3132 3133 /* init sub_dais */ 3134 INIT_LIST_HEAD(&afe->sub_dais); 3135 3136 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 3137 ret = dai_register_cbs[i](afe); 3138 if (ret) { 3139 dev_warn(dev, "dai register i %d fail, ret %d\n", 3140 i, ret); 3141 return ret; 3142 } 3143 } 3144 3145 /* init dai_driver and component_driver */ 3146 ret = mtk_afe_combine_sub_dai(afe); 3147 if (ret) { 3148 dev_warn(dev, "mtk_afe_combine_sub_dai fail, ret %d\n", 3149 ret); 3150 return ret; 3151 } 3152 3153 afe->mtk_afe_hardware = &mt8195_afe_hardware; 3154 afe->memif_fs = mt8195_memif_fs; 3155 afe->irq_fs = mt8195_irq_fs; 3156 3157 afe->runtime_resume = mt8195_afe_runtime_resume; 3158 afe->runtime_suspend = mt8195_afe_runtime_suspend; 3159 3160 platform_set_drvdata(pdev, afe); 3161 3162 mt8195_afe_parse_of(afe, pdev->dev.of_node); 3163 3164 pm_runtime_enable(dev); 3165 if (!pm_runtime_enabled(dev)) { 3166 ret = mt8195_afe_runtime_resume(dev); 3167 if (ret) 3168 return ret; 3169 } 3170 3171 /* enable clock for regcache get default value from hw */ 3172 afe_priv->pm_runtime_bypass_reg_ctl = true; 3173 pm_runtime_get_sync(dev); 3174 3175 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, 3176 &mt8195_afe_regmap_config); 3177 if (IS_ERR(afe->regmap)) { 3178 ret = PTR_ERR(afe->regmap); 3179 goto err_pm_put; 3180 } 3181 3182 ret = regmap_register_patch(afe->regmap, mt8195_cg_patch, 3183 ARRAY_SIZE(mt8195_cg_patch)); 3184 if (ret < 0) { 3185 dev_err(dev, "Failed to apply cg patch\n"); 3186 goto err_pm_put; 3187 } 3188 3189 /* register component */ 3190 ret = devm_snd_soc_register_component(dev, &mt8195_afe_component, 3191 NULL, 0); 3192 if (ret) { 3193 dev_warn(dev, "err_platform\n"); 3194 goto err_pm_put; 3195 } 3196 3197 component = devm_kzalloc(dev, sizeof(*component), GFP_KERNEL); 3198 if (!component) { 3199 ret = -ENOMEM; 3200 goto err_pm_put; 3201 } 3202 3203 ret = snd_soc_component_initialize(component, 3204 &mt8195_afe_pcm_dai_component, 3205 dev); 3206 if (ret) 3207 goto err_pm_put; 3208 3209 #ifdef CONFIG_DEBUG_FS 3210 component->debugfs_prefix = "pcm"; 3211 #endif 3212 3213 ret = snd_soc_add_component(component, 3214 afe->dai_drivers, 3215 afe->num_dai_drivers); 3216 if (ret) { 3217 dev_warn(dev, "err_dai_component\n"); 3218 goto err_pm_put; 3219 } 3220 3221 mt8195_afe_init_registers(afe); 3222 3223 pm_runtime_put_sync(dev); 3224 afe_priv->pm_runtime_bypass_reg_ctl = false; 3225 3226 regcache_cache_only(afe->regmap, true); 3227 regcache_mark_dirty(afe->regmap); 3228 3229 return 0; 3230 3231 err_pm_put: 3232 pm_runtime_put_sync(dev); 3233 pm_runtime_disable(dev); 3234 3235 return ret; 3236 } 3237 3238 static int mt8195_afe_pcm_dev_remove(struct platform_device *pdev) 3239 { 3240 struct mtk_base_afe *afe = platform_get_drvdata(pdev); 3241 3242 snd_soc_unregister_component(&pdev->dev); 3243 3244 pm_runtime_disable(&pdev->dev); 3245 if (!pm_runtime_status_suspended(&pdev->dev)) 3246 mt8195_afe_runtime_suspend(&pdev->dev); 3247 3248 mt8195_afe_deinit_clock(afe); 3249 return 0; 3250 } 3251 3252 static const struct of_device_id mt8195_afe_pcm_dt_match[] = { 3253 {.compatible = "mediatek,mt8195-audio", }, 3254 {}, 3255 }; 3256 MODULE_DEVICE_TABLE(of, mt8195_afe_pcm_dt_match); 3257 3258 static const struct dev_pm_ops mt8195_afe_pm_ops = { 3259 SET_RUNTIME_PM_OPS(mt8195_afe_runtime_suspend, 3260 mt8195_afe_runtime_resume, NULL) 3261 }; 3262 3263 static struct platform_driver mt8195_afe_pcm_driver = { 3264 .driver = { 3265 .name = "mt8195-audio", 3266 .of_match_table = mt8195_afe_pcm_dt_match, 3267 .pm = &mt8195_afe_pm_ops, 3268 }, 3269 .probe = mt8195_afe_pcm_dev_probe, 3270 .remove = mt8195_afe_pcm_dev_remove, 3271 }; 3272 3273 module_platform_driver(mt8195_afe_pcm_driver); 3274 3275 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8195"); 3276 MODULE_AUTHOR("Bicycle Tsai <bicycle.tsai@mediatek.com>"); 3277 MODULE_LICENSE("GPL v2"); 3278